JPH07176751A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07176751A JPH07176751A JP32282393A JP32282393A JPH07176751A JP H07176751 A JPH07176751 A JP H07176751A JP 32282393 A JP32282393 A JP 32282393A JP 32282393 A JP32282393 A JP 32282393A JP H07176751 A JPH07176751 A JP H07176751A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- region
- substrate
- interlayer insulating
- connection hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Thin Film Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
ＳＯＩ半導体装置における基板電位付与構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a substrate potential applying structure in an SOI semiconductor device.
【０００２】[0002]
【従来の技術】半導体基板上に埋込絶縁体層を挟んで配
設されるとともに側面が側壁分離絶縁領域に接する複数
の単結晶島状半導体領域と、島状半導体領域及び側壁分
離絶縁領域上に配設された層間絶縁膜とを有するいわゆ
るＳＯＩ構造の従来の半導体装置では、基板電位付与の
ために基板の裏面全面に電極を設けるのが通例である
が、この方法では裏面電極形成工程が必要となる点、及
び、基板全体が同電位となり基板のある部分のみに所定
のバイアス電位を印加することができないなどの問題が
あった。2. Description of the Related Art A plurality of single crystal island-shaped semiconductor regions, which are disposed on a semiconductor substrate with a buried insulator layer sandwiched therebetween and whose side surfaces are in contact with sidewall isolation insulating regions, and on the island-shaped semiconductor regions and sidewall isolation insulating regions. In a conventional semiconductor device having a so-called SOI structure having an interlayer insulating film disposed on the substrate, an electrode is usually provided on the entire back surface of the substrate to apply the substrate potential. There is a problem in that it is necessary and that the predetermined bias potential cannot be applied only to a certain portion of the substrate because the entire substrate has the same potential.
【０００３】この問題を解決するために、特開平２ー２
９４０７６号公報は、側壁分離絶縁領域及び埋込絶縁体
層からなる素子分離絶縁膜（フィールド絶縁膜）とその
上の層間絶縁膜とを一挙に貫孔して接続孔を形成し、こ
の接続孔を通じて層間絶縁膜上の基板電位付与用の配線
を基板に接続している。In order to solve this problem, Japanese Patent Laid-Open No. 2-2
JP-A-94076 discloses that a device isolation insulating film (field insulating film) composed of a sidewall isolation insulating region and a buried insulating layer and an interlayer insulating film formed on the device isolation insulating film are formed at once to form a connection hole. The wiring for applying the substrate potential on the interlayer insulating film is connected to the substrate through.
【０００４】[0004]
【発明が解決しようとする課題】ところが上記した公報
の基板接続方式では、この場合には、接続孔の深さがフ
イールド絶縁膜（側壁分離絶縁領域及びその直下の埋込
絶縁体層を総称してフイールド絶縁膜ともいう）及び層
間絶縁膜の膜厚の和となり、この値は約１μｍ以上にも
なるので、この段差によって配線が段差切れし易いとい
う問題がある。However, in the substrate connection method of the above-mentioned publication, in this case, the depth of the connection hole is a generic term for the field insulating film (the side wall isolation insulating region and the buried insulating layer immediately thereunder). (Also referred to as a field insulating film) and the film thickness of the interlayer insulating film, which is as large as about 1 μm or more. Therefore, there is a problem that the step easily breaks the wiring.
【０００５】すなわち、ＳＯＩ構造の半導体装置では、
比較的厚い（薄いと基板間の寄生容量が大きくなってし
まう）埋込絶縁体層が存在するために少なくともその分
だけ従来より基板電位付与用の開口深さが増大してしま
い、必然的に基板電位付与用の配線の段差切れが生じ易
くなってしまう。本発明は上記問題点に鑑みなされたも
のであり、基板電位付与用の配線の段差切れが抑止可能
なＳＯＩ構造の半導体装置を提供することを、その目的
としている。That is, in the SOI structure semiconductor device,
Since there is a relatively thick buried insulator layer (if it is thin, the parasitic capacitance between the substrates will increase), the opening depth for applying the substrate potential will increase by at least that much, and inevitably It is easy for a step difference in the wiring for applying the substrate potential to occur. The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device having an SOI structure capable of suppressing a step difference in a wiring for applying a substrate potential.
【０００６】[0006]
【課題を解決するための手段】第１発明の半導体装置
は、半導体基板上に埋込絶縁体層を挟んで配設されると
ともに側面が側壁分離絶縁領域に接する複数の単結晶島
状半導体領域と、前記島状半導体領域及び前記側壁分離
絶縁領域上に配設された層間絶縁膜と、前記層間絶縁膜
及び前記埋込絶縁体層に開口された接続孔と、前記層間
絶縁膜上に配設されるとともに前記接続孔に充填される
基板電位付与用の配線とを備える半導体装置において、
前記接続孔は、前記島状半導体領域及びその直下の埋込
絶縁体層に開口された外孔と、前記外孔に充填された前
記層間絶縁膜に開口された内孔とからなり、前記基板電
位付与用の配線は前記内孔を通じて前記基板に接続され
ることを特徴としている。According to a first aspect of the present invention, there is provided a semiconductor device having a plurality of single crystal island-shaped semiconductor regions which are disposed on a semiconductor substrate with a buried insulator layer interposed therebetween and whose side surfaces are in contact with sidewall isolation insulating regions. An interlayer insulating film provided on the island-shaped semiconductor region and the sidewall isolation insulating region, a connection hole opened in the interlayer insulating film and the buried insulating layer, and an interlayer insulating film provided on the interlayer insulating film. In a semiconductor device provided with a wiring for applying a substrate potential filled in the connection hole
The connection hole includes an outer hole opened in the island-shaped semiconductor region and a buried insulator layer immediately below the island-shaped semiconductor region, and an inner hole opened in the interlayer insulating film filled in the outer hole. The potential applying wiring is connected to the substrate through the inner hole.
【０００７】第２発明の半導体装置は、半導体基板上に
埋込絶縁体層を挟んで配設されるとともに側面が側壁分
離絶縁領域に接する複数の単結晶島状半導体領域と、前
記島状半導体領域及び前記側壁分離絶縁領域上に配設さ
れた層間絶縁膜と、前記層間絶縁膜及び前記埋込絶縁体
層に開口された接続孔と、前記層間絶縁膜上に配設され
るとともに前記接続孔に充填される基板電位付与用の配
線とを備える半導体装置において、前記接続孔は、前記
側壁分離絶縁領域及びその直下の埋込絶縁体層に開口さ
れた外孔と、前記外孔に充填された前記層間絶縁膜に開
口された内孔とからなり、前記基板電位付与用の配線は
前記内孔を通じて前記基板に接続されることを特徴とし
ている。A semiconductor device according to a second aspect of the present invention includes a plurality of single crystal island-shaped semiconductor regions which are disposed on a semiconductor substrate with a buried insulator layer interposed therebetween and whose side surfaces are in contact with sidewall isolation insulating regions, and the island-shaped semiconductor. Region and an interlayer insulating film provided on the sidewall isolation insulating region, a connection hole opened in the interlayer insulating film and the buried insulator layer, and the connection provided on the interlayer insulating film In a semiconductor device having a wiring for applying a substrate potential, which is filled in the hole, the connection hole includes an outer hole opened in the sidewall isolation insulating region and a buried insulator layer immediately below the sidewall insulating region, and the outer hole. It is characterized in that the wiring for applying the substrate potential is connected to the substrate through the inner hole.
【０００８】[0008]
【作用及び発明の効果】両発明はＳＯＩ半導体装置であ
って、各島状半導体領域の底面は埋込絶縁体層により、
その側面は側壁分離絶縁領域により絶縁分離されてい
る。島状半導体領域の表面に配設された配線は層間絶縁
膜により各島状半導体領域から絶縁分離される。Both of the inventions are SOI semiconductor devices in which the bottom surface of each island-shaped semiconductor region is formed by a buried insulator layer.
The side surface is insulated and separated by the side wall isolation insulating region. The wiring provided on the surface of the island-shaped semiconductor region is insulated and separated from each island-shaped semiconductor region by the interlayer insulating film.
【０００９】第１発明の半導体装置では、島状半導体領
域及びその直下の埋込絶縁体層に開口された外孔に充填
された層間絶縁膜を開口して内孔が形成され、基板電位
付与用の配線はこの内孔を通じて基板に接続される。第
２発明の半導体装置では、側壁分離絶縁領域及びその直
下の埋込絶縁体層に開口された外孔に充填された層間絶
縁膜を開口して内孔が形成され、基板電位付与用の配線
はこの内孔を通じて基板に接続される。In the semiconductor device according to the first aspect of the present invention, the inner hole is formed by opening the interlayer insulating film filled in the outer hole formed in the island-shaped semiconductor region and the buried insulating layer immediately thereunder, and the substrate potential is applied. The wiring for use is connected to the substrate through this inner hole. In the semiconductor device of the second aspect of the present invention, the inner wall is formed by opening the interlayer insulating film filled in the outer hole formed in the sidewall isolation insulating region and the buried insulating layer immediately thereunder, and the wiring for applying the substrate potential. Is connected to the substrate through this inner hole.
【００１０】すなわちこれら両発明によれば、基板電位
付与用の接続孔を外孔及び内孔の２段開口により構成す
ることになるので、上記従来のＳＯＩ半導体装置におけ
る基板電位付与用の接続孔に比較して段差が格段に低減
され、その結果、配線の段差切れが防止できる。That is, according to both of these inventions, since the connection hole for applying the substrate potential is constituted by the two-stage opening of the outer hole and the inner hole, the connection hole for applying the substrate potential in the conventional SOI semiconductor device described above. Compared with the above, the step difference is remarkably reduced, and as a result, it is possible to prevent the step difference of the wiring.
【００１１】[0011]
（実施例１）図１に本発明の第１の実施例を示す。シリ
コン基板１上に埋め込み酸化膜（本発明でいう埋込絶縁
体層）２を介して単結晶シリコン層（本発明でいう単結
晶島状半導体領域、以下ＳＯＩ層ともいう）３が形成さ
れ、ＳＯＩ層３には、ゲート絶縁膜４、ゲート電極５、
層間絶縁膜６、配線７から成るＭＯＳＦＥＴが形成され
ている。ここでＭＯＳＦＥＴを形成しないＳＯＩ層（島
状半導体領域）３Ａの内側に形成された第１の接続孔
（本発明でいう外孔）８において層間絶縁膜６とシリコ
ン基板１とが接触している。さらに、第１の接続孔８の
内側に位置して層間絶縁膜６を開口して形成された第２
の接続孔（本発明でいう内孔）９において配線７Ａとシ
リコン基板１とが接触している。(Embodiment 1) FIG. 1 shows a first embodiment of the present invention. A single crystal silicon layer (single crystal island semiconductor region in the present invention, hereinafter also referred to as an SOI layer) 3 is formed on a silicon substrate 1 with a buried oxide film (the buried insulating layer in the present invention) 2 interposed therebetween, The SOI layer 3 includes a gate insulating film 4, a gate electrode 5,
A MOSFET including the interlayer insulating film 6 and the wiring 7 is formed. Here, the interlayer insulating film 6 and the silicon substrate 1 are in contact with each other in the first connection hole (outer hole in the present invention) 8 formed inside the SOI layer (island-shaped semiconductor region) 3A where the MOSFET is not formed. . Further, the second insulating film 6 is formed inside the first connection hole 8 and is formed by opening the interlayer insulating film 6.
The wiring 7A and the silicon substrate 1 are in contact with each other in the connection hole 9 (inner hole in the present invention).
【００１２】このようにすれば、第１の接続孔８の段差
はｄ2 ＋ｄ3 となる。ｄ2 はＳＯＩ層３Ａの膜厚に相当
し通常１００ｎｍ以下であり、ｄ3 は埋め込み酸化膜２
の膜厚に相当し通常１００〜４００ｎｍ程度であるため
ｄ2 ＋ｄ3 の値は５００ｎｍ程度以下となり、本段差は
ＭＯＳＦＥＴのゲート電極による段差とほぼ同程度以下
となる。また、第１の接続孔８を形成後、その段差上に
形成される層間絶縁膜６のリフロー処理により、接続孔
８の段差上における層間絶縁膜６の表面の段差は緩和さ
れ、そ上に配設される配線７Ａの段差は大幅に緩和さ
れ、その段差切れが防止される。In this way, the step difference of the first connection hole 8 becomes d 2 + d 3 . d 2 corresponds to the film thickness of the SOI layer 3 A and is usually 100 nm or less, and d 3 represents the buried oxide film 2
Corresponding to the film thickness of 100 to 400 nm, and the value of d 2 + d 3 is about 500 nm or less, and this step is about the same or less than the step due to the gate electrode of the MOSFET. Further, after the first connection hole 8 is formed, the step of the surface of the interlayer insulation film 6 on the step of the connection hole 8 is relaxed by the reflow treatment of the interlayer insulation film 6 formed on the step, and the first step is formed on the step. The step difference of the provided wiring 7A is significantly reduced, and the step difference is prevented from being broken.
【００１３】次に、第２の接続孔９における段差ｄ1 は
層間絶縁膜６の膜厚による段差であり、ＭＯＳＦＥＴの
コンタクトホール１１における段差と全く同一形状とな
ることから、本段差において配線７Ａが断線することも
ない。以下図２〜図５を参照して、上記装置の製造工程
について説明する。まず図２に示すように、公知の方法
によりシリコン基板１上に埋め込み酸化膜２を介して単
結晶シリコン層を形成し、この単結晶シリコン層の所定
領域を例えばＬＯＣＯＳ酸化により側壁分離絶縁領域１
０を形成して、残りを単結晶シリコン層（島状半導体領
域）３、３Ａとし、ゲート絶縁膜４、ゲート電極５を順
次形成する。なお、埋め込み酸化膜２及びその直上の側
壁分離絶縁領域１０を素子分離絶縁膜（フィールド酸化
膜）１２と総称する。Next, the step d 1 in the second connection hole 9 is a step due to the film thickness of the interlayer insulating film 6 and has exactly the same shape as the step in the contact hole 11 of the MOSFET. Will not be disconnected. The manufacturing process of the above device will be described below with reference to FIGS. First, as shown in FIG. 2, a single crystal silicon layer is formed on a silicon substrate 1 through a buried oxide film 2 by a known method, and a predetermined region of the single crystal silicon layer is formed by sidewall oxidation insulation region 1 by, for example, LOCOS oxidation.
0 is formed, and the rest is formed into single crystal silicon layers (island semiconductor regions) 3 and 3A, and a gate insulating film 4 and a gate electrode 5 are sequentially formed. The buried oxide film 2 and the sidewall isolation insulating region 10 immediately above it are collectively referred to as an element isolation insulating film (field oxide film) 12.
【００１４】次に図３に示すように、第２の接続孔形成
予定領域を含み、しかもこの予定領域よりも広範囲の単
結晶シリコン層３Ａ及び埋め込み酸化膜２を通常のフォ
トリソグラフィ及びエッチング技術によりエッチング除
去することにより、第１の接続孔８を形成してシリコン
基板１の表面を露出させる。その後、本図中には示さな
いものの、ゲート電極用の側壁形成を行った場合には第
１の接続孔８による段差部にも同時に側壁が形成され
る。Next, as shown in FIG. 3, the single crystal silicon layer 3A and the buried oxide film 2 including the second connection hole formation planned region and wider than the planned region are formed by the usual photolithography and etching techniques. By removing by etching, the first connection hole 8 is formed and the surface of the silicon substrate 1 is exposed. After that, although not shown in the figure, when the side wall for the gate electrode is formed, the side wall is also formed at the step portion by the first connection hole 8 at the same time.
【００１５】次に図４に示すように、単結晶シリコン層
３に形成する基板と同一導電型のＭＯＳＦＥＴのソース
・ドレインを形成する不純物１３′をイオン注入する際
に、上記第１の接続孔８によって露出されたシリコン基
板１の表面にも同時に不純物１３′をイオン注入して、
ソース・ドレイン領域１３及び高濃度不純物領域１４を
形成する。この時、ソース・ドレイン領域１３の表面に
薄い酸化膜が形成されている場合には、第１の接続孔８
により露出されたシリコン基板１の表面部分にも同様に
酸化膜が形成されている。Next, as shown in FIG. 4, when the impurities 13 'forming the source / drain of the MOSFET of the same conductivity type as the substrate formed on the single crystal silicon layer 3 are ion-implanted, the first connection hole is formed. Impurities 13 'are simultaneously ion-implanted into the surface of the silicon substrate 1 exposed by 8,
A source / drain region 13 and a high concentration impurity region 14 are formed. At this time, when a thin oxide film is formed on the surface of the source / drain region 13, the first connection hole 8
An oxide film is also formed on the surface portion of the silicon substrate 1 exposed by.
【００１６】次に図５に示すように、層間絶縁膜６を形
成してから熱処理を行うことにより層間絶縁膜６をリフ
ローして表面をなだらかにするとともにＭＯＳＦＥＴの
ソース・ドレイン領域１３及び高濃度不純物１４にイオ
ン注入された不純物１３′を活性化する。その後、単結
晶シリコン層３にコンタクトホール１１を形成すると同
時に、第１の接続孔８の内側に第２の接続孔９を形成し
て再びシリコン基板１の表面を露出させる。したがっ
て、層間絶縁膜６はリンガラスなどが用いられることが
好ましいがＣＶＤシリコン酸化膜などでもよい。Next, as shown in FIG. 5, after the interlayer insulating film 6 is formed, heat treatment is performed to reflow the interlayer insulating film 6 so that the surface is smoothed and the source / drain regions 13 and high concentration of the MOSFET are formed. The impurity 13 'ion-implanted into the impurity 14 is activated. Then, the contact hole 11 is formed in the single crystal silicon layer 3, and at the same time, the second connection hole 9 is formed inside the first connection hole 8 to expose the surface of the silicon substrate 1 again. Therefore, the interlayer insulating film 6 is preferably made of phosphorus glass or the like, but may be a CVD silicon oxide film or the like.
【００１７】次に図１に示すように、配線７、７Ａを形
成することにより図１に示す構造が完成する。本実施例
によれば、ＳＯＩ構造を有する半導体装置において層間
絶縁膜上の基板電位付与用の配線を基板に接続するため
の接続孔に複数の段差を与えたので、配線の断線を防止
することができる。Next, as shown in FIG. 1, wirings 7 and 7A are formed to complete the structure shown in FIG. According to the present embodiment, in the semiconductor device having the SOI structure, the connection holes for connecting the wiring for applying the substrate potential on the interlayer insulating film to the substrate are provided with a plurality of steps, so that the disconnection of the wiring can be prevented. You can
【００１８】また、電気的に良好にコンタクトを形成す
る為には配線と接触する基板表面部分に高濃度に不純物
をドーピングする必要があるが、本実施例によれば、こ
のドーピングをＭＯＳＦＥＴのソース・ドレイン等の不
純物ドーピング工程で同時に行うので、製造工程を簡略
化することができる。 （実施例２）本発明の第２の実施例を図６を参照して説
明する。Further, in order to form a good electrical contact, it is necessary to dope the substrate surface portion in contact with the wiring with a high concentration of impurities. According to the present embodiment, this doping is performed by the source of the MOSFET. -Since it is performed simultaneously with the impurity doping process for the drain and the like, the manufacturing process can be simplified. (Embodiment 2) A second embodiment of the present invention will be described with reference to FIG.
【００１９】この実施例では、埋込絶縁体層２と、埋込
絶縁体層２上の単結晶シリコン層をＬＯＣＯＳ酸化して
形成された側壁分離絶縁領域１０とからなる素子分離絶
縁膜（フィールド酸化膜）１２を開口して第１の接続孔
８Ａを形成する点が、第１の実施例と異なっている。本
実施例における第１の接続孔８Ａにおける段差ｄｄ2 は
素子分離絶縁膜１２の膜厚（ｄｄ2 ）に相当するが、ｄ
ｄ2 の値を小さくすることはゲート電極配線の寄生容量
が大きくなり、素子の動作速度が遅くなり、消費電力が
増加する等の問題を招き、ｄｄ2 の値を上記ｄ2 ＋ｄ3
の値よりも小さくすることはできない。従ってこの実施
例の第１の接続孔８Ａによる段差は、第１の実施例の第
１の接続孔８による段差よりも大きくなる。しかし、図
７に示した従来構造の接続孔の段差は素子分離絶縁膜１
２（埋込絶縁体層２及び側壁分離絶縁領域１０）の膜厚
（Ｄ2 ）と層間絶縁膜６の膜厚（Ｄ1 ）との和となるこ
とを考えれば、格段の段差低減を実現することができ、
断線を防止することができる。In this embodiment, an element isolation insulating film (field) formed of a buried insulating layer 2 and a sidewall isolation insulating region 10 formed by LOCOS oxidation of a single crystal silicon layer on the buried insulating layer 2 is used. This is different from the first embodiment in that the oxide film) 12 is opened to form the first connection hole 8A. The step dd 2 in the first connection hole 8A in this embodiment corresponds to the film thickness (dd 2 ) of the element isolation insulating film 12,
Reducing the value of d 2 causes a problem that the parasitic capacitance of the gate electrode wiring increases, the operation speed of the element slows down, and the power consumption increases, and the value of dd 2 is set to the above d 2 + d 3
Cannot be less than the value of. Therefore, the step due to the first connection hole 8A in this embodiment is larger than the step due to the first connection hole 8 in the first embodiment. However, the step difference of the connection hole of the conventional structure shown in FIG.
2 Given that the sum of the thickness (D 2) and the thickness of the interlayer insulating film 6 (buried insulator layer 2 and the sidewall isolation region 10) (D 1), realizing remarkable step difference reduction You can
It is possible to prevent disconnection.
【図１】本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】図１の半導体装置の製造工程を示す断面図であ
る。FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor device of FIG.
【図３】図１の半導体装置の製造工程を示す断面図であ
る。FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device of FIG.
【図４】図１の半導体装置の製造工程を示す断面図であ
る。FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device of FIG.
【図５】図１の半導体装置の製造工程を示す断面図であ
る。FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device of FIG.
【図６】本発明の他実施例を示す断面図である。FIG. 6 is a sectional view showing another embodiment of the present invention.
【図７】従来の装置構造を示す断面図である。FIG. 7 is a cross-sectional view showing a conventional device structure.
１はシリコン基板（半導体基板）、２は埋め込み酸化膜
（埋込絶縁体層）、３Ａは多結晶シリコン層（島状半導
体領域）、６は層間絶縁膜、７Ａは配線、８は第１の接
続孔（外孔）、９は第２の接続孔（内孔）、１２は素子
分離絶縁領域（側壁分離絶縁領域及びその直下の埋込絶
縁体層）。1 is a silicon substrate (semiconductor substrate), 2 is a buried oxide film (buried insulator layer), 3A is a polycrystalline silicon layer (island semiconductor region), 6 is an interlayer insulating film, 7A is wiring, and 8 is a first A connection hole (outer hole), 9 is a second connection hole (inner hole), and 12 is an element isolation insulating region (sidewall isolation insulating region and a buried insulator layer immediately below it).
Claims (2)
されるとともに側面が側壁分離絶縁領域に接する複数の
単結晶島状半導体領域と、前記島状半導体領域及び前記
側壁分離絶縁領域上に配設された層間絶縁膜と、前記層
間絶縁膜及び前記埋込絶縁体層に開口された接続孔と、
前記層間絶縁膜上に配設されるとともに前記接続孔に充
填される基板電位付与用の配線とを備える半導体装置に
おいて、 前記接続孔は、前記島状半導体領域及びその直下の埋込
絶縁体層に開口された外孔と、前記外孔に充填された前
記層間絶縁膜に開口された内孔とからなり、 前記基板電位付与用の配線は前記内孔を通じて前記基板
に接続されることを特徴とする半導体装置。1. A plurality of single crystal island-shaped semiconductor regions, which are arranged on a semiconductor substrate with a buried insulator layer sandwiched therebetween and whose side surfaces are in contact with the sidewall isolation insulating regions, the island-shaped semiconductor regions and the sidewall isolation insulating regions. An interlayer insulating film disposed on the region, a connection hole opened in the interlayer insulating film and the embedded insulator layer,
In a semiconductor device provided on the interlayer insulating film and comprising a wiring for applying a substrate potential, which fills the connection hole, the connection hole includes the island-shaped semiconductor region and a buried insulator layer directly below the island-shaped semiconductor region. And an inner hole opened in the interlayer insulating film filled in the outer hole, wherein the wiring for applying the substrate potential is connected to the substrate through the inner hole. Semiconductor device.
されるとともに側面が側壁分離絶縁領域に接する複数の
単結晶島状半導体領域と、前記島状半導体領域及び前記
側壁分離絶縁領域上に配設された層間絶縁膜と、前記層
間絶縁膜及び前記埋込絶縁体層に開口された接続孔と、
前記層間絶縁膜上に配設されるとともに前記接続孔に充
填される基板電位付与用の配線とを備える半導体装置に
おいて、 前記接続孔は、前記側壁分離絶縁領域及びその直下の埋
込絶縁体層に開口された外孔と、前記外孔に充填された
前記層間絶縁膜に開口された内孔とからなり、 前記基板電位付与用の配線は前記内孔を通じて前記基板
に接続されることを特徴とする半導体装置。2. A plurality of single crystal island-shaped semiconductor regions which are disposed on a semiconductor substrate with a buried insulator layer sandwiched therebetween and whose side surfaces are in contact with the sidewall isolation insulating region, the island-shaped semiconductor region and the sidewall isolation insulating region. An interlayer insulating film disposed on the region, a connection hole opened in the interlayer insulating film and the embedded insulator layer,
In a semiconductor device, which is provided on the interlayer insulating film and comprises a wiring for applying a substrate potential, which fills the connection hole, the connection hole includes the sidewall isolation insulating region and a buried insulator layer immediately below the sidewall insulating region. And an inner hole opened in the interlayer insulating film filled in the outer hole, wherein the wiring for applying the substrate potential is connected to the substrate through the inner hole. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32282393A JP3264402B2 (en) | 1993-12-21 | 1993-12-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32282393A JP3264402B2 (en) | 1993-12-21 | 1993-12-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07176751A true JPH07176751A (en) | 1995-07-14 |
| JP3264402B2 JP3264402B2 (en) | 2002-03-11 |
Family
ID=18148012
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32282393A Expired - Lifetime JP3264402B2 (en) | 1993-12-21 | 1993-12-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3264402B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6566713B2 (en) | 2000-09-27 | 2003-05-20 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| JP2007165568A (en) * | 2005-12-14 | 2007-06-28 | Oki Electric Ind Co Ltd | Method of manufacturing semiconductor device |
-
1993
- 1993-12-21 JP JP32282393A patent/JP3264402B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6566713B2 (en) | 2000-09-27 | 2003-05-20 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| JP2007165568A (en) * | 2005-12-14 | 2007-06-28 | Oki Electric Ind Co Ltd | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3264402B2 (en) | 2002-03-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5442223A (en) | Semiconductor device with stress relief | |
| US5930648A (en) | Semiconductor memory device having different substrate thickness between memory cell area and peripheral area and manufacturing method thereof | |
| JP2812388B2 (en) | Method of manufacturing SOI semiconductor device | |
| JPH0870105A (en) | Semiconductor device and its fabrication | |
| JPH09129877A (en) | Manufacture of semiconductor device, manufacture of insulated gate semiconductor device, and insulated gate semiconductor device | |
| JPS60234372A (en) | Manufacture of semiconductor device | |
| JPH0799286A (en) | Semiconductor device | |
| KR960016824B1 (en) | Semiconductor device and method thereof | |
| KR100344913B1 (en) | Method of manufacturing semiconductor device | |
| JP3264402B2 (en) | Semiconductor device | |
| JP2002076113A (en) | Semiconductor device and its manufacturing method | |
| JP2839088B2 (en) | Semiconductor device | |
| JP3588882B2 (en) | Manufacturing method of dielectric isolation substrate | |
| JPS61172346A (en) | Semiconductor integrated circuit device | |
| JPH0426162A (en) | Floating gate semiconductor memory and manufacture thereof | |
| JPS61288460A (en) | Semiconductor memory device and manufacture thereof | |
| JPH0265274A (en) | Thin film transistor | |
| JP3031137B2 (en) | Insulator-isolated semiconductor device | |
| JPS60148147A (en) | Semiconductor device | |
| JP2950620B2 (en) | Semiconductor device | |
| KR100200747B1 (en) | Device isolation method in silicon processing | |
| JPH1197522A (en) | Dielectric isolation substrate and manufacture therefor | |
| JPH11345884A (en) | Manufacture of semiconductor device and structure thereof | |
| JPH03112151A (en) | Active layer stacked element | |
| JPH10107292A (en) | Fabrication of soi semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 6 Free format text: PAYMENT UNTIL: 20071228 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 9 Free format text: PAYMENT UNTIL: 20101228 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 10 Free format text: PAYMENT UNTIL: 20111228 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 11 Free format text: PAYMENT UNTIL: 20121228 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 12 Free format text: PAYMENT UNTIL: 20131228 |
|
| EXPY | Cancellation because of completion of term |