JPH07140475A - Wiring structure of liquid crystal display device - Google Patents
Wiring structure of liquid crystal display deviceInfo
- Publication number
- JPH07140475A JPH07140475A JP28704993A JP28704993A JPH07140475A JP H07140475 A JPH07140475 A JP H07140475A JP 28704993 A JP28704993 A JP 28704993A JP 28704993 A JP28704993 A JP 28704993A JP H07140475 A JPH07140475 A JP H07140475A
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- Japan
- Prior art keywords
- layer
- glass substrate
- plating
- wiring
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は液晶表示装置に関し、特
に、電気抵抗を低減させた液晶表示装置の配線構造に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a wiring structure of a liquid crystal display device having reduced electric resistance.
【0002】[0002]
【従来の技術】液晶表示装置において、高い解像度並び
に精細な映像の表示が要求される分野では、複数の画素
電極と画素電極ごとにスイッチング素子を配置してそれ
ぞれの画素電極を切換え駆動するアクテイブマトリック
ス型液晶表示装置が一般に使用されている。アクテイブ
マトリックス型液晶表示装置では、その大型化及び高精
細化の要求に伴う表示画面内の配線電極数の増化によ
り、信号配線幅を減少させることが求められているのだ
が、この場合、単に信号配線幅を細くしただけでは電圧
降下により所要の画面表示上の品質が得られないため、
信号配線の微細化と共に配線材料の電気抵抗を低減させ
ることが必要である。2. Description of the Related Art In a liquid crystal display device, in a field where high resolution and fine image display are required, a plurality of pixel electrodes and an active matrix for arranging a switching element for each pixel electrode and switching and driving each pixel electrode. Type liquid crystal display devices are commonly used. In the active matrix type liquid crystal display device, it is required to reduce the signal wiring width by increasing the number of wiring electrodes in the display screen in response to the demand for larger size and higher definition, but in this case, simply Since the required screen display quality cannot be obtained due to the voltage drop just by narrowing the signal wiring width,
It is necessary to reduce the electric resistance of the wiring material together with the miniaturization of the signal wiring.
【0003】アクテイブマトリックス型液晶表示装置の
信号配線の金属材料として、薄膜比抵抗値が約200μ
Ω・cmであるTi、同約25−200μΩ・cmであ
るTa、同約20−50μΩ・cmであるCr、同約5
0μΩ・cmであるMo、同約50μΩ・cmであるM
o−Ta合金、並びに、同約4μΩ・cmであるAl等
が利用可能である。とりわけAlはその薄膜比抵抗値が
上記の材料中で最も低いことから、従来、Alが主要な
配線材料として広く使用されている。As a metal material of a signal wiring of an active matrix type liquid crystal display device, a thin film specific resistance value is about 200 μm.
Ω · cm, Ti: about 25-200 μΩ · cm, Ta: about 20-50 μΩ · cm, Cr: about 5
Mo which is 0 μΩ · cm, M which is about 50 μΩ · cm
It is possible to use an o-Ta alloy as well as Al having the same concentration of about 4 μΩ · cm. Particularly, since Al has the lowest thin film resistivity among the above materials, Al has been widely used as a main wiring material.
【0004】信号配線としてAlを用いてアクテイブマ
トリックス型液晶表示装置の信号配線を形成する場合、
図4に示すように、ガラス基板1上に、例えばAl層を
スパッタにより成膜し、これを所要のパターンにウエッ
トエッチングしてAl配線層5を形成している。このA
l配線層上には一般に絶縁層としての窒化珪素(SiN
x)膜10が被覆形成されている。When forming a signal wiring of an active matrix type liquid crystal display device using Al as a signal wiring,
As shown in FIG. 4, for example, an Al layer is formed on the glass substrate 1 by sputtering, and this is wet-etched into a desired pattern to form an Al wiring layer 5. This A
In general, silicon nitride (SiN) as an insulating layer is formed on the wiring layer.
x) The film 10 is formed by coating.
【0005】[0005]
【発明が解決しようとする課題】しかし、上記の従来の
Al配線層5を用いた配線構造の場合、その絶縁層10
を形成する窒化珪素はプラズマCVD法により約300
℃の高温で堆積されるので、既に形成されているAl配
線層はこの高温処理に際しての熱によりその表面に微細
な突起としての、いわゆるヒロックが発生してしまう問
題があった。このヒロックは、場合によっては、配線の
交差部で配線層間に形成された窒化珪素の絶縁層を貫通
する場合、配線層間の短絡を引き起こす原因となる。更
に、上記従来のAl配線層及び窒化珪素絶縁層は一般
に、図示しない、薄膜型トランジスタ(TFT)素子の
形成と同時に形成されるのだが、この場合もTFT素子
のAlゲート電極とソースまたはドレーン電極との間で
もこれらの間に設けられた窒化珪素層を介してAl層の
ヒロックの突起により短絡が生じてしまう問題があっ
た。However, in the case of the wiring structure using the conventional Al wiring layer 5 as described above, the insulating layer 10 is used.
The silicon nitride forming
Since the Al wiring layer which has already been formed is deposited at a high temperature of .degree. C., there is a problem that so-called hillocks as fine projections are generated on the surface of the Al wiring layer which has already been formed by the heat at the time of this high temperature treatment. In some cases, the hillocks cause a short circuit between the wiring layers when penetrating the insulating layer of silicon nitride formed between the wiring layers at the intersections of the wirings. Further, the conventional Al wiring layer and the silicon nitride insulating layer are generally formed at the same time as the formation of a thin film transistor (TFT) element (not shown). In this case as well, the Al gate electrode and the source or drain electrode of the TFT element are formed. Also, there is a problem that a short circuit occurs due to the hillock projection of the Al layer via the silicon nitride layer provided between them.
【0006】他方、配線用の金属材料としてAlに代え
て、Alよりもより低い薄膜比抵抗値2.5Ω・cmを
有するCuの使用も注目されているのだが、Cuはガラ
ス基板との密着性が劣ること、並びにドライエッチング
による加工が困難であること等から未だ実用化には至っ
ていない。従って、本発明の目的は、配線層及びその保
護層をドライエッチングを行うことなく簡易に形成した
液晶表示装置の配線構造を提供することにある。On the other hand, the use of Cu having a thin film specific resistance value of 2.5 Ω · cm, which is lower than that of Al, as a metal material for wiring has attracted attention, but Cu adheres to a glass substrate. Since it is inferior in properties and it is difficult to process by dry etching, it has not yet been put to practical use. Therefore, an object of the present invention is to provide a wiring structure of a liquid crystal display device in which a wiring layer and its protective layer are easily formed without performing dry etching.
【0007】[0007]
【課題を解決するための手段】上記課題を達成するた
め、本発明の液晶表示装置の配線構造は、絶縁性材料か
らなる基板と、該絶縁性基板上に形成した第1の金属配
線層と、該第1の金属配線層上にこれを被覆するように
電気メッキにより形成した第2の金属配線層と、からな
ることを特徴とする。In order to achieve the above object, the wiring structure of a liquid crystal display device of the present invention comprises a substrate made of an insulating material, and a first metal wiring layer formed on the insulating substrate. A second metal wiring layer formed on the first metal wiring layer by electroplating so as to cover the first metal wiring layer.
【0008】本発明の配線構造は、第2金属配線層の上
にこれを被覆するように、第1金属配線と同種の金属と
第1若しくは第2金属配線とは異種と、の金属の少なく
とも一方からなる金属により第2金属配線層を被覆する
ように電気メッキにより形成された第3の金属配線層を
含むものであってもよい。In the wiring structure of the present invention, at least a metal of the same type as the first metal wiring and a different metal of the first or second metal wiring are formed so as to cover the second metal wiring layer. It may include a third metal wiring layer formed by electroplating so as to cover the second metal wiring layer with a metal of one side.
【0009】[0009]
【作用及び効果】配線構造を、絶縁性材料からなる基板
と、該絶縁性基板上に形成した第1の金属配線層と、該
第1の金属配線層の上にこれを被覆するように電気メッ
キにより形成した第2の金属配線層とから構成したの
で、例えばCuのようにガラス基板に対して密着性が劣
り若しくは被着後のドライエッチングが困難な金属を用
いて金属配線を形成する場合であっても、ガラス基板と
Cu配線層との間にガラス基板に対して密着性の高いC
r配線層を設ければ、ガラス基板との密着性が良く且つ
Cu配線層との密着性も良く更にドライエッチング工程
を要することなく簡易に形成することができる。また、
熱的影響を受け易いAl等の金属配線層を使用する場合
であっても、この上層には更により熱的に安定なNi等
の金属配線層がこれを被覆するように自己整合的に形成
されるので、これらの金属配線上に比較的高温な条件下
でプラズマCVD等により窒素珪素等の絶縁膜を形成す
るに際しても、Al配線層等は上層のより熱的に安定な
Ni等の金属配線層により被覆保護されるのでヒロック
等の熱的な影響は有効に防止される。[Operations and Effects] The wiring structure has a substrate made of an insulating material, a first metal wiring layer formed on the insulating substrate, and an electrical structure so that the first metal wiring layer covers the first metal wiring layer. When the metal wiring is formed by using a second metal wiring layer formed by plating, a metal such as Cu having poor adhesion to the glass substrate or having difficulty in dry etching after deposition is used. C, which has a high adhesion to the glass substrate between the glass substrate and the Cu wiring layer,
When the r wiring layer is provided, the adhesion to the glass substrate is good and the adhesion to the Cu wiring layer is good, and the r wiring layer can be easily formed without requiring a dry etching step. Also,
Even when a metal wiring layer such as Al that is easily affected by heat is used, a metal wiring layer such as Ni, which is more thermally stable, is formed on the upper layer in a self-aligned manner so as to cover the metal wiring layer. Therefore, even when an insulating film such as nitrogen silicon is formed on these metal wirings by plasma CVD or the like under relatively high temperature conditions, the Al wiring layer or the like is made of a metal such as Ni which is more thermally stable than the upper layer. Since it is covered and protected by the wiring layer, thermal effects such as hillocks are effectively prevented.
【0010】[0010]
【実施例】次に、本発明による液晶表示装置の信号配線
形成方法について実施例に従い図1乃至図3を参照しな
がら詳細に説明する。尚、本明細書では同一若しくは類
似の部品または要素に対しては明細書を通して同一の番
号を付して説明する。本発明の配線構造は、ここでは説
明を省略するアクテイブマトリックス型液晶表示装置の
液晶駆動に使用される薄膜型トランジスタ(TFT)を
形成する際にフオトリソグラフイ技術を用いて形成され
る。Next, a method for forming a signal wiring of a liquid crystal display device according to the present invention will be described in detail with reference to FIGS. 1 to 3 according to an embodiment. In the present specification, the same or similar parts or elements will be described with the same numbers throughout the specification. The wiring structure of the present invention is formed by using a photolithography technique when forming a thin film transistor (TFT) used for driving a liquid crystal of an active matrix type liquid crystal display device whose description is omitted here.
【0011】図1は本発明の第1の実施例によるアクテ
イブマトリックス型液晶表示装置の各TFT素子に接続
されるCuを用いた信号配線の断面を示す。同図中、符
号1は液晶表示装置に使用される液晶を挟持する1対の
ガラス基板の一方の要部断面を示す。まず、該ガラス基
板1上に、Cr膜をスパッタにより成膜後、フオトリソ
グラフイ技術により所要のパターンにエッチングしてC
r配線層(第1金属配線層)2を約1000オングスト
ロームの層厚に形成する。FIG. 1 shows a cross section of a signal wiring using Cu connected to each TFT element of an active matrix type liquid crystal display device according to a first embodiment of the present invention. In the figure, reference numeral 1 is a cross-sectional view of the main part of one of a pair of glass substrates that holds a liquid crystal used in a liquid crystal display device. First, a Cr film is formed on the glass substrate 1 by sputtering, and then a desired pattern is etched by a photolithography technique to form a C film.
The r wiring layer (first metal wiring layer) 2 is formed to have a layer thickness of about 1000 Å.
【0012】次いで、Cr配線層2を形成したガラス基
板1上にCu層3を、図2に示す電気メッキ装置を用い
て形成する。該メッキ装置は、内部にメッキ液12を収
容するメッキ槽11と、メッキ槽内のメッキ液を所望の
温度に保持するためにメッキ槽11の下側に設けられた
加熱ヒータからなる温調器13と、メッキ槽11内のメ
ッキ液12を循環させるためにメッキ槽11に設けられ
た循環路14と、メッキ槽11内のメッキ液12を循環
させるために循環路14の途中に設けられた循環ポンプ
15と、循環ポンプ15の上流側の循環路の途中に介設
されたろ過フイルタ16と、を備えている。メッキ槽1
1内に収容されたメッキ液12内には陽極としてのCu
板17と陰極としての上述のCr層が形成されたガラス
基板1がそれぞれの導線を介して直流電源19の陽極及
び陰極に接続される。また、メッキ槽11内のメッキ液
12の温度及びpH値を監視するために温度計及びpH
計20が備えつけられている。Next, a Cu layer 3 is formed on the glass substrate 1 having the Cr wiring layer 2 formed thereon by using the electroplating apparatus shown in FIG. The plating apparatus includes a plating tank 11 that contains a plating solution 12 therein, and a temperature controller that is provided below the plating tank 11 to maintain the plating solution in the plating tank at a desired temperature. 13, a circulation path 14 provided in the plating tank 11 for circulating the plating solution 12 in the plating tank 11, and a circulation path 14 provided in the middle of the circulation path 14 for circulating the plating solution 12 in the plating tank 11. The circulation pump 15 and a filtration filter 16 provided in the middle of the circulation path on the upstream side of the circulation pump 15 are provided. Plating tank 1
In the plating solution 12 contained in 1
The plate 17 and the glass substrate 1 on which the above-mentioned Cr layer as the cathode is formed are connected to the anode and the cathode of the DC power supply 19 through the respective conductive wires. Further, in order to monitor the temperature and pH value of the plating solution 12 in the plating tank 11, a thermometer and a pH are used.
A total of 20 are provided.
【0013】このように構成されたメッキ装置のメッキ
槽11内に、硫酸銅180g/l、硫酸70g/lを溶
解させた水溶液からなるメッキ液12を充満させ、直流
電源19の陽極にCu板17および陰極に上述のように
Cr層を形成したガラス基板1をその非メッキ部分をレ
ジストで覆った状態で導線を介して接続後、Cu板17
とガラス基板1の対向面を約3cm離間させた状態でメ
ッキ溶液12中に浸漬し、直流電源19に所要の電圧を
印加することによりCu板17とガラス基板1のCr層
2との間にメッキ液12を介して電流を通電させて該C
r層2上にCuメッキ層3を形成する。この場合、Cr
層2上の電流密度は約280μA/cm2になるように制
御し、またメッキ液12の温度は約40℃の温度値に維
持することにより、Cr層2上に約0.4μm/min
の成膜速度でCuメッキ層3が形成される。このように
して、Cuメッキ層(第2金属配線層)3が約1000
オングストロームの層厚に形成されたらメッキを終了
し、ガラス基板1上のレジストの除去等の所要の作業を
行う。尚、Cuメッキのメッキ厚は電流密度と処理時間
との積に比例するため、均一なCuメッキ層を得るに
は、例えば陽極のCu板17と陰極のガラス基板1のC
r層2との対向面を平行に配置する等により、Cr層2
上の電流密度の均一化を図ればよい。The plating tank 11 of the plating apparatus thus constructed is filled with the plating solution 12 which is an aqueous solution in which 180 g / l of copper sulfate and 70 g / l of sulfuric acid are dissolved, and the anode of the DC power source 19 is a Cu plate. After connecting the glass substrate 1 on which the Cr layer is formed on the cathode 17 and the cathode as described above with the non-plated portion thereof covered with a resist through a conductor, a Cu plate 17
Between the Cu plate 17 and the Cr layer 2 of the glass substrate 1 by immersing it in the plating solution 12 with the opposite surface of the glass substrate 1 separated from the glass substrate 1 by about 3 cm and applying a required voltage to the DC power supply 19. The electric current is passed through the plating solution 12 so that the C
A Cu plating layer 3 is formed on the r layer 2. In this case, Cr
By controlling the current density on the layer 2 to be about 280 μA / cm 2 and maintaining the temperature of the plating solution 12 at a temperature value of about 40 ° C., about 0.4 μm / min on the Cr layer 2 is obtained.
The Cu plating layer 3 is formed at the film forming speed of. In this way, the Cu plating layer (second metal wiring layer) 3 has a thickness of about 1000.
When the film is formed to a layer thickness of angstrom, the plating is finished, and the required work such as removing the resist on the glass substrate 1 is performed. Since the plating thickness of Cu plating is proportional to the product of current density and processing time, in order to obtain a uniform Cu plating layer, for example, Cu plate 17 of the anode and C of glass substrate 1 of the cathode are used.
By arranging the surface facing the r layer 2 in parallel, the Cr layer 2
It is sufficient to make the above current density uniform.
【0014】上述のようにCuメッキ層3を形成後、こ
の層上に約1000オングストロームの層厚のCrメッ
キ層4を形成する。このCrメッキ層4の形成は、やは
り上述のメッキ装置を用いて、クロム酸250g/l及
び硫酸2.5g/lを溶解させたメッキ溶液12中に、
陽極に純鉛板を接続し、及び陰極に上記のCr層及びC
u層を形成したガラス基板1をその所要の部分をレジス
トで覆った状態で接続して、両者の対向面を、例えば3
cm、離間させた状態で浸漬し、直流電源19によりガ
ラス基板1のCu層3上の電流密度が約5mA/cm2に
なるように制御して行う。この場合、メッキ液12は約
50℃の温度に維持する。このようにCrメッキの条件
を設定することにより、ガラス基板1のCu層3上に約
0.2μm/minの成膜速度でCrメッキ層4(第3
金属配線層)が形成される。約1000オングストロー
ムの層厚にCrメッキ層4が形成されたらメッキを終了
し、ガラス基板1のレジストの除去後、これらの金属配
線層上に絶縁膜としての、図示しない、窒化珪素(Si
Nx)膜をプラズマCVDにより被覆形成することによ
り本発明の第1実施例による配線構造が得られる。この
ように、本発明の第1実施例によれば、ガラス基板に対
して密着性が劣り且つドライエッチングが困難なCu層
を簡易かつ確実にガラス基板上に形成することができ
る。After forming the Cu plating layer 3 as described above, a Cr plating layer 4 having a layer thickness of about 1000 angstrom is formed on this layer. The formation of this Cr plating layer 4 is carried out by using the above-mentioned plating apparatus, in a plating solution 12 in which chromic acid 250 g / l and sulfuric acid 2.5 g / l are dissolved.
Connect a pure lead plate to the anode, and the above-mentioned Cr layer and C to the cathode.
The glass substrate 1 on which the u layer has been formed is connected in a state in which the required portions are covered with a resist, and the opposing surfaces of both are, for example, 3
It is soaked in a state of being separated from the glass substrate 1 by a direct current power source 19 so that the current density on the Cu layer 3 of the glass substrate 1 is about 5 mA / cm 2 . In this case, the plating solution 12 is maintained at a temperature of about 50 ° C. By setting the Cr plating conditions in this way, the Cr plating layer 4 (third layer) is formed on the Cu layer 3 of the glass substrate 1 at a film forming rate of about 0.2 μm / min.
A metal wiring layer) is formed. When the Cr plating layer 4 is formed to a layer thickness of about 1000 angstroms, the plating is terminated, the resist on the glass substrate 1 is removed, and then silicon nitride (Si (Si) (not shown) as an insulating film is formed on these metal wiring layers.
The wiring structure according to the first embodiment of the present invention can be obtained by forming the Nx) film by plasma CVD. As described above, according to the first embodiment of the present invention, it is possible to easily and reliably form the Cu layer, which has poor adhesion to the glass substrate and is difficult to dry-etch, on the glass substrate.
【0015】次に、本発明の第2実施例による信号配線
の形成方法について説明する。図3に示すように、本発
明の第2実施例による信号配線は、ガラス基板1上に約
2000オングストロームの層厚のAl層5と、該Al
層を被覆する約1000オングストロームのNiメッキ
層6からなる。以下に、本発明の第2実施例によるAl
を用いた信号配線の形成方法について説明する。まず、
図3に示すように、ガラス基板1上にスパッタ法にてA
l膜を成膜後、フオトリソグラフイにより所要のパター
ンにエッチングすることによりAl配線層5を形成す
る。Al配線層5を形成したガラス基板1の所要の部分
にレジストによりマスクを施した後、ガラス基板1を硫
酸ニッケル250g/l及びほう酸40g/lを溶解さ
せたメッキ液12中に、純鉛板17’を陽極に、及び上
記のガラス基板1を陰極に接続した状態で約3cm離間
させた状態で浸漬する。メッキ条件としては、電流密度
が約150μA/cm2、メッキ液12の温度が約50
℃、pHは約4となるように設定する。このように条件
を設定することにより、ガラス基板1のAl層5上にN
i層6が約0.2μm/minの成膜速度で形成され
る。本実施例によるメッキ層6の形成も上述したメッキ
装置を用いて第1実施例におけるメッキと同様に行うこ
とができる。このようにして、Niメッキが完了したら
有機溶剤等によりレジストを除去後、金属配線層の上面
に、図示しない、窒化珪素膜をプラズマCVDにより被
覆形成することにより本発明の第2実施例による配線構
造がえられる。本実施例による配線構造によれば、ガラ
ス基板1上のAl配線層5はその露出面がNiメッキ層
6により自己整合的に被覆されるので、図示しない、T
FT素子のゲート絶縁層等のプラズマCVD等による高
温処理に際してもAl配線層のヒロックの発生等を効果
的に防止できる。また、Niは一般にドライエッチング
が困難であるが、本実施例のように電気メッキにより形
成することにより、エッチング工程を要することなく所
望のパターンで被覆形成が可能である。Next, a method of forming a signal wiring according to the second embodiment of the present invention will be described. As shown in FIG. 3, the signal wiring according to the second embodiment of the present invention includes an Al layer 5 having a layer thickness of about 2000 angstroms on the glass substrate 1 and the Al layer.
It consists of about 1000 angstroms of Ni plating layer 6 covering the layer. Hereinafter, Al according to the second embodiment of the present invention will be described.
A method of forming a signal wiring using is described. First,
As shown in FIG.
After forming the l film, the Al wiring layer 5 is formed by etching into a desired pattern by photolithography. After masking a required portion of the glass substrate 1 on which the Al wiring layer 5 is formed with a resist, the glass substrate 1 is immersed in a plating solution 12 in which 250 g / l of nickel sulfate and 40 g / l of boric acid are dissolved to form a pure lead plate. 17 'is connected to the anode, and the glass substrate 1 is connected to the cathode, and the glass substrate 1 and the glass substrate 1 are separated by about 3 cm. As the plating conditions, the current density is about 150 μA / cm 2 , and the temperature of the plating solution 12 is about 50.
The temperature and pH are set to about 4. By setting the conditions in this way, N is formed on the Al layer 5 of the glass substrate 1.
The i layer 6 is formed at a film forming rate of about 0.2 μm / min. The plating layer 6 according to this embodiment can be formed by using the above-described plating apparatus in the same manner as the plating in the first embodiment. Thus, after the Ni plating is completed, the resist is removed with an organic solvent or the like, and then a silicon nitride film (not shown) is formed on the upper surface of the metal wiring layer by plasma CVD to form the wiring according to the second embodiment of the present invention. The structure is obtained. According to the wiring structure of the present embodiment, the exposed surface of the Al wiring layer 5 on the glass substrate 1 is covered with the Ni plating layer 6 in a self-aligned manner.
It is possible to effectively prevent the occurrence of hillocks in the Al wiring layer even during high-temperature processing such as plasma CVD of the gate insulating layer of the FT element. Further, although it is generally difficult to dry-etch Ni, by forming it by electroplating as in this embodiment, it is possible to form a coating in a desired pattern without requiring an etching step.
【0016】上述の第2実施例ではガラス基板上のAl
層上をNiメッキ層で被覆したが、Niメッキ層に代え
て、Crのメッキ層を形成しても全く同様の効果が得ら
れる。また、上記の第2実施例で形成したNiメッキ層
上に更にCrメッキを施し3層の配線構造にすれば、ヒ
ロック発生の防止はより確実になされる。尚、上記実施
例に示した電気メッキの各条件は適宜所望の値に変更し
得ることはいうまでもない。In the above-mentioned second embodiment, Al on the glass substrate is used.
Although the layer is covered with a Ni plating layer, the same effect can be obtained by forming a Cr plating layer instead of the Ni plating layer. If the Ni plating layer formed in the second embodiment is further plated with Cr to form a three-layer wiring structure, the occurrence of hillocks can be prevented more reliably. Needless to say, the electroplating conditions shown in the above embodiments can be changed to desired values as appropriate.
【図1】本発明の第1実施例による配線構造の断面図で
ある。FIG. 1 is a sectional view of a wiring structure according to a first embodiment of the present invention.
【図2】本発明の第2実施例による配線構造の断面図で
ある。FIG. 2 is a sectional view of a wiring structure according to a second embodiment of the present invention.
【図3】本発明の配線構造の形成に使用されるメッキ装
置の概略図である。FIG. 3 is a schematic view of a plating apparatus used for forming the wiring structure of the present invention.
【図4】従来の配線構造の断面図である。FIG. 4 is a cross-sectional view of a conventional wiring structure.
1 ガラス基板 2 Cr配線層 3 Cuメッキ配線層 4 Crメッキ配線層 5 Al配線層 6 Ni配線層 11 メッキ槽 12 メッキ液 14 循環路 15 循環ポンプ 19 直流電源 1 Glass Substrate 2 Cr Wiring Layer 3 Cu Plating Wiring Layer 4 Cr Plating Wiring Layer 5 Al Wiring Layer 6 Ni Wiring Layer 11 Plating Tank 12 Plating Liquid 14 Circulation Path 15 Circulation Pump 19 DC Power Supply
───────────────────────────────────────────────────── フロントページの続き (72)発明者 波多 俊弘 京都市右京区西院溝崎町21番地 ロ−ム株 式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshihiro Hata 21 No. 21 Mizozaki-cho, Saiin, Ukyo-ku, Kyoto City Rome Stock Company
Claims (2)
上に形成した第1の金属配線層と、該第1の金属配線層
上にこれを被覆するように電気メッキにより形成した第
2の金属配線層と、からなることを特徴とする液晶表示
装置の配線構造。1. A substrate made of an insulating material, a first metal wiring layer formed on the insulating substrate, and a first metal wiring layer formed on the first metal wiring layer by electroplating so as to cover the first metal wiring layer. 2. A wiring structure for a liquid crystal display device, comprising: a metal wiring layer 2;
るように、前記第1金属配線と同種の金属と前記第1若
しくは第2金属配線とは異種の金属と、の少なくとも一
方からなる金属により前記第2金属配線層を被覆するよ
うに電気メッキにより形成された第3の金属配線層を含
む請求項1に記載の液晶表示装置の配線構造。2. A metal of the same kind as the first metal wiring and a metal of a different kind from the first or second metal wiring so as to cover the second metal wiring layer. 2. The wiring structure of the liquid crystal display device according to claim 1, further comprising a third metal wiring layer formed by electroplating so as to cover the second metal wiring layer with a metal made of.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28704993A JPH07140475A (en) | 1993-11-16 | 1993-11-16 | Wiring structure of liquid crystal display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28704993A JPH07140475A (en) | 1993-11-16 | 1993-11-16 | Wiring structure of liquid crystal display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07140475A true JPH07140475A (en) | 1995-06-02 |
Family
ID=17712395
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28704993A Pending JPH07140475A (en) | 1993-11-16 | 1993-11-16 | Wiring structure of liquid crystal display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07140475A (en) |
Cited By (8)
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---|---|---|---|---|
WO2001065599A2 (en) * | 2000-03-03 | 2001-09-07 | Micron Technology, Inc. | Nitride layer forming methods |
JP2001343659A (en) * | 2000-06-02 | 2001-12-14 | Casio Comput Co Ltd | Active matrix type liquid crystal display panel and method of manufacture |
JP2002318555A (en) * | 2000-12-21 | 2002-10-31 | Semiconductor Energy Lab Co Ltd | Light emitting device and manufacturing method therefor |
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1993
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001065599A3 (en) * | 2000-03-03 | 2002-02-28 | Micron Technology Inc | Nitride layer forming methods |
WO2001065599A2 (en) * | 2000-03-03 | 2001-09-07 | Micron Technology, Inc. | Nitride layer forming methods |
JP2001343659A (en) * | 2000-06-02 | 2001-12-14 | Casio Comput Co Ltd | Active matrix type liquid crystal display panel and method of manufacture |
US9059216B2 (en) | 2000-12-11 | 2015-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
US10665610B2 (en) | 2000-12-11 | 2020-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
US9666601B2 (en) | 2000-12-11 | 2017-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
US9231044B2 (en) | 2000-12-21 | 2016-01-05 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device and method of manufacturing the same |
JP4741569B2 (en) * | 2000-12-21 | 2011-08-03 | 株式会社半導体エネルギー研究所 | Light emitting device |
JP2008090322A (en) * | 2000-12-21 | 2008-04-17 | Semiconductor Energy Lab Co Ltd | Light emitting device |
US9793335B2 (en) | 2000-12-21 | 2017-10-17 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device and method of manufacturing the same |
JP2002318555A (en) * | 2000-12-21 | 2002-10-31 | Semiconductor Energy Lab Co Ltd | Light emitting device and manufacturing method therefor |
KR100870697B1 (en) * | 2002-03-07 | 2008-11-27 | 엘지디스플레이 주식회사 | Method for fabricating of low resistivity Copper |
KR100848100B1 (en) * | 2002-05-21 | 2008-07-24 | 삼성전자주식회사 | A thin film transistor array panel and a method for manufacture thereof |
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