JPH07122551A - Deposition of insulation film or planarization film for semiconductor - Google Patents
Deposition of insulation film or planarization film for semiconductorInfo
- Publication number
- JPH07122551A JPH07122551A JP26745793A JP26745793A JPH07122551A JP H07122551 A JPH07122551 A JP H07122551A JP 26745793 A JP26745793 A JP 26745793A JP 26745793 A JP26745793 A JP 26745793A JP H07122551 A JPH07122551 A JP H07122551A
- Authority
- JP
- Japan
- Prior art keywords
- film
- coating
- solvent
- polymethylsilsesquioxane
- formula
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高度に集積化された半
導体素子上への新規な絶縁膜または平坦化膜の形成方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a novel insulating film or planarizing film on a highly integrated semiconductor device.
【０００２】[0002]
【従来の技術】ＬＳＩの高集積化と共に配線の多層化が
不可避となってきており、回路の信頼性を維持する上で
層間絶縁膜及び平坦化膜の重要性が増してきている。層
間絶縁膜等の形成方法には一般に気相法（ＣＶＤ法）に
より緻密なＳｉＯ2 膜を堆積し、テトラヒドロキシシラ
ンに代表される無機系のポリシロキサン被覆膜（無機Ｓ
ＯＧ）を塗布法で形成すると共に、この無機ＳＯＧ膜の
上下を緻密なＣＶＤ法、ＳｉＯ2 膜でサンドイッチする
方法が採用されてきた。しかし、半導体の高集積化、多
層配線化が進むにつれ配線幅、パターン間の溝（スペー
ス溝）が狭くなり、配線幅と配線高さの比率であるアス
ペクト比は益々大きくなっている。このため、ＳＯＧ膜
厚を厚くしなければならないが、無機ＳＯＧ膜では０．
２μｍ以上にするとクラックが発生し易い欠点があり、
使用するには問題があった。2. Description of the Related Art With higher integration of LSIs, multi-layered wiring is inevitable, and the importance of interlayer insulating films and flattening films is increasing in order to maintain circuit reliability. As a method of forming an interlayer insulating film or the like, a dense SiO 2 film is generally deposited by a vapor phase method (CVD method), and an inorganic polysiloxane coating film (inorganic S
OG) is formed by a coating method, and the upper and lower sides of this inorganic SOG film are sandwiched by a dense CVD method and a SiO 2 film. However, as semiconductors are highly integrated and multilayer wiring is advanced, the wiring width and the groove (space groove) between patterns are narrowed, and the aspect ratio, which is the ratio of the wiring width and the wiring height, is increasing. For this reason, it is necessary to increase the SOG film thickness.
If it is 2 μm or more, there is a drawback that cracks are likely to occur,
There was a problem to use.
【０００３】そこで近時塗布法に代表されるテトラヒド
ロキシシラン系被膜（無機ＳＯＧ）の厚膜化、耐クラッ
ク性や平坦化能力の問題を解決するために、アルキルト
リヒドロキシシランなどのいわゆる有機ＳＯＧを層間絶
縁膜（平坦化膜）として使用することが提案されてい
る。この場合には溝部を除いて有機ＳＯＧ硬化膜を除去
するエッチバック法が採用されることが多い。しかし、
この有機ＳＯＧ膜にもいくつかの問題点があることが指
摘されている。例えば、平坦度に対する要求が増し、従
来のアルキルトリヒドロキシシランでは「局所的平坦
化」といわれる平坦化レベルまでしか実現できず、素子
の微細化、集積化が進むにつれ所望されている「完全平
坦化」といわれるレベルへの到達は困難なため、配線部
とスペース部に絶対段差が残り、多層配線化が３層、４
層、５層と進むにつれ配線部とスペース部に絶対段差が
残り、後工程リソグラフィーでのスッテパー焦点深度
（フォーカスマージン）が狭くなる等の問題点が懸念さ
れている。Therefore, in order to solve the problems of thickening, crack resistance and flattening ability of a tetrahydroxysilane coating (inorganic SOG) represented by a recent coating method, so-called organic SOG such as alkyltrihydroxysilane is used. Has been proposed as an interlayer insulating film (planarizing film). In this case, an etch back method of removing the organic SOG cured film except the groove is often adopted. But,
It has been pointed out that this organic SOG film also has some problems. For example, the demand for flatness has increased, and conventional alkyltrihydroxysilanes can achieve only a level of planarization called "localized planarization", which is desired as device miniaturization and integration progress. Since it is difficult to reach the level called "development", an absolute step remains on the wiring part and the space part, and the multi-layer wiring becomes three layers or four.
As the number of layers and the number of layers increase, an absolute step remains in the wiring portion and the space portion, and there is a concern that the stepper focus depth (focus margin) in the post-process lithography becomes narrow.
【０００４】更に、半導体素子内に井戸状、蛸壷状など
種々の形状を有し、かつ穴の直径が１μｍ以下であるよ
うな微細穴を設け、各種機能を発現させる高度な集積化
の設計技術も急速に進展しつつある。アルキルトリヒド
ロキシシランのような従来タイプの有機ＳＯＧでは上記
のような１μｍ以下の微細穴には、１〜２回の塗布では
埋め込みが不可能であり、また多数回の塗布により目的
とする絶縁膜または平坦化膜を得たとしても、尚、ボイ
ドが残りデバイスの性能評価試験で不合格になるものが
出るなど信頼性の問題があった。Further, a highly integrated design technique for exhibiting various functions by providing fine holes having various shapes such as a well shape and an octopus shape in a semiconductor element and having a hole diameter of 1 μm or less Is making rapid progress. In the conventional type organic SOG such as alkyltrihydroxysilane, it is impossible to fill the fine holes of 1 μm or less as described above by applying once or twice, and by applying multiple times, the target insulating film is formed. Even if a flattening film is obtained, there still remains a problem in reliability such as voids remaining and some failing in the device performance evaluation test.
【０００５】[0005]
【発明が解決しようとする課題】本発明は、上述した従
来技術の問題点を解決する目的でなされたものであり、
「完全平坦化」に限りなく近いレベルの平坦性と共に、
井戸状、蛸壷状など種々の形状を有し、かつ穴の直径が
１μｍ以下であるような微細穴にも、１〜２回の塗布で
も埋め込み可能な半導体の層間絶縁膜または平坦化膜の
形成方法を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made for the purpose of solving the above-mentioned problems of the prior art.
With a level of flatness as close as possible to "perfect flattening",
Formation of a semiconductor interlayer insulating film or a flattening film that can be embedded even in fine holes having various shapes such as well shape and octopus shape and having a diameter of 1 μm or less by coating once or twice The purpose is to provide a method.
【０００６】[0006]
【課題を解決するための手段】本発明は、直径が１μｍ
以下である微細穴を有する半導体素子をコーティングす
るに際し、下記一般式（１）で示される数平均分子量５
００〜１０，０００のポリメチルシルセスキオキサンThe present invention has a diameter of 1 μm.
When coating a semiconductor device having the following fine holes, a number average molecular weight of 5 represented by the following general formula (1)
100-10,000 polymethylsilsesquioxane
【化２】 （式中、Ｒ1 はメチル基を、Ｒ2 は炭素数１〜４のアル
キル基及び／または水素原子を示し、ｎは分子量に対応
する正の数である。）を下記一般式（２）〜（５）で示
される溶剤 Ｒ3 −Ｏ−Ｒ4 −ＯＣＯＲ5 （２） Ｒ6 −Ｏ−Ｒ7 −ＣＯＯＲ8 （３） Ｒ9 ＣＨ（ＯＨ）ＣＯＯＲ10 （４） Ｒ11ＣＨ（ＯＲ12）ＣＯＯＲ13 （５） （式中、Ｒ3 、Ｒ5 、Ｒ6 、Ｒ8 〜Ｒ13は炭素数１〜４
のアルキル基を、Ｒ4、Ｒ7 はアルキル基で置換可能な
炭素数２〜４のアルキレン基を示す。）の一種または二
種以上の混合物を含む溶剤に溶解させた溶液を使用し、
該微細穴を埋め込むことを特徴とする半導体用絶縁膜ま
たは平坦化膜の形成方法に関する。[Chemical 2] (In the formula, R 1 represents a methyl group, R 2 represents an alkyl group having 1 to 4 carbon atoms and / or a hydrogen atom, and n is a positive number corresponding to the molecular weight.) Is represented by the following general formula (2). To a solvent represented by (5) R 3 —O—R 4 —OCOR 5 (2) R 6 —O—R 7 —COOR 8 (3) R 9 CH (OH) COOR 10 (4) R 11 CH (OR 12 ) COOR 13 (5) (In the formula, R 3 , R 5 , R 6 , and R 8 to R 13 have 1 to 4 carbon atoms.
And the alkyl groups R 4 and R 7 each represent an alkylene group having 2 to 4 carbon atoms which can be substituted with an alkyl group. ) Or a solution containing a mixture of two or more of
The present invention relates to a method for forming an insulating film for a semiconductor or a flattening film, which is characterized by filling the fine holes.
【０００７】また、上記ポリメチルシルセスキオキサン
を溶解させた溶液を半導体素子上にコーティングした
後、１００〜２００℃の温度で溶剤を蒸発させ次いで２
００〜５００℃の温度で加熱硬化させて、ポリメチルシ
ルセスキオキサンの軟化による再流動化をさせる上記の
半導体用絶縁膜または平坦化膜の形成方法に関する。Further, after coating the semiconductor element with a solution in which the above polymethylsilsesquioxane is dissolved, the solvent is evaporated at a temperature of 100 to 200 ° C. and then 2
The present invention relates to the above-mentioned method for forming an insulating film for a semiconductor or a flattening film which is cured by heating at a temperature of 00 to 500 ° C. to reflow the polymethylsilsesquioxane by softening.
【０００８】以下、本発明を詳しく説明する。本発明で
用いられる一般式（１）のポリメチルシルセスキオキサ
ンにおいて、側鎖のＲ1 はメチル基であることが望まし
いが、１０モル％未満の範囲で、他の有機基、例えば低
級アルキル基やフェニル基であっても使用することがで
きる。また、該ポリメチルシルセスキオキサンの数平均
分子量は、ポリスチレン標準試料を用いて、ＧＰＣ（ゲ
ル・パーミュレーション・クロマトグラフィー）法によ
り測定しうるが、数平均分子量としては、５００〜１
０，０００が好ましい。数平均分子量が５００より小さ
いと高温加熱時及び硬化時の収縮率が大きくなり、結果
として微細配線、特にアスペクト比が大なる溝部や前述
の微細穴におけるコーティング膜にクラックが発生し易
くなる。また、数平均分子量が１０，０００より大きい
と有機溶剤に対する溶解性が不充分となるのみならず、
塗布液の粘度が高くなり前述の微細穴に対する埋め込み
性が不充分となる。更に硬化過程での再流動化特性も阻
害され、平坦化特性が不満となる。The present invention will be described in detail below. In the polymethylsilsesquioxane of the general formula (1) used in the present invention, it is desirable that R 1 of the side chain is a methyl group, but within the range of less than 10 mol%, other organic groups such as lower alkyl can be used. Even a group or a phenyl group can be used. The number average molecular weight of the polymethylsilsesquioxane can be measured by GPC (gel permeation chromatography) using a polystyrene standard sample, and the number average molecular weight is 500 to 1
10,000 is preferable. If the number average molecular weight is less than 500, the shrinkage ratio at the time of heating at high temperature and at the time of curing becomes large, and as a result, cracks are likely to occur in the fine wiring, particularly in the groove portion having a large aspect ratio and the coating film in the fine holes described above. Further, if the number average molecular weight is more than 10,000, not only the solubility in an organic solvent becomes insufficient,
The viscosity of the coating solution becomes high, and the embeddability in the aforementioned fine holes becomes insufficient. Further, the refluidization characteristic in the curing process is also impaired, and the planarization characteristic becomes unsatisfactory.
【０００９】本発明における一般式（１）ポリメチルシ
ルセスキオキサンを半導体基板素子上にコーティングす
る際には、有機溶剤に溶解した溶液として用いる。本発
明の分子量域のポリメチルシルセスキオキサンは多様な
有機溶剤に可溶であるが、本発明においては、前記一般
式（２）〜（５）で示される溶剤の一種または二種以上
の混合物を含む溶剤を用いることが必須である。例え
ば、一般式（２）として、プロピレングリコールモノア
ルキルエーテルアセテート類（具体例としてはプロピレ
ングリコールモノメチルエーテルアセテート）、一般式
（２）として、３−アルコキシプロピオン酸エステル類
（具体例としては３−メトキシプロピオン酸メチル、３
−メトキシプロピオン酸エチル）、一般式（３）とし
て、乳酸エステル類（具体例としては乳酸メチル、乳酸
エチル）、一般式（４）として、乳酸エーテルエステル
類（具体例としては乳酸メチルエチルエーテル、乳酸エ
チルメチルエーテル）等が挙げられる。その中でも特
に、溶剤沸点が１００〜２００℃のものが、スピンコー
ト塗布後、溶剤を完全に蒸発させて成膜させるプロセス
の設定が容易であるため好ましい。沸点が１００℃以下
ではスピンコート滴下時の蒸発速度が早すぎるため塗布
膜厚の均一性が得られにくく、また沸点が２００℃以上
の高沸点溶剤においては、本発明のポリメチルシルセス
キオキサンの硬化反応の開始温度が約２００℃であるた
め、膜中に溶剤が残存し良好な膜質が得られにくくなる
欠点がある。When coating the semiconductor substrate element with polymethylsilsesquioxane of the general formula (1) in the present invention, it is used as a solution dissolved in an organic solvent. The polymethylsilsesquioxane in the molecular weight range of the present invention is soluble in various organic solvents, but in the present invention, one or more of the solvents represented by the general formulas (2) to (5) are used. It is essential to use a solvent containing mixture. For example, as general formula (2), propylene glycol monoalkyl ether acetates (specific example is propylene glycol monomethyl ether acetate), and as general formula (2), 3-alkoxypropionic acid esters (specific example is 3-methoxy). Methyl propionate, 3
-Ethyl methoxypropionate), as general formula (3), lactate esters (specific examples are methyl lactate and ethyl lactate), and as general formula (4), lactate ether esters (specific example are methyl lactate ethyl ether, Ethyl lactate ether) and the like. Among them, those having a solvent boiling point of 100 to 200 ° C. are particularly preferable because it is easy to set a process for completely evaporating the solvent and forming a film after spin coating. When the boiling point is 100 ° C. or lower, the evaporation rate at the time of dropping the spin coat is too fast, so that it is difficult to obtain a uniform coating film thickness. Further, in the high boiling point solvent having a boiling point of 200 ° C. or higher, the polymethylsilsesquioxane of the present invention is used. Since the starting temperature of the curing reaction is about 200 ° C., the solvent remains in the film, which makes it difficult to obtain a good film quality.
【００１０】本発明における一般式（１）のポリメチル
シルセスキオキサンを溶解する溶剤としては、アルコー
ル類、エーテル類、エステル類、ケトン類、及び芳香族
炭化水素類等があり、これらの一般に用いられている溶
剤を上記の必須成分である溶剤に一部併用して用いるこ
とができる。これらの溶剤としては例えばアルコール類
としては、メチルアルコール、エチルアルコール、プロ
ピルアルコール、ブチルアルコール、エチレングリコー
ルモノアルキルエーテル、ジエチレングリコールモノア
ルキルエーテル等を挙げることができ、エステル類とし
ては、酢酸アルキルエステル等を挙げることができる。
また、ケトン類としては、例えばアセトン、メチルエチ
ルケトン、シクロヘキサンノン、メチルイソブチルケト
ン等を挙げることができ、芳香族炭化水素類としては、
例えば、ベンゼン、ジエチルベンゼン、クメン等を挙げ
ることができる。Solvents for dissolving the polymethylsilsesquioxane of the general formula (1) in the present invention include alcohols, ethers, esters, ketones, aromatic hydrocarbons, and the like. The solvent used can be used in combination with the above-mentioned essential component solvent. Examples of these solvents include alcohols such as methyl alcohol, ethyl alcohol, propyl alcohol, butyl alcohol, ethylene glycol monoalkyl ether, and diethylene glycol monoalkyl ether. Examples of the esters include acetic acid alkyl ester. Can be mentioned.
Further, examples of the ketones include acetone, methyl ethyl ketone, cyclohexanone, and methyl isobutyl ketone, and examples of the aromatic hydrocarbons include:
For example, benzene, diethylbenzene, cumene and the like can be mentioned.
【００１１】これら一般溶剤と上記一般式（２）〜
（５）の必須成分との組み合わせにおいて、必須成分は
少なくとも１０％、好ましくは２０％以上を含む溶剤と
する。必須成分が１０％以下では、本発明の目的とする
微細穴への埋め込み性が不満足となる。有機溶剤溶液中
のポリメチルシルセスキオキサンの固形分濃度はコーテ
ィング方法にもよるが、通常は２〜５０重量％、好まし
くは１０〜２０重量％である。また、本発明のポリオル
ガノシルセスキオキサン溶液には必要に応じてレベリン
グ剤、カップリング剤、増粘剤、充填剤、その他の添加
剤を加えて使用しても良い。These general solvents and the above general formulas (2) to
In the combination with the essential component (5), the essential component is a solvent containing at least 10%, preferably 20% or more. When the content of the essential component is 10% or less, the embeddability into the fine holes, which is the object of the present invention, becomes unsatisfactory. The solid content of polymethylsilsesquioxane in the organic solvent solution depends on the coating method, but is usually 2 to 50% by weight, preferably 10 to 20% by weight. Further, a leveling agent, a coupling agent, a thickener, a filler, and other additives may be added to the polyorganosilsesquioxane solution of the present invention, if necessary.
【００１２】本発明の半導体用絶縁膜または平坦化膜の
形成方法は、半導体素子内に各種機能を発現させるため
の井戸状、蛸壷状など種々の形状を有し、かつ穴の直径
が１μｍ以下であるような微細穴を有する半導体素子を
コーティングするに際して適用することが望ましい。ポ
リメチルシルセスキオキサン溶液を基板上にコーティン
グするに際しては、通常はスピンコーティング法が採用
される。また、必要に応じてディップコーティング、ス
プレーコーティング、その他の方法でコーティングして
も良い。またポリメチルシルセスキオキサン溶液を半導
体素子上にコーティングするに際しては、配線上にあら
かじめ気相法によるＳｉＯ2 膜を形成しておくのが一般
的である。The method for forming an insulating film for a semiconductor or a flattening film of the present invention has various shapes such as a well shape and an octopus shape for expressing various functions in a semiconductor element, and the diameter of the hole is 1 μm or less. It is desirable to apply it when coating a semiconductor device having such fine holes. When coating the substrate with the polymethylsilsesquioxane solution, spin coating is usually employed. Moreover, you may coat by dip coating, spray coating, and other methods as needed. When coating a semiconductor element with a polymethylsilsesquioxane solution, it is common to previously form a SiO 2 film on the wiring by a vapor phase method.
【００１３】本発明の方法によって形成されるポリオル
ガノシルセスキオキサン塗膜の膜厚は０．０１〜２．０
μｍの範囲で自由に選択することができる。特に膜厚が
１μｍ以上になってもクラックを生じないので、アスペ
クト比（配線高さ／配線スペース幅）が１以上の狭くて
深い溝になっている配線間の凹部を埋め平坦化すること
が可能であり、かつ前述の微細で深い穴へのコーティン
グにおいてもクラックなく埋め込むことが可能である。
これらの膜厚は、多数回の塗布によらなくても、１〜２
回のコーティングでも得ることができる。The film thickness of the polyorganosilsesquioxane coating film formed by the method of the present invention is 0.01 to 2.0.
It can be freely selected in the range of μm. In particular, since cracks do not occur even when the film thickness is 1 μm or more, it is possible to flatten the recesses between the wiring, which are narrow and deep trenches with an aspect ratio (wiring height / wiring space width) of 1 or more. It is possible, and even in the case of coating the fine and deep holes described above, it is possible to embed them without cracks.
These film thicknesses are 1 to 2 even if they are not applied many times.
It can be obtained by coating once.
【００１４】本発明はポリオルガノシルセスキオキサン
溶液をコーティングした後、１００〜２００℃、好まし
くは１６０〜２００℃の温度で１〜３０分間溶剤を実質
的に完全に蒸発させ、つぎに２００〜５００℃、好まし
くは３５０〜４５０℃の温度で１０〜１２０分間加熱す
ることによって行う。これらの加熱硬化条件は配合して
いる有機溶剤の種類やコート及びベーキングを行う装置
の種類により異なるので、硬化に先立ち予め充分な予備
加熱を行い、有機溶剤を乾燥除去した後、前記一般式
（１）で示されるポリオルガノシルセスキオキサンの特
徴である１８０〜２２０℃での軟化による再流動化を伴
う硬化条件を設定することが好ましい。硬化の温度は構
成材料である半導体基板構成材料の耐熱性から許容され
る範囲でなくべく高温にすることが硬化後の塗膜の膜質
（脱ガス性など）及び硬化プロセスの所要時間の面から
望ましいが、本発明で用いるポリメチルシルセスキオキ
サンでは３５０〜４５０℃、３０〜６０分の温度条件で
ほぼ完全に重合硬化させることが可能であるので、半導
体基板構成材料に悪影響を及ぼす熱履歴をなるべく少な
くするという点で極めて有利である。According to the present invention, after coating the polyorganosilsesquioxane solution, the solvent is substantially completely evaporated at a temperature of 100 to 200 ° C., preferably 160 to 200 ° C. for 1 to 30 minutes, and then 200 to 200 ° C. It is carried out by heating at a temperature of 500 ° C., preferably 350 to 450 ° C. for 10 to 120 minutes. These heat-curing conditions vary depending on the type of the compounded organic solvent and the type of the device for coating and baking, so sufficient preliminary heating is performed in advance before curing, and the organic solvent is dried and removed, and then the above-mentioned general formula ( It is preferable to set the curing conditions accompanied by refluidization due to softening at 180 to 220 ° C., which is a characteristic of the polyorganosilsesquioxane shown in 1). The curing temperature should not be allowed within the allowable range due to the heat resistance of the constituent material of the semiconductor substrate, which should be as high as possible from the viewpoint of the film quality (degassing etc.) of the cured film and the time required for the curing process. Although desirable, the polymethylsilsesquioxane used in the present invention can be almost completely polymerized and cured under a temperature condition of 350 to 450 ° C. for 30 to 60 minutes, so that the thermal history which adversely affects the semiconductor substrate constituent material Is extremely advantageous in that
【００１５】[0015]
【作用】本発明は、結果的には従来の有機ＳＯＧの問題
点をポリメチルシルセスキオキサンの配合溶剤組成、ベ
ーク条件を適宜選択してこれを達成したものである。従
来のアルキルトリヒドロキシシラン等の有機ＳＯＧで
は、反応開始温度が１２０℃付近と低いだけでなく、高
沸点の溶剤を配合しているため、溶剤を蒸発させてから
成膜（硬化）させるベーク条件の設定が難しく、良好な
膜質を得ることが困難であるばかりでなく、硬化架橋反
応が低温から始まってしまうため硬化過程での軟化によ
る再流動化といった現象も期待できない。このため硬化
膜の平坦化度は「局所的平坦化」のレベルに止まらざる
を得なかった。また、半導体素子内での穴の直径１．０
μｍ以下の井戸状、蛸壷状など種々の形状の微細穴に対
しても、１〜２回の塗布による埋め込みは不可能であっ
た。As a result, the present invention achieves the problems of the conventional organic SOG by appropriately selecting the compounding solvent composition of polymethylsilsesquioxane and the baking conditions. In the conventional organic SOG such as alkyltrihydroxysilane, the reaction start temperature is as low as around 120 ° C., and since a solvent having a high boiling point is blended, a baking condition for film formation (curing) after evaporation of the solvent Is difficult to obtain, and it is difficult to obtain a good film quality, and the phenomenon of refluidization due to softening in the curing process cannot be expected because the curing and crosslinking reaction starts from a low temperature. Therefore, the flatness of the cured film has to be limited to the level of "local flattening". Also, the diameter of the hole in the semiconductor element is 1.0
It was impossible to embed the fine holes having various shapes such as well-shaped or octopus-shaped having a size of not more than μm by applying once or twice.
【００１６】これに対して、本発明のポリメチルシルセ
スキオキサンと前記の一般式（２）、（３）、（４）、
（５）で示される溶剤を必須成分として含む溶剤配合系
は、比較的低沸点の溶剤配合のみで半導体基板への塗布
均一性を確保することが可能であること、硬化反応開始
温度が２００℃付近と高いため、溶剤を蒸発させてから
成膜（硬化）させるベーク条件の設定が容易で膜質の安
定化が図れること、ラダータイプのポリメチルシルセス
キオキサンを硬化せしめるため熱安定性に優れ良好な膜
質が得られること、さらに硬化過程で硬化による再流動
化現象が起こり、このため硬化膜の平坦化度は「安全平
坦化」に限りなく近いレベルまで可能であること、井戸
状、蛸壷状など種々の形状を有し、かつ穴の直径が１μ
ｍ以下であるような微細穴に対しても、１〜２回塗布に
よる埋め込みが実現できる。On the other hand, the polymethylsilsesquioxane of the present invention and the above-mentioned general formulas (2), (3), (4),
The solvent blending system containing the solvent represented by (5) as an essential component can ensure coating uniformity on a semiconductor substrate only by blending a solvent having a relatively low boiling point, and the curing reaction initiation temperature is 200 ° C. Since it is close to high, it is easy to set the baking conditions to evaporate the solvent and then form the film (curing), and the film quality can be stabilized. Also, the ladder type polymethylsilsesquioxane is cured, so it has excellent thermal stability. Good film quality is obtained, and re-fluidization phenomenon occurs due to curing during the curing process, so that the level of the cured film can be as close as possible to "safety leveling". Well, octopus It has various shapes such as the shape and the diameter of the hole is 1μ
Even in the case of fine holes having a size of m or less, embedding can be realized by coating once or twice.
【００１７】[0017]
【実施例】以下、実施例及び比較例を挙げて本発明を更
に詳細に説明する。但し本発明は何らこれらに限定され
るものではない。尚、実施例及び比較例中の各物性値は
新品ベアシリコンウエハ、再生ベアシリコンウエハ、パ
ターンウエハに塗布したものを適宜下記の方法に従って
測定した。 （１）スピンコート方法 スピナー１Ｈ３６０型（共栄セミコンダクター製）を使
用し、ＳＯＧ溶液を数ｍｌウエハ基板上に滴下し、６０
rpm ５秒、次いで４０００rpm １５秒間回転し、塗布膜
を得た。EXAMPLES The present invention will be described in more detail with reference to Examples and Comparative Examples. However, the present invention is not limited to these. Each physical property value in the examples and comparative examples was measured on a new bare silicon wafer, a recycled bare silicon wafer, and a pattern wafer coated by the following methods as appropriate. (1) Spin coating method Using a spinner 1H360 type (manufactured by Kyoei Semiconductor), several ml of the SOG solution was dropped on a wafer substrate, and 60
The coating film was obtained by rotating at 5 rpm for 15 seconds and then at 4000 rpm for 15 seconds.
【００１８】（２）ベーキング方法 ＳＯＧ膜をスピンコートしたウエハ基板をホットプレー
ト上に載せた後、クリンオーブンＤＴ４２Ｒ（ヤマト科
学社製）にて加熱硬化せしめた。 （３）膜厚の測定方法 エリプソメーター（偏向解析装置）Ｌ−２ｗ−１５ｃ−
８３０（ガードナー社製）にてシリコンウエハ基板上の
膜厚を測定した。 （４）再流動化 パターンウエハ上にスピンコートし、幅１００μｍ角、
高さ１μｍのパッド（幅広配線電極）部の塗膜形状を、
硬化前後（ホットプレート溶剤揮散後とクリンオーブン
加熱硬化後）について微分干渉顕微鏡、デクタックで測
定した。また、ＳＯＧ溶液を６０℃、１２時間加熱し溶
剤を揮散させた固体試料を作成し、高温型熱機械的分析
装置（ＴＭＡ３０：セイコー電子工業製）にて軟化点を
測定した。(2) Baking Method A wafer substrate on which an SOG film was spin-coated was placed on a hot plate and then heat-cured in a clean oven DT42R (manufactured by Yamato Scientific Co., Ltd.). (3) Method of measuring film thickness Ellipsometer (deflection analysis device) L-2w-15c-
The film thickness on the silicon wafer substrate was measured with 830 (manufactured by Gardner). (4) Re-fluidization A patterned wafer was spin-coated with a 100 μm square width,
The coating film shape of the pad (wide wiring electrode) with a height of 1 μm
Before and after curing (after volatilization of hot plate solvent and after curing by heating in a clean oven), measurement was performed by a differential interference microscope and Dectak. Moreover, the SOG solution was heated at 60 ° C. for 12 hours to volatilize the solvent to prepare a solid sample, and the softening point was measured by a high temperature thermomechanical analyzer (TMA30: manufactured by Seiko Denshi Kogyo KK).
【００１９】（５）平坦化特性 配線幅サブミクロン〜数μｍ、スペース幅サブミクロン
〜数十μｍにわたる様々なパターンを含むテストパター
ンウエハ上にＳＯＧをコートし成膜したときの断面ＳＥ
Ｍ観察により平坦化度をみた。 （６）微細穴埋め性 テストパターンウエハ上にＳＯＧをコートし成膜したと
きの半導体素子内での穴の直径１．０μｍ以下の井戸
状、蛸壷状など種々の形状の微細穴に対しての埋め込み
性を断面ＳＥＭ観察によりみた。結果は「大変良い」、
「良い」、「普通」、「悪い」で判定し、表１に各々、
◎、○、△、×で示した。(5) Flattening characteristics Cross-section SE when SOG is coated and formed on a test pattern wafer including various patterns having a wiring width of submicron to several μm and a space width of submicron to several tens of μm.
The degree of flatness was observed by M observation. (6) Fine hole filling property Filling into fine holes of various shapes such as well shape and octopus shape with a diameter of 1.0 μm or less in the semiconductor element when SOG is coated on the test pattern wafer to form a film. The sex was observed by cross-section SEM observation. The result is "very good",
Judged as “good”, “normal”, and “bad”, and shown in Table 1, respectively.
◎, ○, △, × are shown.
【００２０】（実施例１）前記一般式（１）において、
数平均分子量がＭｎ＝３０００、ポリメチルシルセスキ
オキサン１６重量部をエタノール、ブタノール、及び３
−メトキシプロピン酸メチル（ＭＭＰ）の混合溶剤（重
量比＝５５：２７：１８）８４重量部に溶解して塗布液
を得た。上記塗布液をベアシリコンウエハ上で３５００
Ａとなるようにパターンウエハ上にスピンコートし、ホ
ットプレートにて１８０℃２分溶剤を揮散させ、次いで
３５０℃３０分クリンオーブンにて硬化せしめた。硬化
後室温に冷却して諸物性を測定した。結果を表１に示
す。Example 1 In the above general formula (1),
The number average molecular weight was Mn = 3000, and 16 parts by weight of polymethylsilsesquioxane was added to ethanol, butanol, and 3 parts.
A coating solution was obtained by dissolving the mixture in 84 parts by weight of a mixed solvent of methyl methoxypropynate (MMP) (weight ratio = 55: 27: 18). 3500 the above coating solution on bare silicon wafer
A patterned wafer was spin-coated so as to have A, the solvent was volatilized for 2 minutes at 180 ° C. on a hot plate, and then cured at 350 ° C. for 30 minutes in a clean oven. After curing, it was cooled to room temperature and various physical properties were measured. The results are shown in Table 1.
【００２１】（実施例２）前記実施例１と同様のポリメ
チルシルセスキオキサン１７重量部をエタノール、ブタ
ノール、及びプロピレングリコールメチルエーテルアセ
テート（ＰＭＡ）の混合溶剤（重量比＝５５：２５：２
０）８３重量部に溶解して塗布液を得た。上記塗布液を
ベアシリコンウエハ上で４０００Ａとなるようにパター
ンウエハ上にスピンコートし、ホットプレートにて１８
０℃３分溶剤を揮散させ、次いで４００℃３０分クリン
オーブンにて硬化せしめた。硬化後室温に冷却して諸物
性を測定した。結果を表１に示す。Example 2 17 parts by weight of the same polymethylsilsesquioxane as in Example 1 was mixed with a mixed solvent of ethanol, butanol, and propylene glycol methyl ether acetate (PMA) (weight ratio = 55: 25: 2).
0) It was dissolved in 83 parts by weight to obtain a coating solution. The above coating solution was spin-coated on a bare wafer to give 4000 A on a patterned wafer, and a hot plate was used for 18
The solvent was stripped off at 0 ° C. for 3 minutes and then cured at 400 ° C. for 30 minutes in a clean oven. After curing, it was cooled to room temperature and various physical properties were measured. The results are shown in Table 1.
【００２２】（実施例３）前記実施例１と同様のポリメ
チルシルセスキオキサン１６重量部をエタノール、ブタ
ノール、及び乳酸エチルエーテルの混合溶剤（重量比＝
５５：２０：２５）８４重量部に溶解して塗布液を得
た。上記塗布液をベアシリコンウエハ上で３５００Ａと
なるようにパターンウエハ上にスピンコートし、ホット
プレートにて１８０℃２分溶剤を揮散させ、次いで４０
０℃３０分クリンオーブンにて硬化せしめた。硬化後室
温に冷却して諸物性を測定した。結果を表１に示す。Example 3 16 parts by weight of the same polymethylsilsesquioxane as in Example 1 was mixed with a mixed solvent of ethanol, butanol, and ethyl lactate ether (weight ratio =
55:20:25) 84 parts by weight to obtain a coating solution. The above coating solution was spin-coated on a bare silicon wafer so as to give 3500 A, and the solvent was stripped off with a hot plate at 180 ° C. for 2 minutes.
It was cured in a clean oven at 0 ° C. for 30 minutes. After curing, it was cooled to room temperature and various physical properties were measured. The results are shown in Table 1.
【００２３】（実施例４）前記実施例１と同様のポリメ
チルシルセスキオキサン１７重量部をエタノール、ブタ
ノール、及びプロピレングリコールメチルエーテルアセ
テート（ＰＭＡ）の混合溶剤（重量比＝５５：２５：２
０）８３重量部に溶解して塗布液を得た。上記塗布液を
ベアシリコンウエハ上で４０００Ａとなるようにパター
ンウエハ上にスピンコートし、ホットプレートにて２５
０℃３分溶剤を揮散させ、次いで４００℃３０分クリン
オーブンにて硬化せしめた。硬化後室温に冷却して諸物
性を測定した。結果を表１に示す。Example 4 17 parts by weight of the same polymethylsilsesquioxane as in Example 1 was mixed with a mixed solvent of ethanol, butanol and propylene glycol methyl ether acetate (PMA) (weight ratio = 55: 25: 2).
0) It was dissolved in 83 parts by weight to obtain a coating solution. The above coating solution is spin-coated on a patterned wafer so as to be 4000 A on a bare silicon wafer.
The solvent was stripped off at 0 ° C. for 3 minutes and then cured at 400 ° C. for 30 minutes in a clean oven. After curing, it was cooled to room temperature and various physical properties were measured. The results are shown in Table 1.
【００２４】（比較例１）前記実施例１と同様のポリメ
チルシルセスキオキサン１３重量部をエタノール、ブタ
ノールの混合溶剤（重量比＝５５：４５）８７重量部に
溶解して塗布液を得た。上記塗布液をベアシリコンウエ
ハ上で４０００Ａとなるようにパターンウエハ上にスピ
ンコートし、ホットプレートにて１８０℃３分溶剤を揮
散させ、次いで４００℃３０分クリンオーブンにて硬化
せしめた。硬化後室温に冷却して諸物性を測定した。結
果を表１に示す。Comparative Example 1 13 parts by weight of the same polymethylsilsesquioxane as in Example 1 was dissolved in 87 parts by weight of a mixed solvent of ethanol and butanol (weight ratio = 55: 45) to obtain a coating solution. It was The above coating solution was spin-coated on a bare silicon wafer to give 4000 A on a patterned wafer, the solvent was evaporated on a hot plate for 3 minutes at 180 ° C., and then cured at 400 ° C. for 30 minutes in a clean oven. After curing, it was cooled to room temperature and various physical properties were measured. The results are shown in Table 1.
【００２５】（比較例２）メチルトリヒドロキシシラン
１４重量部をメタノールとプロピレングリコールブチル
エーテル（ＰＧＢ）の混合溶剤（重量比＝３０：７０）
８６重量部に溶解した塗布液を用いて、実施例１と同様
にスピンコートし、ホットプレートにて１８０℃３分溶
剤を揮散させ、次いで４００℃３０分クリンオーブンに
て硬化せしめた。硬化後室温に冷却して諸物性を測定し
た。結果を表１に示す。Comparative Example 2 14 parts by weight of methyltrihydroxysilane were mixed with a mixed solvent of methanol and propylene glycol butyl ether (PGB) (weight ratio = 30: 70).
Using the coating liquid dissolved in 86 parts by weight, spin coating was performed in the same manner as in Example 1, the solvent was stripped off on a hot plate at 180 ° C. for 3 minutes, and then cured at 400 ° C. for 30 minutes in a clean oven. After curing, it was cooled to room temperature and various physical properties were measured. The results are shown in Table 1.
【００２６】[0026]
【表１】 [Table 1]
【００２７】[0027]
【発明の効果】本発明により、従来の有機ＳＯＧを使用
した場合には多数回の塗布により行っていた、微細配線
を含むパターンの平坦性並びに半導体素子内に各種機能
を発現させるための微細穴の穴埋め性についての問題点
を、１〜２回の塗布により解決すると同時に、将来の高
集積化（より微細なパターン）、多層配線化に伴う、質
の高い平坦性の要求（安全平坦化）や微細穴の穴埋め性
を達成し得る、実用性のある半導体用絶縁膜及びまたは
平坦化膜及びそれらの形成方法が提供される。According to the present invention, the flatness of the pattern including the fine wiring and the fine holes for expressing various functions in the semiconductor element, which have been carried out by applying a large number of times when the conventional organic SOG is used, are obtained. The problem of the hole filling property is solved by coating once or twice, and at the same time, the demand for high-quality flatness (safety flattening) due to future high integration (finer pattern) and multilayer wiring. There is provided a practicable insulating film for semiconductor and / or a planarizing film and a method for forming the same, which can achieve filling of fine holes.
Claims (2)
半導体素子をコーティングするに際し、下記一般式
（１）で示される数平均分子量５００〜１０，０００の
ポリメチルシルセスキオキサン 【化１】 （式中、Ｒ1 はメチル基を、Ｒ2 は炭素数１〜４のアル
キル基及び／または水素原子を示し、ｎは分子量に対応
する正の数である。）を下記一般式（２）〜（５）で示
される溶剤 Ｒ3 −Ｏ−Ｒ4 −ＯＣＯＲ5 （２） Ｒ6 −Ｏ−Ｒ7 −ＣＯＯＲ8 （３） Ｒ9 ＣＨ（ＯＨ）ＣＯＯＲ10 （４） Ｒ11ＣＨ（ＯＲ12）ＣＯＯＲ13 （５） （式中、Ｒ3 、Ｒ5 、Ｒ6 、Ｒ8 〜Ｒ13は炭素数１〜４
のアルキル基を、Ｒ4、Ｒ7 はアルキル基で置換可能な
炭素数２〜４のアルキレン基を示す。）の一種または二
種以上の混合物を含む溶剤に溶解させた溶液を使用し、
該微細穴を埋め込むことを特徴とする半導体用絶縁膜ま
たは平坦化膜の形成方法。1. A polymethylsilsesquioxane having a number average molecular weight of 500 to 10,000 represented by the following general formula (1) when coating a semiconductor device having fine holes having a diameter of 1 μm or less: (In the formula, R 1 represents a methyl group, R 2 represents an alkyl group having 1 to 4 carbon atoms and / or a hydrogen atom, and n is a positive number corresponding to the molecular weight.) Is represented by the following general formula (2). To a solvent represented by (5) R 3 —O—R 4 —OCOR 5 (2) R 6 —O—R 7 —COOR 8 (3) R 9 CH (OH) COOR 10 (4) R 11 CH (OR 12 ) COOR 13 (5) (In the formula, R 3 , R 5 , R 6 , and R 8 to R 13 have 1 to 4 carbon atoms.
And the alkyl groups R 4 and R 7 each represent an alkylene group having 2 to 4 carbon atoms which can be substituted with an alkyl group. ) Or a solution containing a mixture of two or more of
A method for forming an insulating film for a semiconductor or a planarization film, which comprises filling the fine holes.
せた溶液を半導体素子上にコーティングした後、１００
〜２００℃の温度で溶剤を蒸発させ次いで２００〜５０
０℃の温度で加熱硬化させて、ポリメチルシルセスキオ
キサンの軟化による再流動化をさせる請求項１に記載の
半導体用絶縁膜または平坦化膜の形成方法。2. A semiconductor device is coated with a solution in which polymethylsilsesquioxane is dissolved, and then 100
Evaporate the solvent at a temperature of ~ 200 ° C and then 200-50
The method for forming an insulating film for a semiconductor or a flattening film according to claim 1, wherein the polymethylsilsesquioxane is softened by heating to be re-fluidized by being hardened at a temperature of 0 ° C. 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26745793A JP3339135B2 (en) | 1993-10-26 | 1993-10-26 | Method of forming insulating film or flattening film for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26745793A JP3339135B2 (en) | 1993-10-26 | 1993-10-26 | Method of forming insulating film or flattening film for semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07122551A true JPH07122551A (en) | 1995-05-12 |
| JP3339135B2 JP3339135B2 (en) | 2002-10-28 |
Family
ID=17445113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26745793A Expired - Fee Related JP3339135B2 (en) | 1993-10-26 | 1993-10-26 | Method of forming insulating film or flattening film for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3339135B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100373215B1 (en) * | 2001-02-01 | 2003-02-25 | 주식회사 엘지화학 | Method for preparing low dielectric materials for semiconductor ic device |
| KR100440488B1 (en) * | 2001-12-27 | 2004-07-14 | 주식회사 엘지화학 | Organic silicate polymer for insulation film of the semiconductor device and low dielectric insulation film comprising the same |
| US6888183B1 (en) | 1999-03-03 | 2005-05-03 | Yamaha Corporation | Manufacture method for semiconductor device with small variation in MOS threshold voltage |
| JP2014072248A (en) * | 2012-09-27 | 2014-04-21 | Asahi Kasei E-Materials Corp | Condensation product solution for trench filling, and method for manufacturing trench-filling film |
-
1993
- 1993-10-26 JP JP26745793A patent/JP3339135B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6888183B1 (en) | 1999-03-03 | 2005-05-03 | Yamaha Corporation | Manufacture method for semiconductor device with small variation in MOS threshold voltage |
| KR100373215B1 (en) * | 2001-02-01 | 2003-02-25 | 주식회사 엘지화학 | Method for preparing low dielectric materials for semiconductor ic device |
| KR100440488B1 (en) * | 2001-12-27 | 2004-07-14 | 주식회사 엘지화학 | Organic silicate polymer for insulation film of the semiconductor device and low dielectric insulation film comprising the same |
| JP2014072248A (en) * | 2012-09-27 | 2014-04-21 | Asahi Kasei E-Materials Corp | Condensation product solution for trench filling, and method for manufacturing trench-filling film |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3339135B2 (en) | 2002-10-28 |
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| LAPS | Cancellation because of no payment of annual fees |