JPH07114245B2 - Semiconductor envelope - Google Patents
Semiconductor envelopeInfo
- Publication number
- JPH07114245B2 JPH07114245B2 JP61245316A JP24531686A JPH07114245B2 JP H07114245 B2 JPH07114245 B2 JP H07114245B2 JP 61245316 A JP61245316 A JP 61245316A JP 24531686 A JP24531686 A JP 24531686A JP H07114245 B2 JPH07114245 B2 JP H07114245B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- pins
- envelope
- pin
- aluminum nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔発明の目的〕 （産業上の利用分野） この発明は超LSIなどの半導体装置の半導体外囲器に関
する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor package for a semiconductor device such as a VLSI.
（従来の技術） 論理回路を含む超LSI（ゲート数Ｇ＞105）では、収納す
る回路規模が大きいため、入出力端子数Ｐが大きくな
る。両者の関係はRentの式として、Ｇ＜104の範囲で経
験的におおむね、 として知られているが、VLSI（超LSI）では上式が成立
しなく、Ｇ＝105程度ではＰ＝200〜300である。(Prior Art) In a VLSI including a logic circuit (the number of gates G> 10 5 ), the number of input / output terminals P is large because the circuit scale to be accommodated is large. The relationship between the two is empirically roughly within the range of G <10 4 as the Rent formula, However, in VLSI (VLSI), the above equation does not hold, and at G = 10 5 , P = 200 to 300.
このような多ピンの外囲器としてはピングリップアレイ
パッケージと呼ばれる半導体外囲器が最もよく使われて
いる。A semiconductor package called a pin grip array package is most often used as such a multi-pin package.
第３図は従来例を説明するセラミックピングリッドアレ
イパッケージの断面図である。IC31は多層配線をほどこ
したセラミック32上に搭置されており、ピン3a,3b,…，
がろう接されている。FIG. 3 is a sectional view of a ceramic pin grid array package for explaining a conventional example. The IC 31 is mounted on the ceramic 32 with multi-layered wiring, and the pins 3a, 3b, ...,
They are in contact with each other.
放熱の為のフィン34がピン33a,33b,…とは反対の面に接
合されており、IC31からの発熱を大気中に効率よく放散
させている。The fins 34 for heat dissipation are joined to the surface opposite to the pins 33a, 33b, ..., Efficiently dissipating the heat generated from the IC 31 into the atmosphere.
空洞35の周囲は蓋36がおおっており、これはコバール製
封止止リング37を介してシームウエルドされている。Around the periphery of the cavity 35 is a lid 36, which is seam welded via a Kovar sealing ring 37.
このような従来構造では、ピン33a,33b,…は、空洞部を
除いた余地にしか配置できないため、ピンの数に制約を
受けるか、またはピンの数を増やす為に外囲器外形寸法
を大きくするかをしなければならない。In such a conventional structure, the pins 33a, 33b, ... Can be arranged only in the room excluding the hollow portion, so that the outer dimensions of the envelope are limited in order to limit the number of pins or increase the number of pins. I have to make it bigger.
VLSIのようにピン数が200を超える場合には配列が多く
なり、従来構造では外囲器を大形化しなくてはならない
との不都合があった。When the number of pins exceeds 200 as in VLSI, the array becomes large, and the conventional structure had a disadvantage that the envelope had to be enlarged.
また論理VLSIではIC動作時の発熱が１〜10Wと大きい
為、放熱性の優れた外囲器が必要である。この為、200
ピン以上の超多ピンで５℃/W以下の低熱抵抗（Rth（j-
a））を同時に満足する外囲器が望まれていた。In addition, since the logic VLSI generates a large amount of heat during operation of the IC, which is 1 to 10 W, an enclosure with excellent heat dissipation is required. Therefore, 200
High thermal resistance (Rth (j-
An envelope that satisfies both a)) was desired.
（発明が解決しようとする問題点） 200ピン以上のピン数を持つ外囲器を小形でかつ放熱性
の優れた形で構成したいとの要望があった。(Problems to be Solved by the Invention) There has been a demand for an envelope having a pin number of 200 pins or more to be compact and have excellent heat dissipation.
すなわち、本発明は外囲器形状を大きくすることなく多
ピン（200以上）化することのできる半導体外囲器を提
供することを目的とする。That is, it is an object of the present invention to provide a semiconductor envelope capable of increasing the number of pins (200 or more) without increasing the size of the envelope.
また、本発明は放熱特性の優れた半導体外囲器を提供す
ることを目的とする。Another object of the present invention is to provide a semiconductor package having excellent heat dissipation characteristics.
（問題点を解決するための手段） 本発明は主面に、半導体素子が配置される凹部を有する
窒化アルミニウムセラミック基板と、この窒化アルミニ
ウム基板の前記主面と対向する面に設けられた複数の端
子ピンと、前記主面上の前記凹部の周辺にのみ設けられ
た放熱フィンとを具備することを特徴とする半導体外囲
器を提供するものである。。(Means for Solving Problems) In the present invention, the main surface of the aluminum nitride ceramic substrate has a recess in which a semiconductor element is arranged, and a plurality of aluminum nitride ceramic substrates provided on the surface facing the main surface. The present invention provides a semiconductor package including a terminal pin and a radiation fin provided only around the recess on the main surface. .
本発明は放熱フィンを空洞の周辺に設け空洞の上部には
設けない構造をとることによって、フィンの間を流れる
空気抵抗を小さくすることを可能とし、放熱フィンの間
を流れる空気の通りを良くすることができるので装置の
放熱効果を格段に向上させることができる。The present invention makes it possible to reduce the air resistance flowing between the fins by adopting a structure in which the heat radiation fins are provided around the cavities and not at the upper part of the cavities, and the air flowing between the heat radiating fins is improved. As a result, the heat dissipation effect of the device can be significantly improved.
また、本発明は、基板として熱伝導率の良好な窒化アル
ミニウムを採用することによって、半導体素子で発熱さ
れた熱は効率よくこの特徴ある放熱フィンに導くことが
可能であるので、極めて高い放熱特性を有する半導体外
囲器を提供できるものである。Further, according to the present invention, by adopting aluminum nitride having a good thermal conductivity as the substrate, the heat generated in the semiconductor element can be efficiently guided to this characteristic heat radiation fin, so that the heat radiation characteristic is extremely high. It is possible to provide a semiconductor envelope having
更に、本発明は上記のような放熱特性の良い放熱フィン
を具備しているので、放熱フィンは基板の空洞が形成さ
れた面に設けることができる。従って端子ピンを空洞と
対向する面に設けることを可能とし、放熱効果を向上さ
せつつ更に多ピン化を実現する半導体外囲器を提供でき
るものである。Further, since the present invention includes the heat radiation fin having good heat radiation characteristics as described above, the heat radiation fin can be provided on the surface of the substrate on which the cavity is formed. Therefore, it is possible to provide the terminal pin on the surface facing the cavity, and it is possible to provide a semiconductor envelope in which the number of pins is further increased while improving the heat dissipation effect.
（作用） ピンを空洞（半導体取付側）とは反対面に配置すること
によりセラミック基板全面にピン立てし、超多ピン構造
を可能にする。また、セラミック基板にAlNセラミック
を用いることにより、熱抵抗を低下させ、ひいては全体
の熱抵抗を下げる。(Function) By arranging the pins on the surface opposite to the cavity (semiconductor mounting side), the pins are erected on the entire surface of the ceramic substrate, enabling a super-multi-pin structure. Also, by using AlN ceramic for the ceramic substrate, the thermal resistance is lowered, which in turn lowers the overall thermal resistance.
（実施例） 以下、本発明の実施例について、詳細に説明する。第１
図は本発明による半導体外囲器を示す断面図である。(Example) Hereinafter, the Example of this invention is described in detail. First
FIG. 1 is a sectional view showing a semiconductor package according to the present invention.
ピン11a,11b,…11nはセラミック基板15の下面全面に所
定間隙を有して配設されている。反対面のセラミック基
板15の上面には、冷却用のフィン13と空洞12内に埋設さ
れている集積回路（IC）14が設けられている。セラミッ
ク基板15としては窒化アルミニウム（AlN）が用いられ
ている。このAlN基板15はAlN原料粉と常圧焼結助剤酸化
イットリウムY2O33wt％を含む粉体を泥しよう化し、ス
ラリを得た。厚さ0.7mmにシート成形後、切断成形（空
洞部）し、タングステン（Ｗ）を主体とする導体ペース
トで所定の配線部を印刷した。The pins 11a, 11b, ... 11n are arranged on the entire lower surface of the ceramic substrate 15 with a predetermined gap. A fin 13 for cooling and an integrated circuit (IC) 14 embedded in the cavity 12 are provided on the upper surface of the opposite ceramic substrate 15. Aluminum nitride (AlN) is used as the ceramic substrate 15. The AlN substrate 15 was made into a slurry by making AlN raw material powder and powder containing the atmospheric pressure sintering aid yttrium oxide Y 2 O 3 3 wt% into a sludge. After forming the sheet to a thickness of 0.7 mm, the sheet was cut and formed (hollow portion), and a predetermined wiring portion was printed with a conductor paste mainly containing tungsten (W).
積層後、700℃，N2雰囲気中で4h脱脂した。1800℃，N2
雰囲気下で２時間焼結を進行させ、焼結体を得た。Niめ
っき（２μｍ）を実施後、ピンをろう接した。続いて再
びNiメッキ後、金Auを２μｍ形成しパッケージを得た。After stacking, degreasing was performed for 4 hours in a N 2 atmosphere at 700 ° C. 1800 ℃, N 2
Sintering was allowed to proceed for 2 hours in an atmosphere to obtain a sintered body. After performing Ni plating (2 μm), the pins were brazed. Then, after nickel plating again, gold Au was formed to a thickness of 2 μm to obtain a package.
この時のピン配置を第２図に示した。総ピン数は301で
あり、ピッチは2.54mmとした。The pin arrangement at this time is shown in FIG. The total number of pins was 301 and the pitch was 2.54 mm.
第２図はピン側から見たものである為、空洞部は直接見
えないが、破線にてこの時の空洞21を示した。空洞部に
も16本のピンを立てることにより、小形で301ピンの配
置ができた。（従来の構造の周辺部ピン立て方式では外
形寸法が、2.54×２＝5.08mm大きくなる。） Al放熱フィンを空洞側に熱伝導性銀エポキシ系接着剤で
貼り合わせた。この時の熱抵抗は３℃/W（4m/Sの強制空
冷）となり、多ピンと低熱抵抗を同時に満足することが
できた。Since FIG. 2 is viewed from the pin side, the cavity cannot be seen directly, but the cavity 21 at this time is shown by a broken line. By arranging 16 pins in the cavity, we were able to arrange 301 pins in a small size. (In the conventional peripheral pin-placing method, the external dimensions are larger by 2.54 × 2 = 5.08 mm.) The Al radiation fins were attached to the cavity side with a thermally conductive silver epoxy adhesive. At this time, the thermal resistance was 3 ° C / W (4m / S forced air cooling), and we were able to satisfy both high pin count and low thermal resistance at the same time.
本発明によれば、ピン11a,11b,…を空洞12とは反対の面
に配置して外囲器形状の中央部にもピン11nを立てられ
るようにして多ピン化を実現しやすく、放熱フィン13を
空洞（キャビティ）側に配置して放熱作用を行なわせ、
発熱部としてのIC14と、フィンまでの熱抵抗を低下させ
る為に従来のアルミナの10倍以上の熱伝導率を有する窒
化アルミニウム（AlN）15をセラミック材料として使用
するとの３つの作用を同時に行なわせることで、超多ピ
ン、低熱抵抗（接合−空気間）を満足する。VLSIに適し
た外囲器を構成することができる。According to the present invention, the pins 11a, 11b, ... Are arranged on the surface opposite to the cavity 12 so that the pin 11n can be set up in the central portion of the envelope shape, so that it is easy to realize a large number of pins and the heat dissipation is improved. The fins 13 are arranged on the cavity side for heat dissipation,
The IC14 as a heat generating part and aluminum nitride (AlN) 15, which has a thermal conductivity 10 times or more that of conventional alumina to reduce the thermal resistance to the fin, are used as a ceramic material at the same time. By doing so, ultra-high pin count and low thermal resistance (between junction and air) are satisfied. An envelope suitable for VLSI can be configured.
第１図は本実施例を説明するパッケージ断面図、第２図
はピン配列と空洞との関係をしめす平面図、第３図は従
来構造のパッケージの断面図である。 11a,11b…11n…ピン、12…空洞、13…放熱フィン、14…
IC、15…セラミック。FIG. 1 is a sectional view of a package for explaining the present embodiment, FIG. 2 is a plan view showing the relationship between a pin array and a cavity, and FIG. 3 is a sectional view of a package having a conventional structure. 11a, 11b ... 11n ... Pin, 12 ... Cavity, 13 ... Radiating fin, 14 ...
IC, 15… ceramic.
Claims (3)
する窒化アルミニウムセラミック基板と、 この窒化アルミニウム基板の前記主面と対向する面に設
けられた複数の端子ピンと、 前記主面上の前記凹部の周辺にのみ設けられた放熱フィ
ンとを具備することを特徴とする半導体外囲器。1. An aluminum nitride ceramic substrate having a recess in which a semiconductor element is arranged on a main surface, a plurality of terminal pins provided on a surface of the aluminum nitride substrate facing the main surface, and on the main surface. A semiconductor envelope, comprising: a radiation fin provided only around the recess.
窒化アルミニウムに伝導し、更に前記放熱フィンに伝導
され、この放熱フィンにより放熱されることを特徴とす
る特許請求の範囲第１項記載の半導体外囲器。2. The heat generated from the semiconductor element is conducted to the aluminum nitride, further conducted to the heat radiation fins, and is radiated by the heat radiation fins. Semiconductor enclosure.
成されていることを特徴とする特許請求の範囲第１項或
いは第２項記載の半導体外囲器。3. The semiconductor envelope according to claim 1 or 2, wherein the terminal pin is formed on a surface facing the recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61245316A JPH07114245B2 (en) | 1986-10-17 | 1986-10-17 | Semiconductor envelope |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61245316A JPH07114245B2 (en) | 1986-10-17 | 1986-10-17 | Semiconductor envelope |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63100758A JPS63100758A (en) | 1988-05-02 |
| JPH07114245B2 true JPH07114245B2 (en) | 1995-12-06 |
Family
ID=17131854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61245316A Expired - Fee Related JPH07114245B2 (en) | 1986-10-17 | 1986-10-17 | Semiconductor envelope |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07114245B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02192198A (en) * | 1989-01-20 | 1990-07-27 | Nippon Cement Co Ltd | Multilayer interconnection board mounted with ic chip |
| JPH04192552A (en) * | 1990-11-27 | 1992-07-10 | Nec Corp | Package for semiconductor use |
| EP0544329A3 (en) * | 1991-11-28 | 1993-09-01 | Kabushiki Kaisha Toshiba | Semiconductor package |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4092697A (en) * | 1976-12-06 | 1978-05-30 | International Business Machines Corporation | Heat transfer mechanism for integrated circuit package |
| JPH0134351Y2 (en) * | 1980-11-14 | 1989-10-19 |
-
1986
- 1986-10-17 JP JP61245316A patent/JPH07114245B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63100758A (en) | 1988-05-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |