JPH07106614A - Production of semiconductor element - Google Patents
Production of semiconductor elementInfo
- Publication number
- JPH07106614A JPH07106614A JP5244398A JP24439893A JPH07106614A JP H07106614 A JPH07106614 A JP H07106614A JP 5244398 A JP5244398 A JP 5244398A JP 24439893 A JP24439893 A JP 24439893A JP H07106614 A JPH07106614 A JP H07106614A
- Authority
- JP
- Japan
- Prior art keywords
- film
- transparent conductive
- conductive film
- ito
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Photovoltaic Devices (AREA)
- Liquid Crystal (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は透明導電膜および該膜上
に半導体膜を形成して成る半導体素子に関し、特に透明
基体上に形成される透明導電膜であって更に該膜上に半
導体膜が積層して形成される半導体素子の製法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transparent conductive film and a semiconductor element formed by forming a semiconductor film on the transparent conductive film, and more particularly to a transparent conductive film formed on a transparent substrate, which further has a semiconductor film formed thereon. The present invention relates to a method of manufacturing a semiconductor element formed by stacking.
【0002】[0002]
【従来の技術】透明基体上に形成される半導体素子、例
えば液晶ディスプレイパネルやELディスプレイパネ
ル、密着型イメージセンサ、電子写真感光体などにおい
ては、その透明基体としてガラスや樹脂フィルムなど導
電性を有しない材料が用いられることが多いが、基体に
は透明性と同時に導電性も要求されることがほとんどで
ある。その場合、透明基体の半導体膜が形成される面に
透明性を維持しつつ導電性を持たせるために、基体上に
薄膜形成手段により透明導電膜が形成されることが一般
に行なわれている。このような透明導電膜としては、通
常、ITO(インジウム・スズ・酸化物)やIn2 O3
(酸化インジウム)、SnO2 (二酸化スズ)などが使
用されている。2. Description of the Related Art In a semiconductor element formed on a transparent substrate such as a liquid crystal display panel, an EL display panel, a contact type image sensor, and an electrophotographic photosensitive member, the transparent substrate has conductivity such as glass or resin film. Often, non-use materials are used, but in most cases, the substrate is required to have conductivity as well as transparency. In that case, a transparent conductive film is generally formed on the substrate by means of a thin film forming means in order to have conductivity while maintaining transparency on the surface of the transparent substrate on which the semiconductor film is formed. Such a transparent conductive film is usually ITO (indium tin oxide) or In 2 O 3
(Indium oxide), SnO 2 (tin dioxide), etc. are used.
【0003】[0003]
【発明が解決しようとする問題点】透明導電膜として広
く用いられているITOは、例えばスパッタリング法や
イオンプレーティング法、活性反応蒸着法などの薄膜形
成方法により大面積への成膜が可能で、エッチングによ
るパターン形成などの加工性が良好な優れた性質を有し
ているが、その反面、その膜上にプラズマCVD法によ
って半導体膜を積層する場合に、プラズマによるダメー
ジを受けやすく、膜表面の荒れや変色による透明性の低
下を生じやすいという問題も有している。ITO, which is widely used as a transparent conductive film, can be formed on a large area by a thin film forming method such as a sputtering method, an ion plating method, or an active reaction vapor deposition method. Although it has excellent properties such as good patternability by etching, on the other hand, when a semiconductor film is laminated on the film by a plasma CVD method, it is easily damaged by plasma and the film surface There is also a problem that the transparency is likely to be deteriorated due to the roughness and discoloration.
【0004】また、半導体膜を形成するためのプラズマ
が水素ラジカルなどの還元性活性種を含んでいると、I
TO膜と基体との密着性が低下し、半導体膜を積層した
後で、その半導体膜の応力によってITO膜の剥離が発
生するという問題もあった。このような剥離の発生は、
半導体膜の成膜中に剥離片が飛散して半導体膜が成膜さ
れる製品の欠陥の原因となるほか、製品を使用している
際に剥離が発生する可能性もあり、製品の信頼性に対し
て重大な問題点となる。If the plasma for forming the semiconductor film contains reducing active species such as hydrogen radicals, I
There is also a problem that the adhesion between the TO film and the substrate is lowered, and after the semiconductor films are laminated, the stress of the semiconductor film causes the peeling of the ITO film. The occurrence of such peeling is
The reliability of the product is high because peeling pieces may scatter during the formation of the semiconductor film, which may cause defects in the product in which the semiconductor film is formed and peeling may occur during use of the product. It becomes a serious problem for.
【0005】上記のような透明導電膜の剥離対策とし
て、特開平2−109294号には、透明電極が形成さ
れるガラス基板に、透明電極の膜厚の半分に匹敵する程
度の凹凸を設けることが開示されているが、大面積の基
板にそのような微細な加工を均一に施すことは技術的に
もコスト的にも困難であり、しかもプラズマによるダメ
ージを受けやすいという問題は残されていた。As a measure against peeling of the transparent conductive film as described above, Japanese Patent Laid-Open No. 2-109294 discloses that a glass substrate on which a transparent electrode is formed is provided with irregularities of a size comparable to half the film thickness of the transparent electrode. However, it has been technically and costly difficult to uniformly perform such fine processing on a large-area substrate, and there is a problem that plasma is easily damaged. .
【0006】また特開平2−1519号には、酸化イン
ジウムを主成分とする透明導電層の(222)面の配向
度を50%以上にすることが開示されているが、これは
ショットキーバリア構造の接合特性を改良するものであ
って、上記の剥離やダメージの問題は改善されておら
ず、特定の結晶面の配向度を大面積の基板上で均一に制
御することは技術的にも困難であった。さらにITO膜
表面のプラズマによるダメージを軽減する対策として、
ITO膜上にプラズマによるダメージに強いSnO2 を
薄く積層することも行なわれているが、このように異な
る材料からなる2種類の膜を積層することは、透明導電
膜を成膜する装置の構造や条件の複雑化をもたらし製造
上不利となると共に、2種類の膜の界面で光の反射が生
じたり透明導電膜全体としての光透過率が低下する問題
もあり、加えてSnO2 はエッチングによる加工性がI
TOより劣るため、パターン形成に際しても不利となっ
ていた。Further, Japanese Patent Laid-Open No. 2-1519 discloses that the degree of orientation of the (222) plane of the transparent conductive layer containing indium oxide as a main component is set to 50% or more. This is a Schottky barrier. This is to improve the bonding characteristics of the structure, the problems of peeling and damage described above have not been improved, and it is technically impossible to uniformly control the degree of orientation of a specific crystal plane on a large-area substrate. It was difficult. Furthermore, as a measure to reduce the damage caused by the plasma on the ITO film surface,
Although it has been practiced to thinly deposit SnO 2 which is resistant to plasma damage on the ITO film, it is necessary to stack two kinds of films made of different materials in this way to form a transparent conductive film forming device. with the production resulted in complication of or disadvantaged, there is also a problem that two types of film interface in the light transmittance of the entire transparent conductive film or resulting reflection of light is reduced, by addition SnO 2 by etching Workability is I
Since it is inferior to TO, it was also disadvantageous in pattern formation.
【0007】さらに特開平3−261005号には、ス
パッタリング法により、高抵抗な第一ITO膜の表面に
低抵抗な第二ITO膜を積層した二層膜構造の透明導電
膜を形成することが開示されているが、これは低抵抗で
かつパターニング時のエッチング特性を向上させた透明
導電膜を得るためのもので、上記の剥離やダメージの問
題は同じく改善されていなかった。Further, in JP-A-3-261005, a transparent conductive film having a two-layer film structure in which a low-resistance second ITO film is laminated on the surface of a high-resistance first ITO film can be formed by a sputtering method. Although disclosed, this is to obtain a transparent conductive film having low resistance and improved etching characteristics at the time of patterning, and the problems of peeling and damage have not been similarly improved.
【0008】また、ITO透明導電膜の表面に凹凸を設
けることにより半導体膜の応力を緩和して膜剥離を抑制
できることから、本発明者は特願平5−161270号
において、平均結晶粒径を規定したITO透明導電膜を
提案した。しかし、透明導電膜の表面に形成した凹凸が
あまり大きくなると、この透明導電膜の耐環境性が低下
するという問題があることが判り、この点の改善のため
に本発明者は鋭意研究を継続してきた。Further, since the stress of the semiconductor film can be relieved and the film peeling can be suppressed by providing irregularities on the surface of the ITO transparent conductive film, the present inventor has disclosed the average crystal grain size in Japanese Patent Application No. 5-161270. A specified ITO transparent conductive film was proposed. However, it was found that if the irregularities formed on the surface of the transparent conductive film were too large, the environment resistance of this transparent conductive film would deteriorate, and the inventors of the present invention continued diligent research to improve this point. I've been
【0009】本発明は、上記の問題点を透明導電膜の改
良により解決すべくなされた、透明導電膜および半導体
素子の製法であり、透明導電膜の改善によって、技術的
な困難さや膜形成に係るコストの増加をもたらすことな
く、透明導電膜表面の荒れや変色による透明性の低下お
よび半導体膜を積層した後の透明導電膜の剥離の発生を
抑制し、さらに耐環境性を向上した透明導電膜および半
導体素子を提供することを目的とする。The present invention is a method for producing a transparent conductive film and a semiconductor element, which has been made to solve the above-mentioned problems by improving a transparent conductive film. The improvement of the transparent conductive film causes technical difficulties and film formation. A transparent conductive film that suppresses the deterioration of the transparency due to the surface roughness and discoloration of the transparent conductive film and the peeling of the transparent conductive film after the semiconductor films are laminated without further increasing the cost, and further improves the environmental resistance. An object is to provide a film and a semiconductor device.
【0010】[0010]
【問題点を解決するための手段】本発明の半導体素子の
製法は、透明基体上に薄膜形成手段により、平均結晶粒
径が0.025μm以上であるITO結晶を有する第1
の透明導電膜と、平均結晶粒径が0.025μm未満で
あるITO結晶を有する第2の透明導電膜を順次形成す
るとともに、該第2の透明導電膜上に還元性活性種を含
むプラズマにより半導体膜を形成することを特徴とする
ものである。A method of manufacturing a semiconductor device according to the present invention comprises a first step of forming an ITO crystal having an average crystal grain size of 0.025 μm or more on a transparent substrate by a thin film forming means.
And a second transparent conductive film having ITO crystals having an average crystal grain size of less than 0.025 μm are sequentially formed, and a plasma containing a reducing active species is formed on the second transparent conductive film. It is characterized in that a semiconductor film is formed.
【0011】[0011]
【作用】透明基体上に薄膜形成手段により形成されたI
TO透明導電膜の上に、水素ラジカルなどの還元性活性
種を含むプラズマを用いて別種の半導体膜を形成する
と、その別種半導体膜内および別種半導体膜とITO膜
との間に応力が発生する。その応力がITO膜と透明基
体との密着性より強くなると、ITO膜の剥離を発生さ
せる。このような剥離の発生を抑制し、さらに耐環境性
を向上するべく本発明の製法により作製された半導体素
子の層構成を、図1に断面図で示す。同図によれば、透
明基体1の上に、第1の透明導電膜2と第2の透明導電
膜3とが順次積層され、さらにその上に半導体膜4が形
成された構成となっている。Operation: I formed on the transparent substrate by the thin film forming means
When another type of semiconductor film is formed on the TO transparent conductive film using plasma containing a reducing active species such as hydrogen radicals, stress is generated in the another type of semiconductor film and between the other type of semiconductor film and the ITO film. . When the stress becomes stronger than the adhesion between the ITO film and the transparent substrate, the ITO film is peeled off. FIG. 1 is a sectional view showing the layer structure of a semiconductor element manufactured by the manufacturing method of the present invention in order to suppress the occurrence of such peeling and further improve the environment resistance. According to the figure, the first transparent conductive film 2 and the second transparent conductive film 3 are sequentially laminated on the transparent substrate 1, and the semiconductor film 4 is further formed thereon. .
【0012】このような半導体素子に用いられる透明基
体1としては、パイレックスガラスやソーダガラス、ホ
ウ珪酸ガラス等のガラスや、石英やサファイア等の透明
な無機質系、並びに弗素樹脂やポリエステル、ポリカー
ボネート、ポリエチレンテレフタレート、ビニロン、エ
ポキシ、マイラー等の透明な有機樹脂系が挙げられ、平
板状やシート状、ドラム状あるいはベルト状等の形状で
用いられる。As the transparent substrate 1 used for such a semiconductor device, glass such as Pyrex glass, soda glass, borosilicate glass, transparent inorganic materials such as quartz and sapphire, and fluororesin, polyester, polycarbonate, polyethylene. Examples thereof include transparent organic resin materials such as terephthalate, vinylon, epoxy, mylar, etc., and they are used in a flat plate shape, a sheet shape, a drum shape or a belt shape.
【0013】また上記第1の透明導電膜2および第2の
透明導電膜3を構成する材料には、ITOを始めとして
SnO2 、In2 O3 、酸化鉛(ZnO)、ヨウ化銅
(CuI)、硫化銅(CuS)、InOF、Cd2 Sn
O4 等が使用可能である。そして、これら透明導電膜を
形成するための薄膜形成手段には、イオンプレーティン
グ法や活性反応蒸着法、真空蒸着法、RFスパッタリン
グ法、DCスパッタリング法RFマグネトロンスパッタ
リング法、DCマグネトロンスパッタリング法、熱CV
D法、プラズマCVD法、触媒CVD法、スプレー法、
塗布法、浸漬法等がある。The materials for the first transparent conductive film 2 and the second transparent conductive film 3 include ITO, SnO 2 , In 2 O 3 , lead oxide (ZnO), and copper iodide (CuI). ), Copper sulfide (CuS), InOF, Cd 2 Sn
O 4 etc. can be used. The thin film forming means for forming these transparent conductive films include ion plating method, active reaction vapor deposition method, vacuum vapor deposition method, RF sputtering method, DC sputtering method, RF magnetron sputtering method, DC magnetron sputtering method, and thermal CV.
D method, plasma CVD method, catalytic CVD method, spray method,
There are a coating method and a dipping method.
【0014】ここで、透明基体1上にまず第1のITO
透明導電膜2を形成するに当たってその形成条件を制御
し、例えば遅い成膜速度でITO膜を成膜するなどし
て、透明導電膜2中のITO結晶の配向性をある特定の
方向に強くなるようにして作製すると、その特定方向の
配向を持ったITO結晶の平均粒径が大きくなり、IT
O膜の表面に凹凸ができる。このようにしてITO透明
導電膜2の表面に凹凸を設けることにより、透明導電膜
上に別種半導体膜を形成した場合の別種半導体膜内およ
び別種半導体膜と透明導電膜との間の応力を緩和できる
ため、透明導電膜の剥離を抑制することができる。Here, the first ITO is first formed on the transparent substrate 1.
When the transparent conductive film 2 is formed, its forming conditions are controlled, and for example, the ITO film is formed at a slow film forming speed to strengthen the orientation of the ITO crystals in the transparent conductive film 2 in a specific direction. When manufactured in this manner, the average grain size of the ITO crystals having the orientation in the specific direction increases, and
Irregularities are formed on the surface of the O film. By providing irregularities on the surface of the ITO transparent conductive film 2 in this manner, stress in the different semiconductor film and between the different semiconductor film and the transparent conductive film when the different semiconductor film is formed on the transparent conductive film is relaxed. Therefore, peeling of the transparent conductive film can be suppressed.
【0015】本発明者の得た知見によれば、このように
剥離を抑制するために第1の透明導電膜2表面に設ける
凹凸の大きさは、該膜中のITOの平均結晶粒径により
表わしたときに、0.025μm以上とすることで良好
な結果が得られた。According to the knowledge obtained by the present inventor, the size of the unevenness provided on the surface of the first transparent conductive film 2 in order to suppress the peeling depends on the average crystal grain size of ITO in the film. When expressed, good results were obtained by setting the thickness to 0.025 μm or more.
【0016】次いで、上記第1の透明導電膜2上に第2
の透明導電膜3を形成する。この第2の透明導電膜3を
形成するに当たっては、その形成条件を制御し、例えば
第1の透明導電膜2より速い成膜速度で成膜するなどし
て作製すると、ITOの平均結晶粒径が小さく従って表
面の凹凸の小さい透明導電膜が形成される。しかし、こ
の第2の透明導電膜3を積層した後の透明導電膜の表面
の凹凸は、第1の透明導電膜2の凹凸の大きさが反映さ
れて凹凸の大きな状態が維持されるため、上記の剥離抑
制の効果は保たれる。一方、第2の透明導電膜3自身の
凹凸および平均結晶粒径は小さくなっているため、これ
により耐環境性が優れて特性の安定性が向上したITO
透明導電膜となる。Then, a second film is formed on the first transparent conductive film 2.
Transparent conductive film 3 is formed. When the second transparent conductive film 3 is formed, if the conditions for forming the second transparent conductive film 3 are controlled and the second transparent conductive film 3 is formed at a higher film forming speed than that of the first transparent conductive film 2, the average crystal grain size of ITO is increased. Therefore, a transparent conductive film having a small surface roughness is formed. However, since the unevenness of the surface of the transparent conductive film after the second transparent conductive film 3 is laminated reflects the size of the unevenness of the first transparent conductive film 2, the large unevenness is maintained, The effect of suppressing peeling is maintained. On the other hand, since the irregularities and the average crystal grain size of the second transparent conductive film 3 itself are small, the ITO having the excellent environmental resistance and the improved stability of the characteristics is thereby obtained.
It becomes a transparent conductive film.
【0017】本発明者の得た知見によれば、このように
剥離抑制の効果を維持しつつ耐環境性を高めて特性の安
定性を向上するために設ける第2の透明導電膜3表面の
凹凸の大きさは、該膜中のITOの平均結晶粒径により
表わしたときに、0.025μm未満とすることで良好
な結果が得られた。According to the knowledge obtained by the inventor of the present invention, the surface of the second transparent conductive film 3 provided in order to improve the environment resistance and the stability of the characteristics while maintaining the effect of suppressing the peeling. Good results were obtained by setting the size of the irregularities to less than 0.025 μm when expressed by the average crystal grain size of ITO in the film.
【0018】このように平均結晶粒径を0.025μm
以上とすることにより特性の安定性が向上するが、その
際の結晶粒径のばらつきの下限としては、粒径が小さ過
ぎると表面の凹凸の形成が不十分となって応力を吸収し
きれずに剥離が発生することから、0.012μm以上
であることが望ましい。一方、結晶粒径の上限として
は、この結晶粒径が大きくなると導電率が低くなってし
まい、また環境の変化に対する特性の変動が大きくなる
といった理由により、0.05μm以下であることが好
ましい。Thus, the average crystal grain size is 0.025 μm.
By the above, the stability of the characteristics is improved, but as the lower limit of the variation of the crystal grain size at that time, if the grain size is too small, the formation of surface irregularities becomes insufficient and the stress cannot be completely absorbed. Since peeling occurs, 0.012 μm or more is desirable. On the other hand, the upper limit of the crystal grain size is preferably 0.05 μm or less because the electrical conductivity decreases as the crystal grain size increases, and the fluctuation of the characteristics with respect to environmental changes increases.
【0019】また、第1の透明導電膜の厚みは、250
Å以上、より好適には250〜2000Åの範囲とする
ことが望ましい。この範囲内であれば、ITOの結晶粒
径が透明導電膜と半導体膜との間の応力を緩和するのに
必要な0.025μm以上に成長させて、最も優位に密
着性を向上させることができる。但し、2000Åを大
きく越える場合は、温度や湿度などの環境による抵抗率
あるいは光透過率の変化が大きくなることがあり、この
膜および第2の透明導電膜を積層した透明導電膜全体と
しての耐環境性が十分に高められないことがあるが、こ
の上限は臨界的なものではなく、所望の特性との兼ね合
いで適宜設定される。第2の透明導電膜の厚みは、50
0Å、より好適には500〜2000Åの範囲とするこ
とが望ましい。この範囲内であれば、抵抗率が低くなっ
て良好な導電性が得られ易い。2000Åを大きく越え
る場合は、透明導電膜全体の膜厚が増えて光透過率が低
下する傾向にあるが、この上限も臨界的なものではな
く、所望の特性との兼ね合いで適宜設定される。The thickness of the first transparent conductive film is 250.
Å or more, and more preferably 250 to 2000Å. Within this range, the crystal grain size of ITO can be grown to 0.025 μm or more, which is necessary to relieve the stress between the transparent conductive film and the semiconductor film, and the adhesion can be most significantly improved. it can. However, if it exceeds 2000 Å, the resistance or the light transmittance may change greatly due to the environment such as temperature and humidity, and the resistance of the entire transparent conductive film in which this film and the second transparent conductive film are laminated is increased. Although environmental properties may not be sufficiently enhanced, this upper limit is not critical and is appropriately set in consideration of desired properties. The thickness of the second transparent conductive film is 50.
It is desirable to set it in the range of 0Å, more preferably in the range of 500 to 2000Å. Within this range, the resistivity becomes low and good conductivity is easily obtained. If it exceeds 2000 Å, the film thickness of the entire transparent conductive film tends to increase and the light transmittance tends to decrease. However, this upper limit is not critical and is appropriately set in consideration of desired characteristics.
【0020】上記のような平均結晶粒径の異なる2種類
の膜の組合せによる応力緩和と耐環境性向上の作用は、
ITO透明導電膜の場合に限らず、SnO2 やIn2 O
3 等の他の透明導電膜やその他の多結晶膜に別種半導体
膜を積層する場合にも、同様に応用できるものと考えら
れる。The action of stress relaxation and environmental resistance improvement by the combination of the two kinds of films having different average crystal grain sizes as described above is as follows.
Not limited to the case of ITO transparent conductive film, SnO 2 or In 2 O
It is considered that the invention can be similarly applied to the case where another kind of semiconductor film is laminated on another transparent conductive film such as 3 or other polycrystalline film.
【0021】そして、本発明の構成の半導体素子の応用
としては、例えば電子写真感光体および太陽電池、TF
T(薄膜トランジスタ)、光センサー、読み取りセンサ
ー、フォトダイオード等の各種薄膜デバイスがある。The application of the semiconductor device having the structure of the present invention is, for example, an electrophotographic photosensitive member, a solar cell, or TF.
There are various thin film devices such as T (thin film transistor), optical sensor, reading sensor, and photodiode.
【0022】[0022]
【実施例】以下、実施例を具体的に示す。 〔例1〕図2に、本発明のITO透明導電膜の成膜に用
いたイオンプレーティング装置5の概略構成図を示す。
イオンプレーティング装置5は、本体6aとその底体6
bとからなる真空容器6の中に、成膜用イオン供給源と
しての蒸発源7と反応性プラズマ生成用の高周波コイル
8、陰極ベースを兼ねた基体支持体9、ハロゲンヒータ
ー等からなる基体加熱用ヒーター10、成膜の開始と終
了を制御するためのシャッター11とが配置されてお
り、蒸発源7には蒸発源電源12が、高周波コイル8に
は高周波電源13が、基体支持体9には直流電源14が
それぞれ接続されている。また真空容器の本体6aに
は、バルブ15とガス流量調整器16を介した反応ガス
導入口17と、イオンポンプや油拡散ポンプなどの真空
排気手段(図示せず)に接続されたガス排気口18とが
配設されている。図中の矢印は、ガスの流れを表わす。EXAMPLES Examples will be specifically described below. Example 1 FIG. 2 shows a schematic configuration diagram of an ion plating device 5 used for forming the ITO transparent conductive film of the present invention.
The ion plating device 5 includes a main body 6a and a bottom body 6 thereof.
In a vacuum container 6 consisting of b, an evaporation source 7 as an ion supply source for film formation, a high-frequency coil 8 for generating a reactive plasma, a substrate support 9 also serving as a cathode base, and a substrate heating comprising a halogen heater or the like. A heater 10 for heating and a shutter 11 for controlling the start and end of film formation are arranged. An evaporation source power source 12 is provided for the evaporation source 7, a high frequency power source 13 is provided for the high frequency coil 8, and a substrate support 9 is provided. Are connected to DC power supplies 14, respectively. Further, in the main body 6a of the vacuum container, a reaction gas introduction port 17 via a valve 15 and a gas flow rate regulator 16 and a gas exhaust port connected to a vacuum exhaust unit (not shown) such as an ion pump or an oil diffusion pump. And 18 are provided. The arrows in the figure represent the flow of gas.
【0023】このイオンプレーティング装置5によりI
TO成膜を行なうには、まず基体支持体9に被成膜用透
明基体19を装着して、真空容器6内を真空排気手段に
より10-6Torr程度の真空度まで排気すると共に、ヒー
ター10によって基体19を所定の成膜温度まで加熱す
る。次いで、バルブ15を開け、アルゴン(Ar)と酸
素(O2 )の混合ガス等からなる反応ガスを、流量調整
器16により所定の流量に設定してガス導入口17より
容器6内に導入し、容器6内を所定圧力に設定する。次
に、蒸発源電源12をONにして蒸発源7にエレクトロ
ンビーム電流を流して電力を印加し、蒸発源7からイン
ジウム(In)とスズ(Sn)の酸化物などからなる成
膜用材料を蒸発させると共に、高周波電源13よりコイ
ル8に高周波を印加して反応性プラズマを生成し、また
直流電源14により基体支持体9に負電圧を印加して、
成膜条件を調整し安定化させる。その後、シャッター1
1を開けることにより蒸発源7からの成膜用材料が反応
性プラズマを通過して基体19へ到達し、ITO膜が成
膜される。そして、所望の膜厚が得られたら再びシャッ
ター11を閉じて成膜を終了する。With this ion plating device 5, I
In order to perform TO film formation, first, the film formation transparent substrate 19 is mounted on the substrate support 9, the inside of the vacuum container 6 is evacuated to a vacuum degree of about 10 −6 Torr, and the heater 10 is used. The base 19 is heated to a predetermined film forming temperature by. Next, the valve 15 is opened, and a reaction gas composed of a mixed gas of argon (Ar) and oxygen (O 2 ) or the like is set to a predetermined flow rate by the flow rate controller 16 and introduced into the container 6 through the gas introduction port 17. , The inside of the container 6 is set to a predetermined pressure. Next, the evaporation source power supply 12 is turned on, an electron beam current is passed through the evaporation source 7 to apply power, and a film forming material composed of an oxide of indium (In) and tin (Sn) is applied from the evaporation source 7. While evaporating, a high frequency power is applied to the coil 8 from the high frequency power supply 13 to generate reactive plasma, and a negative voltage is applied to the substrate support 9 by the DC power supply 14,
Adjust film formation conditions to stabilize. After that, shutter 1
By opening 1, the film forming material from the evaporation source 7 passes through the reactive plasma and reaches the substrate 19 to form an ITO film. Then, when the desired film thickness is obtained, the shutter 11 is closed again to complete the film formation.
【0024】上記のイオンプレーティング装置5を用い
て、透明基体として外径30mm、長さ260mmのパ
イレックスガラス管を使用し、表1の条件により、平均
結晶粒径の異なる第1および第2のITO透明導電膜を
成膜した。平均結晶粒径は成膜速度を変えることにより
変化させ、成膜速度の制御は、蒸発源に印加する電力を
エレクトロンビーム電流の大きさにより調整して、蒸発
量を変えることで行なった。この蒸発量の確認は、蒸発
源を蒸発させる前後の真空容器6内の圧力上昇値を真空
計でモニターすることで行なった。Using the ion plating device 5 described above, a Pyrex glass tube having an outer diameter of 30 mm and a length of 260 mm was used as a transparent substrate, and the first and second Pyrex glass tubes having different average crystal grain sizes were used under the conditions shown in Table 1. An ITO transparent conductive film was formed. The average crystal grain size was changed by changing the film formation rate, and the film formation rate was controlled by adjusting the electric power applied to the evaporation source according to the magnitude of the electron beam current and changing the evaporation amount. The amount of evaporation was confirmed by monitoring the pressure rise value in the vacuum container 6 before and after the evaporation source was evaporated with a vacuum gauge.
【0025】[0025]
【表1】 [Table 1]
【0026】これら第1および第2のITO透明導電膜
の平均結晶粒径は、膜表面のSEM(走査型電子顕微
鏡)写真により求めた。これらのSEM写真は、日立製
S800走査型電子顕微鏡を使用し、試料表面にPt−Pd
蒸着を行なって、チルト角度0度で5万倍の倍率で撮影
した。このようにして撮影した各々のSEM写真に長さ
50mmの線を10本引き、各線にかかる結晶粒子の個
数を数えて50mm当たりの結晶粒子の平均個数を求
め、その平均個数より平均結晶粒径を計算して求めた。
表1には、これら平均結晶粒径の計算結果も示した。上
記のようにして、第1および第2の透明導電膜の平均結
晶粒径を求めたところ、エレクトロンビーム電流を3.
0A(アンペア)と小さくして成膜速度を遅くした第1
の透明導電膜では、結晶粒子の平均個数が33.2個で
あり、平均結晶粒径は(50mm/33.2)÷50,
000=3.010×10-5mmすなわち0.030μ
mと大きくなっており、他方、エレクトロンビーム電流
を6.0Aと大きくして成膜速度を速くした第2の透明
導電膜では、結晶粒子の平均個数が49.3個であり、
平均結晶粒径は(50mm/49.3)÷50,000
=2.028×10-5mmすなわち0.020μmと小
さくなっていた。従って、各試料の平均結晶粒径は、エ
レクトロンビーム電流の大きさにより蒸発量を変えて成
膜速度を変えることにより、変化していることが確認で
きた。また、それにより膜表面に形成される凹凸の大き
さを制御できることが確認できた。The average crystal grain size of these first and second ITO transparent conductive films was determined by SEM (scanning electron microscope) photographs of the film surface. These SEM photographs were taken using a Hitachi S800 scanning electron microscope, and Pt-Pd on the sample surface.
After vapor deposition, an image was taken at a tilt angle of 0 degree and a magnification of 50,000 times. In each SEM photograph thus taken, 10 lines with a length of 50 mm were drawn, the number of crystal grains per line was counted, the average number of crystal grains per 50 mm was calculated, and the average crystal grain size was calculated from the average number. Was calculated and calculated.
Table 1 also shows the calculation results of these average crystal grain sizes. When the average crystal grain size of the first and second transparent conductive films was determined as described above, the electron beam current was 3.
First to reduce the film formation rate by reducing it to 0 A (ampere)
In the transparent conductive film of, the average number of crystal grains is 33.2, and the average crystal grain size is (50 mm / 33.2) ÷ 50,
000 = 3.010 × 10 -5 mm or 0.030μ
On the other hand, in the second transparent conductive film in which the electron beam current was increased to 6.0 A and the film formation rate was increased, the average number of crystal grains was 49.3.
The average crystal grain size is (50 mm / 49.3) ÷ 50,000
= 2.028 × 10 −5 mm, that is, 0.020 μm. Therefore, it was confirmed that the average crystal grain size of each sample was changed by changing the evaporation rate according to the magnitude of the electron beam current and changing the film formation rate. It was also confirmed that the size of the irregularities formed on the film surface could be controlled thereby.
【0027】次いで、上記のようにして形成した2層構
成のITO透明導電膜の上に、プラズマCVD法により
a−Si膜を積層した。本実施例に使用したa−Si膜
を形成するためのプラズマCVD成膜反応炉を、図3に
基づいて説明する。図3は、プラズマCVD成膜反応炉
20の概略構成図である。図3に示したプラズマCVD
成膜反応炉20において、21は円筒状の金属製反応
炉、22はITO膜が形成されたガラス管基体19を装
着する筒状の導電性支持体であり、基体19は、ITO
膜と支持体22との導通を取り、かつ基体19の端部に
非成膜部を設けるためのマスク23と、ダミーリング2
4とによって、支持体22に保持されている。25は基
体加熱用ヒーター、26はa−Siの成膜に用いられる
筒状のグロー放電用電極板であり、この電極板26には
多数のガス噴出口27が形成されている。そして、28
は反応炉内部へガスを導入するためのガス導入口、29
はグロー放電に晒されたガスの残余ガスを排気するため
のガス排出口であり、30は導電性支持体22とグロー
放電用電極板26の間でグロー放電を発生させるための
高周波電源である。ここで図中の矢印は、ガスの流れを
表わす。また、この反応炉20は円筒体21aと蓋体2
1bと底体21cとからなり、そして、円筒体21aと
蓋体21bとの間、並びに円筒体21aと底体21cと
の間には、それぞれ絶縁性のリング21dを設けてお
り、これによって高周波電源30の一方の端子は円筒体
21aを介してグロー放電用電極板26と導通してお
り、他方の端子は蓋体21bや底体21cを介して導電
性支持体22と導通し、接地されている。また、蓋体2
1bの上に付設したモーター31により回転軸32を介
して導電性支持体22が回転駆動され、これに伴って基
体19も回転する。Next, an a-Si film was laminated by the plasma CVD method on the two-layered ITO transparent conductive film formed as described above. The plasma CVD film forming reaction furnace for forming the a-Si film used in this embodiment will be described with reference to FIG. FIG. 3 is a schematic configuration diagram of the plasma CVD film forming reaction furnace 20. Plasma CVD shown in FIG.
In the film forming reaction furnace 20, 21 is a cylindrical metal reaction furnace, 22 is a cylindrical conductive support on which a glass tube substrate 19 having an ITO film is mounted, and the substrate 19 is ITO.
A mask 23 for establishing electrical continuity between the film and the support 22 and providing a non-film-forming portion at the end of the base body 19, and the dummy ring 2
It is held by the support 22 by means of 4. Reference numeral 25 is a heater for heating the substrate, 26 is a cylindrical glow discharge electrode plate used for film formation of a-Si, and a large number of gas ejection ports 27 are formed in this electrode plate 26. And 28
Is a gas inlet for introducing gas into the reactor, 29
Is a gas outlet for exhausting the residual gas of the gas exposed to the glow discharge, and 30 is a high frequency power source for generating glow discharge between the conductive support 22 and the glow discharge electrode plate 26. . Here, the arrows in the figure represent the flow of gas. Further, the reaction furnace 20 includes a cylindrical body 21a and a lid body 2.
1b and a bottom body 21c, and an insulating ring 21d is provided between the cylinder body 21a and the lid body 21b, and between the cylinder body 21a and the bottom body 21c, respectively. One terminal of the power supply 30 is electrically connected to the glow discharge electrode plate 26 through the cylindrical body 21a, and the other terminal is electrically connected to the conductive support 22 through the lid 21b and the bottom body 21c and is grounded. ing. Also, the lid 2
The conductive support 22 is rotatably driven by the motor 31 attached above 1b via the rotary shaft 32, and the base 19 is also rotated accordingly.
【0028】このプラズマCVD成膜反応炉20を用い
てa−Si膜を成膜する場合には、基体19を支持体2
2に装着し、a−Si生成用の原料ガスとしてのシラン
ガスやジシランガス、あるいはa−Siの特性調整用に
添加される不純物ガスとしてのジボランガスやホスフィ
ンガス、メタンガス、アセチレンガス、アンモニアガ
ス、窒素ガス、更に希釈用ガスとして用いられる水素ガ
スやヘリウムガス、アルゴンガス等を所定の組成比で混
合したガスを、ガス導入口28より反応炉内部へ導入
し、このガスをガス噴出口27を介して基体19表面へ
向けて噴出し、更にヒーター25によって基体19を所
要の温度に設定すると共に、高周波電源30より高周波
電力を供給して支持体22と電極板26との間でグロー
放電を発生させ、更に基体19を回転させることによっ
て基体19の周面にa−Si膜を成膜する。このように
してa−Si膜を成膜するグロ−放電プラズマ中には、
a−Si生成用ガス中に含まれている水素が、還元性活
性種である水素ラジカルとして存在している。When an a-Si film is formed using this plasma CVD film forming reaction furnace 20, the substrate 19 is used as the support 2.
The silane gas or disilane gas as a raw material gas for generating a-Si, or the diborane gas or phosphine gas or phosphine gas as an impurity gas added to adjust the characteristics of a-Si, methane gas, acetylene gas, ammonia gas, nitrogen gas. Further, a gas obtained by mixing hydrogen gas, helium gas, argon gas, etc. used as a diluting gas at a predetermined composition ratio is introduced into the reaction furnace through the gas inlet port 28, and this gas is introduced through the gas jet port 27. The base material 19 is jetted toward the surface of the base material 19, the base material 19 is set to a required temperature by the heater 25, and high frequency power is supplied from the high frequency power supply 30 to generate glow discharge between the support body 22 and the electrode plate 26. Then, the base 19 is further rotated to form an a-Si film on the peripheral surface of the base 19. Thus, during the glow discharge plasma for forming the a-Si film,
Hydrogen contained in the a-Si generating gas exists as hydrogen radicals that are reducing active species.
【0029】表1に示した2層構成のITO透明導電膜
を形成したガラス管基体に、上記のプラズマCVD成膜
反応炉20を用いて、表2の条件でa−Si膜を積層
し、本発明の構成の半導体素子を作製した。On the glass tube substrate on which the two-layered ITO transparent conductive film shown in Table 1 was formed, the a-Si film was laminated under the conditions shown in Table 2 using the plasma CVD film forming reaction furnace 20. A semiconductor device having the constitution of the present invention was produced.
【0030】[0030]
【表2】 [Table 2]
【0031】そして、上記のようにして得られた2層構
成のITO透明導電膜および半導体素子に対して、耐環
境性試験を行なった。耐環境性試験としては、透明導電
膜に対しては耐熱性、耐アルカリ性、耐湿性および耐水
素プロセス性の各試験を行ない、半導体素子に対しては
密着性試験を行なった。合否判定のための特性測定は、
透明導電膜に対して、シート抵抗と波長550〜790
nmにおける光透過率とについて行ない、試験前後での
それらの変化率を求めて判定した。また、半導体素子に
対する密着性は、目視で判定した。表3に、これらの試
験条件および優良品判定基準を示す。Then, an environment resistance test was conducted on the two-layered ITO transparent conductive film and the semiconductor element obtained as described above. As the environment resistance test, heat resistance, alkali resistance, humidity resistance and hydrogen process resistance tests were conducted on the transparent conductive film, and an adhesion test was conducted on the semiconductor element. The characteristic measurement for pass / fail judgment is
Sheet resistance and wavelength of 550 to 790 for transparent conductive film
The light transmittance in nm and the change rate before and after the test were calculated and judged. Further, the adhesion to the semiconductor element was visually determined. Table 3 shows these test conditions and the criteria for determining excellent products.
【0032】[0032]
【表3】 [Table 3]
【0033】これらの耐環境性試験の結果、透明導電膜
については、耐熱性におけるシート抵抗の変化率が5%
以内、耐アルカリ性におけるシート抵抗の変化率(以
下、抵抗変化率と略す)が1.5%、耐湿性における抵
抗変化率が2%、耐水素プラズマ性における抵抗変化率
が1%および光透過率が90%で光透過率の変化率も4
%であり、また半導体素子については密着性試験で膜剥
がれが認められず、それぞれ優れた耐環境性を示した。As a result of these environment resistance tests, the transparent conductive film showed a change rate of sheet resistance of 5% in heat resistance.
Within, the rate of change in sheet resistance in alkali resistance (hereinafter abbreviated as resistance change rate) is 1.5%, the rate of resistance change in humidity resistance is 2%, the rate of resistance change in hydrogen plasma resistance is 1%, and the light transmittance. Is 90% and the change rate of light transmittance is 4
%, And no peeling of the film was observed in the adhesion test of the semiconductor element, and each showed excellent environment resistance.
【0034】〔例2〕〔例1〕と同様にして、外径30
mm、長さ260mmのガラス管基体に平均結晶粒径お
よび厚みを変えた成膜速度を変えた第1および第2のI
TO透明導電膜を幾通りが形成し、その上にプラズマC
VD法によりa−Si膜を積層して、半導体素子A〜W
を作製した。また、比較例として、第2の透明導電膜を
形成せずにa−Si膜を積層した半導体素子X〜Zも作
製した。[Example 2] In the same manner as in [Example 1], an outer diameter of 30
mm and length 260 mm, the first and second I are obtained by changing the average crystal grain size and thickness and changing the film formation rate.
Several kinds of TO transparent conductive films are formed and plasma C is formed on them.
The semiconductor elements A to W are formed by stacking a-Si films by the VD method.
Was produced. Further, as comparative examples, semiconductor elements X to Z in which a-Si films were laminated without forming the second transparent conductive film were also manufactured.
【0035】これらの試料の透明導電膜の平均結晶粒径
および厚みと、各試料に対して〔例1〕と同様に行なっ
た耐環境性試験の結果を、表4および表5にまとめた。
両表中の耐環境性試験の結果には、透明導電膜に対する
耐熱性、耐アルカリ性、耐湿性および耐水素プロセス性
の各試験での抵抗または光透過率の変化率、および耐水
素プラズマ性試験での光透過率と、半導体素子に対する
密着性試験での膜剥がれの発生率を示し、併せてそれら
の判定結果として、上記の優良品レベルには○を、それ
よりはやや劣るものの実用上差し支えない良品レベルに
は△を、実用上問題となるレベルには×をそれぞれ表示
した。また、本発明の範囲外のものには、試料番号欄に
*を併記した。Tables 4 and 5 summarize the average crystal grain size and thickness of the transparent conductive films of these samples, and the results of the environmental resistance test conducted on each sample in the same manner as in [Example 1].
The results of the environmental resistance test in both tables include the change rate of resistance or light transmittance in each test of heat resistance, alkali resistance, moisture resistance and hydrogen process resistance for the transparent conductive film, and hydrogen plasma resistance test. Shows the light transmittance of the film and the rate of occurrence of film peeling in the adhesion test for semiconductor elements, and as a result of these judgments, the above-mentioned excellent product level is indicated by ○, and although slightly lower than that, it is a practical problem. △ is shown for a non-defective product level, and × is shown for a practically problematic level. In addition, * was additionally written in the sample number column for those outside the scope of the present invention.
【0036】[0036]
【表4】 [Table 4]
【0037】[0037]
【表5】 [Table 5]
【0038】これらの耐環境性試験の結果、本発明の半
導体素子EおよびJ〜Wは、透明導電膜における耐熱性
および耐アルカリ性、耐湿性に対するシート抵抗または
光透過率の変化率、並びに耐水素プラズマ性に対する抵
抗変化率および光透過率の変化率のいずれも良好であ
り、また半導体素子における密着性でも膜剥がれが認め
られず、それぞれ優れた耐環境性を示した。As a result of these environmental resistance tests, the semiconductor elements E and J to W of the present invention were found to have heat resistance and alkali resistance in the transparent conductive film, a change rate of sheet resistance or light transmittance with respect to moisture resistance, and hydrogen resistance. Both the rate of change in resistance with respect to the plasma property and the rate of change in light transmittance were good, and no film peeling was observed in the adhesiveness in the semiconductor element, and each showed excellent environment resistance.
【0039】[0039]
【発明の効果】以上詳述したように、本発明により、I
TO透明導電膜の成膜条件、特に成膜速度を制御して平
均粒径および膜表面の凹凸などを制御するという簡便な
方法で、技術的な困難さや膜形成に係るコストの増加を
もたらすことなく、透明導電膜表面の荒れや変色による
透明性の低下を抑制した半導体素子を提供することがで
きた。As described above in detail, according to the present invention, I
A simple method of controlling the average particle size and the unevenness of the film surface by controlling the film forming conditions of the TO transparent conductive film, particularly the film forming speed, which brings about technical difficulties and an increase in the film forming cost. In addition, it was possible to provide a semiconductor element in which the deterioration of the transparency due to the roughness or discoloration of the surface of the transparent conductive film was suppressed.
【0040】また本発明により、透明導電膜上に半導体
膜を積層した後の透明導電膜および半導体膜の剥離の発
生を抑制し、密着性を高めた半導体素子を提供すること
ができた。Further, according to the present invention, it is possible to provide a semiconductor element in which the occurrence of peeling of the transparent conductive film and the semiconductor film after the semiconductor film is laminated on the transparent conductive film is suppressed and the adhesion is improved.
【0041】さらに本発明によれば、耐環境性を向上し
た透明導電膜およびその上に半導体膜を形成した半導体
素子を提供することができ、電子写真感光体や読み取り
センサーを始めとする各種薄膜デバイスへの応用が可能
となった。Further, according to the present invention, it is possible to provide a transparent conductive film having improved environmental resistance and a semiconductor element having a semiconductor film formed thereon, and various thin films such as electrophotographic photoreceptors and reading sensors. Now it can be applied to devices.
【0042】そして、半導体素子作製中の膜剥離がなく
なることから成膜欠陥が減少し、それにより素子の良品
率が向上して高い品質を確保することができると共に、
素子の特性が安定し、薄膜デバイス製品としての優れた
安定性を確保することができた。Since film peeling during the manufacture of semiconductor elements is eliminated, film formation defects are reduced, which improves the yield rate of elements and ensures high quality.
The element characteristics were stable, and it was possible to secure excellent stability as a thin film device product.
【図1】本発明の製法により作製された半導体素子の層
構成を示す断面図である。FIG. 1 is a cross-sectional view showing a layer structure of a semiconductor element manufactured by a manufacturing method of the present invention.
【図2】本実施例に使用したイオンプレーティング装置
の概略構成図である。FIG. 2 is a schematic configuration diagram of an ion plating apparatus used in this example.
【図3】本実施例に使用したプラズマCVD成膜反応炉
の概略構成図である。FIG. 3 is a schematic configuration diagram of a plasma CVD film forming reaction furnace used in this example.
1、19・・・透明基体 2・・・・・・第1の透明導電膜 3・・・・・・第2の透明導電膜 4・・・・・・半導体膜 5・・・・・・イオンプレーティング装置 7・・・・・・蒸発源 8・・・・・・高周波コイル 13、30・・高周波電源 20・・・・・プラズマCVD成膜反応炉 26・・・・・グロー放電用電極板 1, 19 ... Transparent substrate 2 ... First transparent conductive film 3 ... Second transparent conductive film 4 ... Semiconductor film 5 ... Ion plating device 7 ... Evaporation source 8 ... High-frequency coil 13, 30 ... High-frequency power source 20 ... Plasma CVD film forming reactor 26 ... For glow discharge Electrode plate
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 G02F 1/1343 H01L 29/786 21/336 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location G02F 1/1343 H01L 29/786 21/336
Claims (1)
晶粒径が0.025μm以上であるITO結晶を有する
第1の透明導電膜と平均結晶粒径が0.025μm未満
であるITO結晶を有する第2の透明導電膜を順次形成
するとともに、該第2の透明導電膜上に還元性活性種を
含むプラズマにより半導体膜を形成することを特徴とす
る半導体素子の製法。1. A first transparent conductive film having an ITO crystal having an average crystal grain size of 0.025 μm or more and a ITO crystal having an average crystal grain size of less than 0.025 μm on a transparent substrate by a thin film forming means. A method of manufacturing a semiconductor device, comprising: forming a second transparent conductive film sequentially and forming a semiconductor film on the second transparent conductive film by plasma containing reducing active species.
Priority Applications (1)
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JP05244398A JP3101962B2 (en) | 1993-09-30 | 1993-09-30 | Semiconductor element manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05244398A JP3101962B2 (en) | 1993-09-30 | 1993-09-30 | Semiconductor element manufacturing method |
Publications (2)
Publication Number | Publication Date |
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JPH07106614A true JPH07106614A (en) | 1995-04-21 |
JP3101962B2 JP3101962B2 (en) | 2000-10-23 |
Family
ID=17118082
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JP05244398A Expired - Fee Related JP3101962B2 (en) | 1993-09-30 | 1993-09-30 | Semiconductor element manufacturing method |
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JP (1) | JP3101962B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006162686A (en) * | 2004-12-02 | 2006-06-22 | Ricoh Co Ltd | Optical deflecting element, optical deflector provided with the element, and picture display device |
EP1351317A3 (en) * | 2002-03-19 | 2010-12-15 | Sanyo Electric Co., Ltd. | Photovoltaic element and manufacturing method of the photovoltaic element |
JP2013012593A (en) * | 2011-06-29 | 2013-01-17 | Kaneka Corp | Thin film photoelectric conversion device |
WO2013073211A1 (en) * | 2011-11-18 | 2013-05-23 | 三洋電機株式会社 | Solar cell and production method for solar cell |
US9581875B2 (en) | 2005-02-23 | 2017-02-28 | Sage Electrochromics, Inc. | Electrochromic devices and methods |
-
1993
- 1993-09-30 JP JP05244398A patent/JP3101962B2/en not_active Expired - Fee Related
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1351317A3 (en) * | 2002-03-19 | 2010-12-15 | Sanyo Electric Co., Ltd. | Photovoltaic element and manufacturing method of the photovoltaic element |
JP2006162686A (en) * | 2004-12-02 | 2006-06-22 | Ricoh Co Ltd | Optical deflecting element, optical deflector provided with the element, and picture display device |
US9581875B2 (en) | 2005-02-23 | 2017-02-28 | Sage Electrochromics, Inc. | Electrochromic devices and methods |
US10061174B2 (en) | 2005-02-23 | 2018-08-28 | Sage Electrochromics, Inc. | Electrochromic devices and methods |
US11567383B2 (en) | 2005-02-23 | 2023-01-31 | Sage Electrochromics, Inc. | Electrochromic devices and methods |
JP2013012593A (en) * | 2011-06-29 | 2013-01-17 | Kaneka Corp | Thin film photoelectric conversion device |
WO2013073211A1 (en) * | 2011-11-18 | 2013-05-23 | 三洋電機株式会社 | Solar cell and production method for solar cell |
JPWO2013073211A1 (en) * | 2011-11-18 | 2015-04-02 | 三洋電機株式会社 | Solar cell and method for manufacturing solar cell |
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JP3101962B2 (en) | 2000-10-23 |
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