JPH07101717B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH07101717B2 JPH07101717B2 JP62075314A JP7531487A JPH07101717B2 JP H07101717 B2 JPH07101717 B2 JP H07101717B2 JP 62075314 A JP62075314 A JP 62075314A JP 7531487 A JP7531487 A JP 7531487A JP H07101717 B2 JPH07101717 B2 JP H07101717B2
- Authority
- JP
- Japan
- Prior art keywords
- forming
- type
- bipolar transistor
- well
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にCMOS型電界
効果トランジスタとバイポーラトランジスタを同一基板
上に有する半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a CMOS field effect transistor and a bipolar transistor on the same substrate.
バイポーラトランジスタとCMOS型電界効果トランジスタ
（以下CMOSトランジスタと記す）を同一基板に形成した
集積回路（以下Bi−CMOS ICと記す）は、CMOSトランジ
スタの低消費電力動作とバイポーラトランジスタの高速
動作，高駆動能力を同時に実現出来ることから、近年多
くその製造が報告されている。An integrated circuit (hereinafter referred to as Bi-CMOS IC) in which a bipolar transistor and a CMOS type field effect transistor (hereinafter referred to as CMOS transistor) are formed on the same substrate is a low power consumption operation of the CMOS transistor and high speed operation and high driving of the bipolar transistor. Since the capability can be realized at the same time, many productions have been reported in recent years.
以下、第３図を用いて従来のBi−CMOSICの製造方法につ
いて説明する。Hereinafter, a conventional method for manufacturing a Bi-CMOS IC will be described with reference to FIG.
まず、Ｐ型基板１にN+型埋込層２を形成し、その上にＰ
型エピタキシャル層３を成長させ、ＰチャネルMOSトラ
ンジスタ形成領域とバイポーラトランジスタ形成領域に
Ｎウェル4A,4Bをそれぞれ形成する。次に、素子分離酸
化膜5,ゲート酸化膜10を形成後、バイポーラトランジス
タのベース領域8,多結晶シリコンからなるゲート電極６
を形成する。First, the N + type buried layer 2 is formed on the P type substrate 1, and P is formed thereon.
The type epitaxial layer 3 is grown to form N wells 4A and 4B in the P channel MOS transistor forming region and the bipolar transistor forming region, respectively. Next, after forming the element isolation oxide film 5 and the gate oxide film 10, the base region 8 of the bipolar transistor and the gate electrode 6 made of polycrystalline silicon.
To form.
以下、バイポーラトランジスタのエミッタ及びＮチャネ
ルMOSトランジスタのソース・ドレイン領域を形成し、
次にＰチャネルMOSトランジスタのソース・ドレイン領
域を形成してBi−CMOS ICを完成させる。Hereinafter, the emitter of the bipolar transistor and the source / drain region of the N-channel MOS transistor are formed,
Next, the source / drain regions of the P-channel MOS transistor are formed to complete the Bi-CMOS IC.
以上最近のBi−CMOSプロセスの一例を示したが、このプ
ロセスによればバイポーラトランジスタのコレクタ領域
となるＮウェル4BとＰチャネルMOSトランジスタ形成領
域のＮウェル4Aとを同時に形成しているため、Ｐチャネ
ルMOSトランジスタを微細化する際、ゲート酸化膜の薄
膜化と共にＮウェル濃度を上げるが、この時同時にバイ
ポーラトランジスタを形成するＮウェル4Bも同様に濃度
が上ってしまう。このためMOSトランジスタの微細化を
進めていくと、バイポーラトランジスタのコレクタ−ベ
ース接合の耐圧が下がりバイポーラトランジスタの最大
動作電圧が低下してしまうと共に、コレクタ−ベース接
合容量が増加し、バイポーラトランジスタの高速動作の
防げとなるという欠点がある。An example of the recent Bi-CMOS process has been described above. According to this process, the N well 4B serving as the collector region of the bipolar transistor and the N well 4A of the P channel MOS transistor forming region are simultaneously formed. When the channel MOS transistor is miniaturized, the N well concentration is increased with the thinning of the gate oxide film, but at the same time, the concentration of the N well 4B forming the bipolar transistor is also increased. For this reason, as MOS transistors become finer, the collector-base junction breakdown voltage of the bipolar transistor decreases, the maximum operating voltage of the bipolar transistor decreases, and the collector-base junction capacitance increases, increasing the bipolar transistor's operating speed. It has the drawback that it prevents movement.
本発明の目的は、バイポーラトランジスタの特性を劣化
させることなくCMOSトランジスタの微細化が可能な半導
体装置の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device, which enables miniaturization of CMOS transistors without deteriorating the characteristics of bipolar transistors.
本発明の半導体装置の製造方法は、Ｐ型半導体基板上に
N+型埋込層を形成したのち全面にＰ型エピタキシャル層
を形成する工程と、前記N+型埋込層上の前記エピタキシ
ャル層にN+型埋込層に接続し、バイポーラトランジスタ
及びCMOSトランジスタのＰチャネルMOSトランジスタ形
成領域となるＮウェルをそれぞれ形成する工程と、ホウ
素をイオン注入し前記バイポーラトランジスタ形成領域
となるＮウェルのＮ型不純物濃度を下げる工程と、Ｎ型
不純物濃度の低下した前記Ｎウェルの上部にベース領域
を形成する工程とを含んで構成される。A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device on a P-type semiconductor substrate.
Forming a P-type epitaxial layer on the entire surface after forming the N + -type buried layer is connected to the N + -type buried layer in the epitaxial layer on said N + -type buried layer, bipolar transistors and CMOS transistors Each of the N-wells forming the P-channel MOS transistor forming regions, the step of lowering the N-type impurity concentration of the N-well forming the bipolar transistor forming regions by implanting boron ions, and the step of reducing the N-type impurity concentration. And a step of forming a base region on the N well.
以下、本発明の実施例について図面を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図（ａ），（ｂ）は本発明の一実施例を説明するた
めの半導体チップの断面図である。1 (a) and 1 (b) are sectional views of a semiconductor chip for explaining one embodiment of the present invention.
先ず、第１図（ａ）に示す様に、Ｐ型基板１にN+型埋込
層２を形成したのち全面にＰ型エピタキシャル層３を２
〜５μｍ程度の厚さに成長させる。次で、N+型埋込層２
上のエピタキシャル層３にＰチャネルMOSトランジスタ
形成領域とバイポーラトランジスタ形成領域となるＮウ
ェル4A,4Bを形成する。First, as shown in FIG. 1 (a), an N + type buried layer 2 is formed on a P type substrate 1, and then a P type epitaxial layer 3 is formed on the entire surface.
Grow to a thickness of about 5 μm. Next, N + type buried layer 2
In the upper epitaxial layer 3, N wells 4A and 4B to be a P channel MOS transistor forming region and a bipolar transistor forming region are formed.
次に、第１図（ｂ）に示す様に、素子分離酸化膜5,ゲー
ト酸化膜10を形成したのち多結晶シリコンからなるゲー
ト電極６及びN+型コレクタコンタクト領域７を形成す
る。次に、Ｎウェル4Bを除いてホトレジスト等からなる
マスク11を形成し、バイポーラトランジスタのベース領
域を形成する際、100〜200keVでホウ素を１×1011〜１
×1014cm-2程度イオン注入し、ベース接合近傍のＮウェ
ル濃度を低下させ、N-ウェル領域９を形成する。次に、
10〜30keVの低加速エネルギーでホウ素をイオン注入す
ることによりベース領域８を形成する。Next, as shown in FIG. 1B, after forming an element isolation oxide film 5 and a gate oxide film 10, a gate electrode 6 made of polycrystalline silicon and an N + type collector contact region 7 are formed. Next, except for the N well 4B, a mask 11 made of photoresist or the like is formed, and when forming the base region of the bipolar transistor, boron is added at 1 × 10 11 -1 at 100 to 200 keV.
Ion implantation is performed at about × 10 14 cm -2 to reduce the N well concentration near the base junction and form the N − well region 9. next,
The base region 8 is formed by ion-implanting boron with a low acceleration energy of 10 to 30 keV.
第１図（ｂ）のＡ−Ａ′線断面における深さ方向の不純
物の濃度分布を第２図に示す。FIG. 2 shows the concentration distribution of impurities in the depth direction in the cross section taken along the line AA ′ of FIG. 1 (b).
第２図に示したように、バイポーラトランジスタ形成領
域のＮウェル4BのＮ型不純物濃度はホウ素のイオン注入
により低下する。従って、従来のように、バイポーラト
ランジスタのコレクタ−ベース接合の耐圧の低下や、コ
レクタ−ベース接合の容量の増加はなくなる。As shown in FIG. 2, the N-type impurity concentration of the N well 4B in the bipolar transistor formation region is lowered by the boron ion implantation. Therefore, unlike the conventional case, the breakdown voltage of the collector-base junction of the bipolar transistor is not lowered and the capacitance of the collector-base junction is not increased.
以上説明したように本発明によれば、バイポーラトラン
ジスタのベース領域形成の前又は形成後にＮウェルに高
加速エネルギーでホウ素をイオン注入しその不純物濃度
を下げることにより、これまでCMOSトランジスタの微細
化及びバイポーラトランジスタの耐圧維持，高速化に対
して防げとなっていたＮウェルの濃度に対して、CMOSト
ランジスタ形成領域のＮウェルの濃度を自由に設定出来
るため、CMOSトランジスタの微細化が容易にできる効果
がある。As described above, according to the present invention, before or after the formation of the base region of the bipolar transistor, boron is ion-implanted into the N well with high acceleration energy to reduce the impurity concentration thereof, and thus the miniaturization of the CMOS transistor has been achieved so far. The concentration of the N well in the CMOS transistor formation region can be freely set in contrast to the concentration of the N well that has been prevented from maintaining the breakdown voltage and increasing the speed of the bipolar transistor, so that the CMOS transistor can be easily miniaturized. There is.
又、バイポーラトランジスタの最高動作電圧を高く維持
出来るだけでなく、コレクタ−ベース接合容量も減少す
るため、バイポーラトランジスタの高速動作にも有利で
あるという利点がある。Further, not only the maximum operating voltage of the bipolar transistor can be maintained high, but also the collector-base junction capacitance is reduced, which is advantageous for high-speed operation of the bipolar transistor.
第１図（ａ），（ｂ）は本発明の一実施例を説明するた
めの半導体チップの断面図、第２図は第１図（ｂ）のＡ
−Ａ′線断面における不純物の濃度分布を示す図、第３
図は従来の半導体装置の製造方法を説明するための半導
体チップの断面図である。 １……Ｐ型基板、２……N+型埋込層、３……Ｐ型エピタ
キシャル層、4A,4B……Ｎウェル、５……素子分離酸化
膜、６……ゲート電極、７……コレクタコンタクト領
域、８……ベース領域、９……N-ウェル、10……ゲート
酸化膜、11……マスク。1 (a) and 1 (b) are cross-sectional views of a semiconductor chip for explaining one embodiment of the present invention, and FIG. 2 is A in FIG. 1 (b).
FIG. 3 is a diagram showing the concentration distribution of impurities in the section taken along the line AA, FIG.
FIG. 1 is a sectional view of a semiconductor chip for explaining a conventional method of manufacturing a semiconductor device. 1 ... P-type substrate, 2 ... N + type buried layer, 3 ... P-type epitaxial layer, 4A, 4B ... N well, 5 ... Element isolation oxide film, 6 ... Gate electrode, 7 ... Collector contact region, 8 ... Base region, 9 ... N - well, 10 ... Gate oxide film, 11 ... Mask.
Claims (1)
のち全面にＰ型エピタキシャル層を形成する工程と、前
記N+型埋込層上の前記エピタキシャル層にN+型埋込層に
接続し、バイポーラトランジスタ及びCMOSトランジスタ
のＰチャネルMOSトランジスタ形成領域となるＮウェル
をそれぞれ形成する工程と、ホウ素をイオン注入し前記
バイポーラトランジスタ形成領域となるＮウェルのＮ型
不純物濃度を下げる工程と、Ｎ型不純物濃度の低下した
前記Ｎウェルの上部にベース領域を形成する工程とを含
むことを特徴とする半導体装置の製造方法。1. A forming a P-type epitaxial layer on the entire surface after forming the N + -type buried layer on a P-type semiconductor substrate, buried N + -type on the epitaxial layer on said N + -type buried layer A step of forming N wells each of which is to be a P-channel MOS transistor forming region of a bipolar transistor and a CMOS transistor, and boron is ion-implanted to lower the N-type impurity concentration of the N well to be the bipolar transistor forming region. A method of manufacturing a semiconductor device, comprising: a step of forming a base region on the N well having a reduced N-type impurity concentration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62075314A JPH07101717B2 (en) | 1987-03-27 | 1987-03-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62075314A JPH07101717B2 (en) | 1987-03-27 | 1987-03-27 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63240058A JPS63240058A (en) | 1988-10-05 |
| JPH07101717B2 true JPH07101717B2 (en) | 1995-11-01 |
Family
ID=13572670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62075314A Expired - Lifetime JPH07101717B2 (en) | 1987-03-27 | 1987-03-27 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07101717B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2575876B2 (en) * | 1989-05-17 | 1997-01-29 | 株式会社東芝 | Semiconductor device |
| US6130122A (en) * | 1997-07-21 | 2000-10-10 | Texas Instruments Incorporated | Method for forming a BiCMOS integrated circuit with Nwell compensation implant and method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60167367A (en) * | 1984-02-09 | 1985-08-30 | Nec Corp | Semiconductor device |
| JPS61182253A (en) * | 1985-02-08 | 1986-08-14 | Oki Electric Ind Co Ltd | Manufacture of a semiconductor ic device |
-
1987
- 1987-03-27 JP JP62075314A patent/JPH07101717B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63240058A (en) | 1988-10-05 |
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