JPH0697454A - Monovatile semiconductor memory device and driving method thereof - Google Patents
Monovatile semiconductor memory device and driving method thereofInfo
- Publication number
- JPH0697454A JPH0697454A JP4243423A JP24342392A JPH0697454A JP H0697454 A JPH0697454 A JP H0697454A JP 4243423 A JP4243423 A JP 4243423A JP 24342392 A JP24342392 A JP 24342392A JP H0697454 A JPH0697454 A JP H0697454A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- floating gate
- semiconductor memory
- gate electrode
- channel region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、超小型半導体装置にか
かわり、特に電気的に書き込み、及び電気的に消去可能
な二重ゲート構造を持つ不揮発性メモリに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microminiature semiconductor device, and more particularly to a non-volatile memory having a double gate structure that is electrically writable and electrically erasable.
【０００２】[0002]
【従来の技術】現在、浮遊ゲートを中間電極として持
ち、基板と浮遊ゲートの間でトンネル電流をやりとりす
る事で電気的な書き込み及び消去を可能にする二重ゲー
ト型不揮発性メモリは、４メガビットのＬＳＩが量産さ
れ、１６メガビットの開発が進んでいる。それととも
に、要求される信頼度を確保する事は困難になりつつあ
る。たとえば、基板と浮遊ゲート電極間の絶縁膜が１０
０Å程度になってくると今まで表れなかったような、い
わゆるストレス・リークという現象が出現する事が報告
されている（IEEE ED-35(1988)2259）。これは、この型
の不揮発性メモリの場合、高電界により酸化膜中を電流
が直接流れるので、酸化膜には常に強い電気的ストレス
が加わる。それによって、酸化膜は次第に劣化し、必要
な絶縁性が維持出来なくなってくる。すなわち、図２に
おいて、浮遊ゲート下の絶縁膜を流れるリーク電流はス
トレスを受ける前は曲線ａで示される程度であったもの
が、ストレスを受けると曲線ｂの様に増加してしまう。2. Description of the Related Art Currently, a dual-gate type nonvolatile memory which has a floating gate as an intermediate electrode and enables electric writing and erasing by exchanging a tunnel current between a substrate and a floating gate is a 4-megabit memory. Is being mass-produced, and 16-megabit development is in progress. At the same time, it is becoming difficult to secure the required reliability. For example, if the insulating film between the substrate and the floating gate electrode is 10
It has been reported that a so-called stress leak phenomenon that did not appear until now appears at about 0 Å (IEEE ED-35 (1988) 2259). This is because in the case of this type of non-volatile memory, a current flows directly through the oxide film due to the high electric field, so that a strong electric stress is always applied to the oxide film. As a result, the oxide film gradually deteriorates, and the required insulation cannot be maintained. That is, in FIG. 2, the leakage current flowing through the insulating film under the floating gate was about the level shown by the curve a before the stress was applied, but it increased like the curve b when the stress was applied.
【０００３】このストレスによるリーク電流の発生のメ
カニズムは分かっていないが、絶縁膜か薄いほど顕著で
あった。その為、絶縁膜の厚みは少なくとも１００Åは
必要であり、微細化に伴ってアスペクト比が大きくなっ
てしまい、集積度向上の大きな障害になっていた。又、
絶縁膜が厚いと、当然印加電圧も高くなり駆動回路の負
担も大きかった。例えば、浮遊ゲート下の絶縁膜には書
き込み時に約７Ｖの電圧を加えねばならず、その為には
制御ゲートには２２Ｖもの高電圧の印加が必要であっ
た。しかし、薄い絶縁膜を用いて印加電圧を低くする
と、ストレスリークが発生してしまい信頼性に欠けると
いう問題点があった。Although the mechanism of the generation of leak current due to this stress is not known, it was more remarkable as the insulating film was thinner. Therefore, the thickness of the insulating film needs to be at least 100 Å, and the aspect ratio increases with miniaturization, which is a major obstacle to improvement in the degree of integration. or,
If the insulating film is thick, the applied voltage is naturally high, and the load on the drive circuit is heavy. For example, a voltage of about 7 V must be applied to the insulating film below the floating gate at the time of writing, which requires application of a voltage as high as 22 V to the control gate. However, when the applied voltage is lowered by using a thin insulating film, there is a problem that stress leak occurs and reliability is deteriorated.
【０００４】[0004]
【発明が解決しようとする課題】即ち、従来の浮遊ゲー
ト下の絶縁膜は１００Å以上であったが為に、集積度の
向上に限界があった。That is, since the conventional insulating film under the floating gate has a thickness of 100 Å or more, there is a limit to the improvement of the degree of integration.
【０００５】本発明は、絶縁膜の厚みを大幅に減少させ
ると共に、ストレスリークの問題を解決することによっ
て、長期信頼性の高い不揮発性半導体メモリを提供する
ことを目的とする。It is an object of the present invention to provide a non-volatile semiconductor memory with high long-term reliability by significantly reducing the thickness of an insulating film and solving the problem of stress leak.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決する為
に、本発明の特徴は、半導体基板と、この半導体基板に
設けられたソース、ドレイン及びチャネル領域と、この
チャネル領域上に第１の絶縁膜を介して形成された浮遊
ゲート電極と、この浮遊ゲート電極上に第２の絶縁膜を
介して形成された制御ゲート電極を備えた半導体メモリ
装置であって、トンネル現象を起こさせる為に前記第１
の絶縁膜に加える電圧を、４．５Ｖ以下にしたことであ
る。その理由及び作用は次の通りである。In order to solve the above problems, the present invention is characterized in that a semiconductor substrate, a source, a drain and a channel region provided in the semiconductor substrate and a first region on the channel region are provided. What is claimed is: 1. A semiconductor memory device comprising: a floating gate electrode formed via an insulating film; and a control gate electrode formed on the floating gate electrode via a second insulating film. The first
That is, the voltage applied to the insulating film is set to 4.5 V or less. The reason and action are as follows.
【０００７】[0007]
【作用】本発明者は、ストレスによる絶縁特性の劣化の
性質を解明すべく実験を繰り返したが、その結果次の事
実が判明した。即ち、ストレスは高い電界によるのでは
なく、電子の持つエネルギーによると思われるのであ
る。図３に、絶縁膜に加わる電圧（ストレス電圧）とス
トレスによるリーク電流との関係を、低い電圧範囲にお
いて示す。図から分かる様に、絶縁膜が厚い程リーク電
流は大きくなるが、ストレス電圧が或る程度以下に小さ
くなると、膜の厚みとは無関係に急激に小さくなるので
ある。実験によれば、リーク電流は５Ｖで非常に小さく
なり、４．５Ｖでは測定できる範囲ではなくなった。即
ち、問題は電子のエネルギーであり、これが或るしきい
値を越えると絶縁膜にダメージを与えると考えられる。
従って、ストレス電圧を５Ｖ以下、より好ましくは４．
５Ｖ以下まで下げればリーク電流は、実質的になくなる
ことが分かる。この場合、適切なトンネル現象を起こさ
せる絶縁膜の厚みは３０Åから４０Å程度となる。The present inventor repeated experiments to clarify the nature of the deterioration of the insulation characteristics due to stress, and as a result, the following facts were found. That is, the stress seems to be due to the energy of the electrons, not the high electric field. FIG. 3 shows the relationship between the voltage applied to the insulating film (stress voltage) and the leakage current due to stress in the low voltage range. As can be seen from the figure, the thicker the insulating film is, the larger the leak current is, but when the stress voltage is reduced to a certain level or less, it is rapidly reduced regardless of the thickness of the film. According to the experiment, the leak current was very small at 5V and was out of the measurable range at 4.5V. That is, the problem is electron energy, and it is considered that the insulating film is damaged when this exceeds a certain threshold value.
Therefore, the stress voltage is 5 V or less, more preferably 4.
It can be seen that if the voltage is reduced to 5 V or less, the leak current is practically eliminated. In this case, the thickness of the insulating film that causes an appropriate tunneling phenomenon is about 30Å to 40Å.
【０００８】[0008]
【実施例】第１図は本発明による不揮発性半導体メモリ
装置の実施例の断面図を示す。1 is a sectional view of an embodiment of a nonvolatile semiconductor memory device according to the present invention.
【０００９】この半導体メモリ装置は、シリコン基板４
にチャネル領域を挾んで形成されたＮ導電型のソース及
びドレイン領域５，６間上に、第１のゲート酸化膜３
ａ、多結晶シリコン浮遊ゲート２、第２のゲート酸化膜
３ｂ及び多結晶シリコン制御ゲート１が各々積層されて
いる。This semiconductor memory device has a silicon substrate 4
The first gate oxide film 3 is formed between the N-conductivity type source and drain regions 5 and 6 which are formed by sandwiching the channel region.
a, a polycrystalline silicon floating gate 2, a second gate oxide film 3b, and a polycrystalline silicon control gate 1 are stacked.
【００１０】従来装置との違いは、第１のゲート酸化膜
にかかる電圧が４．５Ｖ以下と極めて低いという特徴を
持つ点にある。トンネル電流を基板側と浮遊ゲート２と
の間で選択的に出し入れする事で、浮遊ゲートでの蓄積
電荷の有無によって情報を保持するタイプのこの素子で
は、従来、上記電圧が低いとトンネル電流が流れにく
く、書き込み、読みだしに時間がかかって使えない。し
かし、それを克服するためには第１のゲート酸化膜厚を
薄膜化すれば、リーク電流が発生してしまう。本発明で
は、電圧及び膜厚を大幅に減少させることによって問題
を解決した。つまり、トンネル電流は電圧ではなく、電
界によって決まっている事による。The difference from the conventional device is that the voltage applied to the first gate oxide film is 4.5 V or less, which is extremely low. In this type of device that retains information depending on the presence or absence of accumulated charges in the floating gate by selectively taking in and out the tunnel current between the substrate side and the floating gate 2, when the voltage is low, the tunnel current It is hard to flow and it takes a long time to write and read, so it cannot be used. However, in order to overcome this, if the first gate oxide film thickness is reduced, a leak current will occur. The present invention solves the problem by greatly reducing the voltage and film thickness. That is, the tunnel current is determined by the electric field, not the voltage.
【００１１】次に、この構造の一実施例の製造方法を示
す。Ｐ型単結晶シリコン基板上に塩酸を微量に含む熱酸
化膜を４０オングストローム形成し、続いて多結晶シリ
コンを１０００オングストローム堆積し、そこに燐を導
入した後、ＲＩＥを用いて浮遊ゲートを形成するために
パターニングする。それに続いて、自己整合的にソー
ス、ドレインを形成するために砒素をイオン注入する。
その不純物活性化のための熱処理を施した後、ＳｉＯ2
膜を１００オングストローム形成し、更に多結晶シリコ
ンを２０００オングストローム堆積した後に、それをＲ
ＩＥでパターニングする。その時、制御ゲート電極と浮
遊ゲート電極の間のキャパシタンスと浮遊ゲート電極と
基板との間のキャパシタンスの比が３：１以上になるよ
うにパターニングしてある。図３に示した様に、酸化膜
の厚さによらずに、ストレス電圧が４．５Ｖ以下になっ
てくるとストレス・リーク電流はほとんど見られなくな
る。この特徴を用いて、上記の装置を信頼性高く動作さ
せる。その具体的方法は次の通りである。Next, a manufacturing method of an embodiment of this structure will be described. A thermal oxide film containing a small amount of hydrochloric acid is formed to a thickness of 40 angstroms on a P-type single crystal silicon substrate, then polycrystalline silicon is deposited to a thickness of 1000 angstroms, phosphorus is introduced therein, and then a floating gate is formed using RIE. For patterning. Subsequently, arsenic is ion-implanted to form the source and drain in a self-aligned manner.
After heat treatment for activating the impurities, SiO 2
After forming a film of 100 angstrom and further depositing polycrystalline silicon of 2000 angstrom, it is R
Pattern with IE. At that time, patterning is performed so that the ratio of the capacitance between the control gate electrode and the floating gate electrode and the capacitance between the floating gate electrode and the substrate is 3: 1 or more. As shown in FIG. 3, regardless of the thickness of the oxide film, when the stress voltage becomes 4.5 V or less, the stress leak current is hardly seen. This feature is used to operate the device reliably. The specific method is as follows.
【００１２】情報の書き込みは、図４に示す様に、制御
電極１に６Ｖかける。その結果、浮遊ゲート電極２と基
板４の間には４Ｖかかる事になる。これは、酸化膜にか
かる電界としては１０ＭＶ／ｃｍを意味し十分なトンネ
ル電流を確保する事ができる。浮遊ゲートから電荷を抜
く場合はこの逆になる様にすればよい。すなわち、この
酸化膜に今度は逆方向に４Ｖを印加すれば良い。データ
を読む場合は、制御電極に２Ｖかけ、チャネルの導電状
態によって浮遊ゲート上の荷電の有無が確認できる。こ
の場合、浮遊ゲートと基板の間には１．５Ｖかかる事に
なり、酸化膜電界に換算すると、４ＭＶ／ｃｍ程度にな
り通常であるとストレス・リークが問題になるが、今回
の場合は書き込み電圧が４．５Ｖ以下であるので、それ
は全く問題にならない。To write information, as shown in FIG. 4, 6V is applied to the control electrode 1. As a result, 4V is applied between the floating gate electrode 2 and the substrate 4. This means that the electric field applied to the oxide film is 10 MV / cm, and a sufficient tunnel current can be secured. In the case of discharging the electric charge from the floating gate, the reverse order may be adopted. That is, 4 V may be applied to this oxide film in the opposite direction this time. When reading data, the control electrode is applied with 2 V, and the presence or absence of charge on the floating gate can be confirmed by the conduction state of the channel. In this case, 1.5 V is applied between the floating gate and the substrate, which is about 4 MV / cm when converted to the electric field of the oxide film, and stress leak becomes a problem under normal conditions. Since the voltage is below 4.5V, it is not a problem at all.
【００１３】以上の様に、高信頼性の不揮発性メモリを
達成する事ができる。また、Ｎ基板上にＰ型のソース、
ドレインを持った場合にも、もちろん適用出来る事は言
うまでもない。As described above, a highly reliable nonvolatile memory can be achieved. In addition, a P-type source on the N substrate,
Needless to say, it can be applied to the case of having a drain.
【００１４】[0014]
【発明の効果】以上説明したように本発明によれば、高
集積化にすぐれた電気的に書き込み及び消去可能な不揮
発性メモリを、長期信頼性を確保しながら実現する事が
できる。As described above, according to the present invention, an electrically writable and erasable nonvolatile memory excellent in high integration can be realized while ensuring long-term reliability.
【図１】本発明を実施した不揮発性半導体メモリー・セ
ルの断面図である。FIG. 1 is a cross-sectional view of a non-volatile semiconductor memory cell embodying the present invention.
【図２】典型的なストレス印加前、印加後の酸化膜に流
れるトンネル電流を示すグラフ図であり、１００μｍ×
１００μｍλＭＣＳキャパシタを用い、ストレス電圧６
Ｖを印加する前後での結果を示す。FIG. 2 is a graph showing a typical tunnel current flowing through an oxide film before and after applying stress, which is 100 μm ×
Using a 100 μmλ MCS capacitor, stress voltage 6
The result before and after applying V is shown.
【図３】ストレス印加後のリーク電流と印加電圧との関
係を三種類の酸化膜厚に関して示したグラフ図であり１
００μｍ×１００μｍのＭＯＳキャパシタを用いた結果
を示す。FIG. 3 is a graph showing the relationship between the leak current after stress application and the applied voltage for three types of oxide film thicknesses.
The results of using a MOS capacitor of 00 μm × 100 μm are shown.
【図４】本発明のメモリーセルにデータを書き込む際の
模式図である。FIG. 4 is a schematic diagram when writing data to the memory cell of the present invention.
１ 制御ゲート電極 ２ 浮遊ゲート電極 ３ ゲート酸化膜 ３ａ 第一のゲート酸化膜 ３ｂ 第二のゲート酸化膜 ４ シリコン基板 ５ ｎ＋ソース領域 ６ ｎ＋ドレイン領域 1 Control Gate Electrode 2 Floating Gate Electrode 3 Gate Oxide Film 3a First Gate Oxide Film 3b Second Gate Oxide Film 4 Silicon Substrate 5 n + Source Region 6 n + Drain Region
Claims (4)
ス及びドレイン領域間にチャネル領域が画定され、その
チャネル領域上に第一の絶縁膜を介して浮遊ゲートが、
更にその上に第二の絶縁膜を介して制御ゲートが各々積
層された絶縁ゲート型電界効果トランジスタ構造を有
し、前記第一の絶縁膜に４．５Ｖ以下の電位差がかかる
事によって、第一の絶縁膜間をトンネル電流が流れて電
荷のやりとりをする事を特徴とする半導体メモリ装置。1. A channel region is defined between source and drain regions of one conductivity type provided in a semiconductor substrate, and a floating gate is formed on the channel region via a first insulating film.
Further, an insulating gate type field effect transistor structure in which control gates are laminated on each other via a second insulating film, and a potential difference of 4.5 V or less is applied to the first insulating film, A semiconductor memory device characterized in that a tunnel current flows between the insulating films to exchange charges.
第一及び第二の絶縁膜は二酸化シリコン膜である事を特
徴とする請求項１記載の半導体メモリ装置。2. The semiconductor memory device according to claim 1, wherein the semiconductor substrate is silicon, and the first and second insulating films are silicon dioxide films.
ス及びドレイン領域間にチャネル領域が画定され、その
チャネル領域上に第一の絶縁膜を介して浮遊ゲートが、
更にその上に第二の絶縁膜を介して制御ゲートが積層さ
れた絶縁ゲート型電界効果トランジスタ構造を有し、前
記第一の絶縁膜の厚さが３０Å以上４０Å以下であり、
第一の絶縁膜間をトンネル電流が流れて電荷のやりとり
をする事を特徴とする半導体メモリ装置。3. A channel region is defined between source and drain regions of one conductivity type provided on a semiconductor substrate, and a floating gate is formed on the channel region via a first insulating film.
Furthermore, it has an insulated gate type field effect transistor structure in which a control gate is laminated on it via a second insulating film, and the thickness of the first insulating film is 30 Å or more and 40 Å or less,
A semiconductor memory device characterized in that a tunnel current flows between first insulating films to exchange charges.
れたソース、ドレイン及びチャネル領域と、このチャネ
ル領域上に第１の絶縁膜を介して形成された浮遊ゲート
電極と、この浮遊ゲート電極上に第２の絶縁膜を介して
形成された制御ゲート電極を備え、前記第１の絶縁膜の
厚みは４０Å以下である電気的に書き換え可能な不揮発
性半導体メモリ装置を駆動する方法であって、前記第１
の絶縁膜にトンネル電流を起こさせるべく印加される電
圧の大きさは、４．５Ｖを超えない範囲から選ばれてい
ることを特徴とする駆動方法。4. A semiconductor substrate, a source, a drain and a channel region provided on the semiconductor substrate, a floating gate electrode formed on the channel region via a first insulating film, and a floating gate electrode on the floating gate electrode. A method for driving an electrically rewritable nonvolatile semiconductor memory device, comprising: a control gate electrode formed via a second insulating film, wherein the thickness of the first insulating film is 40 Å or less, The first
The driving method characterized in that the magnitude of the voltage applied to cause a tunnel current to the insulating film is selected from the range not exceeding 4.5V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4243423A JPH0697454A (en) | 1992-09-11 | 1992-09-11 | Monovatile semiconductor memory device and driving method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4243423A JPH0697454A (en) | 1992-09-11 | 1992-09-11 | Monovatile semiconductor memory device and driving method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0697454A true JPH0697454A (en) | 1994-04-08 |
Family
ID=17103653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4243423A Pending JPH0697454A (en) | 1992-09-11 | 1992-09-11 | Monovatile semiconductor memory device and driving method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0697454A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1837900A3 (en) * | 2006-03-21 | 2008-10-15 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device |
| US7692232B2 (en) | 2006-03-21 | 2010-04-06 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device |
| US7723773B2 (en) | 2006-02-10 | 2010-05-25 | Semiconductor Energy Laboratory Co., Ltd | Nonvolatile semiconductor storage device and manufacturing method thereof |
| US7786526B2 (en) | 2006-03-31 | 2010-08-31 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device |
| US7842992B2 (en) | 2006-03-31 | 2010-11-30 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device having floating gate that includes two layers |
| US8022460B2 (en) | 2006-03-31 | 2011-09-20 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device |
| US8212302B2 (en) | 2006-03-21 | 2012-07-03 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device |
| US8212304B2 (en) | 2006-03-31 | 2012-07-03 | Semiconductor Energy Laboratory Co., Ltd. | Method for deleting data from NAND type nonvolatile memory |
-
1992
- 1992-09-11 JP JP4243423A patent/JPH0697454A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7723773B2 (en) | 2006-02-10 | 2010-05-25 | Semiconductor Energy Laboratory Co., Ltd | Nonvolatile semiconductor storage device and manufacturing method thereof |
| US8338257B2 (en) | 2006-02-10 | 2012-12-25 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor storage device and manufacturing method thereof |
| EP1837900A3 (en) * | 2006-03-21 | 2008-10-15 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device |
| US7692232B2 (en) | 2006-03-21 | 2010-04-06 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device |
| US8212302B2 (en) | 2006-03-21 | 2012-07-03 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device |
| US8227863B2 (en) | 2006-03-21 | 2012-07-24 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device |
| US7786526B2 (en) | 2006-03-31 | 2010-08-31 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device |
| US7842992B2 (en) | 2006-03-31 | 2010-11-30 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device having floating gate that includes two layers |
| US8022460B2 (en) | 2006-03-31 | 2011-09-20 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device |
| US8212304B2 (en) | 2006-03-31 | 2012-07-03 | Semiconductor Energy Laboratory Co., Ltd. | Method for deleting data from NAND type nonvolatile memory |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5629541A (en) | Semiconductor memory device constituted by single transistor type non-volatile cells and facilitated for both electrical erasing and writing of data | |
| US4881108A (en) | Semiconductor device | |
| US5739569A (en) | Non-volatile memory cell with oxide and nitride tunneling layers | |
| US4996572A (en) | Semiconductor memory device | |
| US5500816A (en) | Non-volatile semiconductor memory device and manufacturing method thereof | |
| WO2001017030A1 (en) | Non-volatile memory structure for twin-bit storage and methods of making same | |
| JP3630491B2 (en) | Semiconductor device | |
| JPH0697454A (en) | Monovatile semiconductor memory device and driving method thereof | |
| US6483133B2 (en) | EEPROM with high channel hot carrier injection efficiency | |
| US5151761A (en) | Nonvolatile semiconductor memory device with isolated gate electrodes | |
| US5252846A (en) | Semiconductor memory device with an improved erroneous write characteristic and erasure characteristic | |
| EP0282023B1 (en) | Semiconductor memory device | |
| JP3028984B2 (en) | Manufacturing method of nonvolatile semiconductor memory device | |
| JP3251699B2 (en) | Non-volatile storage device | |
| JP3512975B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0878544A (en) | Nonvolatile semiconductor memory | |
| JPH0450754B2 (en) | ||
| JPH02174171A (en) | Semiconductor storage device | |
| JPH0555600A (en) | Semiconductor nonvolatile memory device | |
| JPH06334192A (en) | Non-volatile semiconductor memory | |
| JPH06342894A (en) | Nonvoltile semiconductor memory | |
| JPH04287976A (en) | Semiconductor memory | |
| JPH065875A (en) | Nonvolatile memory | |
| JPH06104449A (en) | Semiconductor nonvolatile memory cell and semiconductor nonvolatile memory using it | |
| JPH09260515A (en) | Nonvolatile semiconductor storage device and its manufacture |