JPH0697386A - Fabrication of capacitor - Google Patents
Fabrication of capacitorInfo
- Publication number
- JPH0697386A JPH0697386A JP4248084A JP24808492A JPH0697386A JP H0697386 A JPH0697386 A JP H0697386A JP 4248084 A JP4248084 A JP 4248084A JP 24808492 A JP24808492 A JP 24808492A JP H0697386 A JPH0697386 A JP H0697386A
- Authority
- JP
- Japan
- Prior art keywords
- film
- conductive film
- capacitor
- storage electrode
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は, ＩＣの構成素子である
キャパシタの製造方法に関する。近年目覚ましく発達し
ている微細加工技術により素子の寸法は飛躍的に小さく
なってきている。これに伴うキャパシタの容量確保のた
めに，深いトレンチ構造や，多枚フィン構造が用いられ
ているが，これらの構造のキャパシタ形成方法，特に，
エッチング方法については技術的に大変な困難が伴う。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor which is a constituent element of an IC. In recent years, due to the remarkable development of microfabrication technology, the dimensions of devices have been dramatically reduced. A deep trench structure and a multi-fin structure are used to secure the capacitance of the capacitor accompanying this.
The etching method is technically very difficult.
【０００２】そこで本発明は，エッチングの特性である
マイクロローディング効果を用いて，蓄積電極本体と，
その表面への凹凸を同時に形成し，短手番で容量の確保
を行う方法である。Therefore, the present invention uses a microloading effect, which is a characteristic of etching, to form a storage electrode body,
It is a method of forming irregularities on the surface at the same time and securing the capacity in a short time.
【０００３】[0003]
【従来の技術】図５は従来例の説明図である。図におい
て，21はSi基板，22はSiO2膜，23は第１のポリSi膜, 2
3'は蓄積電極,24は Si3N4膜, 24'は誘電体膜 , 25は
第２のポリSi膜, 25'は対向電極, 26は第一のレジスト
膜, 27は第二のレジスト膜である。2. Description of the Related Art FIG. 5 is an explanatory view of a conventional example. In the figure, 21 is a Si substrate, 22 is a SiO 2 film, 23 is a first poly-Si film, 2
3'is a storage electrode, 24 is a Si 3 N 4 film, 24 'is a dielectric film, 25 is a second poly-Si film, 25' is a counter electrode, 26 is a first resist film, 27 is a second resist It is a film.
【０００４】従来のスタック構造のキャパシタでは，図
５（ａ）に模式断面図で示すように，当初，その容量の
確保に平面的な広がりのみを利用していた。そのため，
より微細なギャパシタでは容量が不足する。In the conventional stack structure capacitor, as shown in the schematic sectional view of FIG. 5 (a), only the planar spread was initially used to secure the capacity. for that reason,
The capacity of the finer gap capacitors is insufficient.
【０００５】そこで，図５（ｂ）に模式断面図で示すよ
うに，フィン構造のキャパシタがＩＥＤＭにおいて１９
８８年に発表されたが，容量増加のためには，フィンの
枚数を増やす必要があり，工程が増加するとともに，技
術的にも困難が伴う。Therefore, as shown in the schematic sectional view of FIG.
It was announced in 1988, but in order to increase the capacity, it is necessary to increase the number of fins, which increases the number of steps and technically involves difficulties.
【０００６】そのため，図５（ｃ）〜（ｄ）に蓄積電極
の工程順模式断面図で示すように，従来のスタック型キ
ャパシタの蓄積電極23' の表面に凹凸を形成して，容量
を確保するキャパシタが発明された。（平３−１３３１
７２）Therefore, as shown in FIGS. 5 (c) to 5 (d), which are schematic cross-sectional views of the storage electrode in the order of steps, unevenness is formed on the surface of the storage electrode 23 'of the conventional stack type capacitor to secure the capacitance. A capacitor that does this was invented. (Flat 3-1331
72)
【０００７】[0007]
【発明が解決しようとする課題】この方法では, スタッ
ク型キャパシタの蓄積電極23' の表面上に凹凸を形成す
る方法として，先ず，第１のレジスト膜26をマスクとし
て, 蓄積電極23' 形成用の第１のポリSi膜23にハーフエ
ッチングを施した後に，再度, 第２のレジスト膜17をマ
スクとして, パターニングを行って，個々のキャパシタ
の蓄積電極23' を形成するという方法であった。In this method, as a method of forming irregularities on the surface of the storage electrode 23 'of the stack type capacitor, first, the first resist film 26 is used as a mask to form the storage electrode 23'. The first poly-Si film 23 was half-etched, and then the second resist film 17 was used as a mask to perform patterning again to form the storage electrodes 23 'of the individual capacitors.
【０００８】そのため，フォトリソグラフィやエッチン
グの工程が増加するとともに，二度の蓄積電極形成のた
めのエッチングの位置合わせが困難であり，位置合わせ
の余裕度を考慮すると，単位面積当たりの容量が制限さ
れてしまうといった問題があった。As a result, the number of photolithography and etching processes is increased, and it is difficult to perform the etching alignment for forming the storage electrode twice. Considering the alignment margin, the capacitance per unit area is limited. There was a problem that it would be done.
【０００９】また，ハーフエッチングを用いず，図５
（ｅ）及び平面図を図５（ｆ）の左側に示すように，ス
タック型キャパシタの蓄積電極23' の上部に貫通部を形
成したものではストライプが分離されてしまい，キャパ
シタ構造としては，図５（ｆ）の右側に示すように，蓄
積電極23' 全体が一連に繋がっている必要があり，その
接続を保証するためには，パターン的制約を受けて，図
５（ｆ）に示すような穴ぼこ型の凹凸に限られて，容量
に寄与するキャパシタ絶縁膜の面積が減少してしまい，
効率の良い容量の確保をより困難なものとしていた。Further, without using half etching, as shown in FIG.
As shown in (e) and the plan view on the left side of FIG. 5 (f), stripes are separated in the stack type capacitor in which the penetrating portion is formed above the storage electrode 23 ', and the capacitor structure is As shown on the right side of FIG. 5 (f), the entire storage electrode 23 'needs to be connected in series, and in order to guarantee the connection, there is a pattern constraint, and as shown in FIG. 5 (f). The area of the capacitor insulating film that contributes to the capacitance is reduced due to the limited unevenness of the holes.
It was made more difficult to secure efficient capacity.
【００１０】本発明は，以上の点に鑑み，簡単な方法で
効率良く凹凸を形成して，容量を確保するキャパシタ形
成方法の開発を目的として提供されるものである。In view of the above points, the present invention is provided for the purpose of developing a capacitor forming method for efficiently forming irregularities by a simple method to secure a capacitance.
【００１１】[0011]
【課題を解決するための手段】図１は本発明の原理説明
図である。図において，１は半導体基板，２は絶縁膜，
３は第一の導電膜，3'は蓄積電極, ４はレジスト膜, 4'
は高密度凹凸パターン，５は誘電体膜，６は第二の導電
膜, 6'は対向電極である。FIG. 1 is a diagram for explaining the principle of the present invention. In the figure, 1 is a semiconductor substrate, 2 is an insulating film,
3 is a first conductive film, 3'is a storage electrode, 4 is a resist film, 4 '
Is a high-density concavo-convex pattern, 5 is a dielectric film, 6 is a second conductive film, and 6'is a counter electrode.
【００１２】問題解決の手段として，本発明では，従来
のスタック型キャパシタの蓄積電極5'表面上にレジスト
膜４を用いて，微細な高密度の凹凸パターン4'を形成
し，それをマスクとして，エッチング時にその微細なパ
ターンと周辺の広域なパターンとでは，エッチング速度
が変化する現象，いわゆる疎密パターンのマイクロロー
ディング効果を利用し，一つの蓄積電極5'上部に襞状の
凹凸パターンを形成するのと同時に，個々のキャパシタ
の蓄積電極5'を同時にエッチングにより形成することに
より，短手番で，素子面積当たりの容量を確保すること
ができる。As a means for solving the problem, in the present invention, a resist film 4 is used on the surface of the storage electrode 5'of the conventional stack type capacitor to form a fine high-density concavo-convex pattern 4 ', which is used as a mask. , The fine pattern and the wide area pattern in the periphery during etching utilize the phenomenon that the etching rate changes, that is, the micro-loading effect of the so-called sparse and dense pattern, and form a fold-shaped concavo-convex pattern on one storage electrode 5 '. At the same time, by simultaneously forming the storage electrodes 5'of the individual capacitors by etching, the capacitance per element area can be secured in a short time.
【００１３】即ち, 本発明の目的は, 図１（ａ）に示す
ように，絶縁膜２で被覆された半導体基板１上に第一の
導電膜３を形成する工程と,図１（ｂ）に示すように，
該第一の導電膜３上にレジスト膜４をパターニングし
て, 該第一の導電膜３上のキャパシタ形成領域上にレジ
スト膜４を用いて高密度凹凸パターン4'をパターニング
する工程と,図１（ｃ）に示すように，該第一の導電膜
３をレジスト膜４をマスクとし, マイクロローディング
効果を利用して, 該第一の導電膜３の途中までエッチン
グしてキャパシタ形成領域上に蓄積電極3'の凹凸パター
ンを形成すると同時に, キャパシタ形成領域外の第一の
導電膜３をエッチング除去して蓄積電極3'を画定形成す
る工程と,図１（ｄ）に示すように，該第一の導電膜３
上のレジスト膜４を除去する工程と,図１（ｅ）に示す
ように，パターニングされた第一の導電膜３上に誘電体
膜５を被覆する工程と,続いて，該半導体基板１上に第
二の導電膜６を形成し, パターニングして対向電極6'と
する工程とを含むことにより達成される。That is, an object of the present invention is to form a first conductive film 3 on a semiconductor substrate 1 covered with an insulating film 2 as shown in FIG. As shown in
A step of patterning a resist film 4 on the first conductive film 3 and patterning a high-density concavo-convex pattern 4 ′ using the resist film 4 on the capacitor formation region on the first conductive film 3; As shown in FIG. 1 (c), the first conductive film 3 is etched to the middle of the first conductive film 3 by using the resist film 4 as a mask and utilizing the microloading effect, so that it is formed on the capacitor formation region. At the same time as forming the concavo-convex pattern of the storage electrode 3 ′, a step of etching and removing the first conductive film 3 outside the capacitor formation region to define and form the storage electrode 3 ′, as shown in FIG. First conductive film 3
A step of removing the upper resist film 4 and a step of covering the patterned first conductive film 3 with a dielectric film 5 as shown in FIG. And forming a second conductive film 6 and patterning it to form the counter electrode 6 '.
【００１４】[0014]
【作用】本発明によれば, エッチングのマイクロローデ
ィング効果を用いることにより，蓄積電極形成用の第１
の導電膜を１度のパターニングでスタック型キャパシタ
用蓄積電極表面の微細な高密度パターンの凹凸と個々の
キャパシタに画定分離することが出来るために，工程の
短縮，及び容量の確保を図ることができる。According to the present invention, by using the microloading effect of etching, the first electrode for forming the storage electrode is formed.
Since the conductive film of can be separated and separated into individual capacitors by fine patterning of the high density pattern on the surface of the storage electrode for the stack type capacitor by patterning once, it is possible to shorten the process and secure the capacity. it can.
【００１５】[0015]
【実施例】図２はパターンの疎密度とエッチング深さ，
図３は本発明の一実施例の工程順模式断面図で示した説
明図，図４は本発明の一実施例に用いたエッチング装置
の模式断面図である。EXAMPLE FIG. 2 shows the pattern sparse density and etching depth,
FIG. 3 is an explanatory view showing schematic cross-sectional views in order of steps of one embodiment of the present invention, and FIG. 4 is a schematic cross-sectional view of an etching apparatus used in one embodiment of the present invention.
【００１６】図において，７はSi基板，８はSiO2膜，９
は第１のポリSi膜，9'は蓄積電極,10はレジスト膜, 11
は Si3N4膜, 11'は誘電体膜，12は第２のポリSi膜， 1
2'は対向電極, 13はキャパシタ, 14はチャンバ, 15は上
部電極, 16は下部電極, 17はＲＦ電源，18はガス導入
口, 19は排気口, 20はSi基板である。In the figure, 7 is a Si substrate, 8 is a SiO 2 film, and 9
Is the first poly-Si film, 9'is the storage electrode, 10 is the resist film, 11
Is a Si 3 N 4 film, 11 'is a dielectric film, 12 is a second poly-Si film, 1
2'is a counter electrode, 13 is a capacitor, 14 is a chamber, 15 is an upper electrode, 16 is a lower electrode, 17 is an RF power supply, 18 is a gas inlet, 19 is an exhaust port, and 20 is a Si substrate.
【００１７】図３により，本発明のキャパシタの製造方
法の一実施例について説明する。図３（ａ）に平面図
で，図３（ｂ）に模式断面図で示すように，4,000 Åの
厚さのSiO2膜８で被覆されたSi基板１上にＣＶＤ法によ
り, 8,000 Åの厚さに蓄積電極9'形成用の第１のポリSi
膜９を形成する。第１のポリSi膜はキャパシタ形成領域
で，SiO2膜８の開口部を通してSi基板７と接している。An embodiment of the method of manufacturing a capacitor according to the present invention will be described with reference to FIG. As shown in the plan view of FIG. 3 (a) and the schematic cross-sectional view of FIG. 3 (b), a 8,000 Å layer is formed on the Si substrate 1 covered with the SiO 2 film 8 having a thickness of 4,000 Å by the CVD method. First poly-Si for forming storage electrode 9'to thickness
The film 9 is formed. The first poly-Si film is in the capacitor formation region and is in contact with the Si substrate 7 through the opening of the SiO 2 film 8.
【００１８】第１のポリSi膜９上にレジスト膜10を１μ
ｍの厚さに塗布し，フォトリソグラフィにより幅0.35μ
ｍ, 長さ１μｍのストライプパターンを間隔0.35μｍ開
けて３本パターニングする。A resist film 10 having a thickness of 1 μm is formed on the first poly-Si film 9.
0.35μ wide by photolithography
Three stripe patterns each having a length of m and a length of 1 μm are spaced by 0.35 μm and patterned.
【００１９】図３（ｃ）に示すように，レジスト膜10を
マスクとして, 異方性ドライエッチングにより第１のポ
リSi膜９をエッチングして，蓄積電極9'を形成する。エ
ッチングには, 図４に示すＲＩＥ装置を用いて行った。
エッチングガスとして臭化水素(HBr) を150sccm の割合
でガス導入口18からチャンバ14内に導入し,13.56MHzの
ＲＦパワー150 Ｗ，チャンバ14内圧力 0.2 Torr, Si基
板温度30℃で第１のポリSi膜のエッチングを行った。As shown in FIG. 3C, the first poly-Si film 9 is etched by anisotropic dry etching using the resist film 10 as a mask to form a storage electrode 9 '. The etching was performed using the RIE device shown in FIG.
Hydrogen bromide (HBr) as an etching gas was introduced into the chamber 14 from the gas inlet 18 at a rate of 150 sccm, the RF power of 13.56 MHz was 150 W, the pressure in the chamber 14 was 0.2 Torr, and the Si substrate temperature was 30 ° C. The poly-Si film was etched.
【００２０】マイクロローディング効果を利用したエッ
チングでは，図２にパターンの疎密度とエッチング深さ
の関係で示すように，例えば，図２（ａ）に平面図で，
図２（ｂ）に断面図で示した２μｍのラインアンドスペ
ースのパターンでは，図２（ｃ）に示したエッチングレ
ートとラインアンドスペースパターンの図で分かるよう
に，第１のポリSi膜９のエッチングレートが約 3,000Å
／min であるのに対して, 本発明の一実施例で採用した
0.35μｍのラインアンドスペースのパターンではパター
ンとパターンの間の穴は，約 1,300Å／min とエッチン
グレートが約１／３に低下する。In the etching utilizing the microloading effect, as shown in the relationship between the sparse density of the pattern and the etching depth in FIG. 2, for example, in the plan view of FIG.
In the 2 μm line-and-space pattern shown in the cross-sectional view in FIG. 2B, as can be seen from the etching rate and line-and-space pattern shown in FIG. Etching rate is about 3,000Å
/ Min, but adopted in one embodiment of the present invention.
In the 0.35 μm line-and-space pattern, the hole between the patterns is about 1,300 Å / min, and the etching rate is reduced to about 1/3.
【００２１】そのため，本発明の一実施例では，厚さが
4,000 Åの第１のポリSi膜９のラインパターンの中を3,
000 Åの深さＢにエッチングしている間に, 蓄積電極9'
を画定するラインアンドスペースの外側Ａはオーバーエ
ッチングにより, 完全にエッチングが完了することとな
り, 図３（ｃ）に示す蓄積電極9'が形成できる。Therefore, in one embodiment of the present invention, the thickness is
3, in the line pattern of the first poly-Si film 9 of 4,000 Å
While etching to a depth B of 000 Å, the storage electrode 9 '
The outside A of the line-and-space that demarcates is completely etched by overetching, and the storage electrode 9 ′ shown in FIG. 3C can be formed.
【００２２】この後, 図３（ｄ）に示すように，通常の
工程で， Si3N4膜11を約100 Åの厚さに被覆しパターニ
ングして誘電体膜11' を形成し, 更に, 第２のポリSi膜
12を6,000Åの厚さに被覆しパターニングして対向電極1
2とし, キャパシタ13を完成する。After this, as shown in FIG. 3D, in a normal process, the Si 3 N 4 film 11 is coated to a thickness of about 100 Å and patterned to form a dielectric film 11 ′. , Second poly-Si film
Counter electrode 1 by coating 12 with a thickness of 6,000Å and patterning
Then, the capacitor 13 is completed.
【００２３】[0023]
【発明の効果】以上説明した様に，本発明によれば，エ
ッチングのマイクロローディング効果を用いることによ
り，１度のパターニングでスタック型キャパシタ表面の
凹凸と個々のキャパシタとを形成できるために，高集
積，微細パターンのＬＳＩにおける工程の短縮，特性向
上に寄与するところが大きい。As described above, according to the present invention, by using the micro-loading effect of etching, it is possible to form unevenness on the surface of the stack type capacitor and individual capacitors by one-time patterning. It greatly contributes to shortening the process and improving the characteristics of integrated and fine pattern LSIs.
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 パターンの疎密度とエッチング深さ[FIG. 2] Pattern sparse density and etching depth
【図３】 本発明の一実施例の説明図FIG. 3 is an explanatory diagram of an embodiment of the present invention.
【図４】 本発明の一実施例に用いたエッチング装置FIG. 4 is an etching apparatus used in an embodiment of the present invention.
【図５】 従来例の説明図FIG. 5 is an explanatory diagram of a conventional example.
１ 半導体基板 ２ 絶縁膜 ３ 第一の導電膜 ３' 蓄積電極 ４ レジスト膜 ４' 高密度凹凸パターン ５ 誘電体膜 ６ 第二の導電膜 ６' 対向電極 ７ Si基板 ８ SiO2膜 ９ 第１のポリSi膜 ９' 蓄積電極 10 レジスト膜 11 Si3N4膜 11' 誘電体膜 12 第２のポリSi膜 12 対向電極 13 キャパシタ 14 チャンバ 15 上部電極 16 下部電極 17 ＲＦ電源 18 ガス導入口 19 排気口 20 Si基板1 semiconductor substrate 2 insulating film 3 first conductive film 3'storage electrode 4 resist film 4'high density uneven pattern 5 dielectric film 6 second conductive film 6'counter electrode 7 Si substrate 8 SiO 2 film 9 first Poly-Si film 9'Storage electrode 10 Resist film 11 Si 3 N 4 film 11 'Dielectric film 12 Second poly-Si film 12 Counter electrode 13 Capacitor 14 Chamber 15 Upper electrode 16 Lower electrode 17 RF power supply 18 Gas inlet 19 Exhaust Mouth 20 Si substrate
Claims (1)
上に第一の導電膜(3) を形成する工程と, 該第一の導電膜(3) 上のキャパシタ形成領域上にレジス
ト膜(4) を用いて高密度凹凸パターン(4')をパターニン
グする工程と, 該レジスト膜(4) をマスクとし, マイクロローディング
効果を利用して, 該第一の導電膜(3) を途中までエッチ
ングしてキャパシタ形成領域上に蓄積電極(3')の凹凸パ
ターンを形成すると同時に, キャパシタ形成領域外の該
第一の導電膜(3) をエッチング除去して，蓄積電極(3')
を画定形成する工程と, 該第一の導電膜(3) 上の該レジスト膜(4) を除去する工
程と, パターニングされた該第一の導電膜(3) からなる蓄積電
極(3')上に誘電体膜(5) を被覆する工程と, 該半導体基板(1) 上に第二の導電膜(6) を形成し, パタ
ーニングして対向電極(6')とする工程とを含むことを特
徴とするキャパシタの製造方法。1. A semiconductor substrate (1) covered with an insulating film (2)
Forming a first conductive film (3) on the upper surface, and patterning a high-density concavo-convex pattern (4 ') using a resist film (4) on the capacitor formation region on the first conductive film (3) And the resist film (4) as a mask, the micro-loading effect is used to etch the first conductive film (3) halfway to form unevenness of the storage electrode (3 ′) on the capacitor formation region. At the same time as forming the pattern, the first conductive film (3) outside the capacitor formation region is removed by etching, and the storage electrode (3 ') is formed.
And a step of removing the resist film (4) on the first conductive film (3), and a storage electrode (3 ') made of the patterned first conductive film (3). And a step of forming a second conductive film (6) on the semiconductor substrate (1) and patterning it to form a counter electrode (6 ′). And a method for manufacturing a capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4248084A JPH0697386A (en) | 1992-09-17 | 1992-09-17 | Fabrication of capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4248084A JPH0697386A (en) | 1992-09-17 | 1992-09-17 | Fabrication of capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0697386A true JPH0697386A (en) | 1994-04-08 |
Family
ID=17172977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4248084A Withdrawn JPH0697386A (en) | 1992-09-17 | 1992-09-17 | Fabrication of capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0697386A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744853A (en) * | 1995-09-15 | 1998-04-28 | Chartered Semiconductor Manufacturing Pte Ltd | Three dimensional polysilicon capacitor for high density integrated circuit applications |
| KR19980050149A (en) * | 1996-12-20 | 1998-09-15 | 김영환 | Method for manufacturing storage electrode of semiconductor device |
| JP2004031950A (en) * | 2002-06-27 | 2004-01-29 | Samsung Electronics Co Ltd | Semiconductor memory element and manufacturing method thereof |
| JP2005303334A (en) * | 1997-04-18 | 2005-10-27 | Nippon Steel Corp | Manufacturing method of semiconductor device |
| KR100816533B1 (en) * | 2006-05-11 | 2008-03-26 | 박영진 | Multi layer capacitor device and multi layer varistor device and method for manufacturing the same |
| JP2011258763A (en) * | 2010-06-09 | 2011-12-22 | Lapis Semiconductor Co Ltd | Fuse structure of semiconductor device and method for manufacturing the same |
-
1992
- 1992-09-17 JP JP4248084A patent/JPH0697386A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744853A (en) * | 1995-09-15 | 1998-04-28 | Chartered Semiconductor Manufacturing Pte Ltd | Three dimensional polysilicon capacitor for high density integrated circuit applications |
| KR19980050149A (en) * | 1996-12-20 | 1998-09-15 | 김영환 | Method for manufacturing storage electrode of semiconductor device |
| JP2005303334A (en) * | 1997-04-18 | 2005-10-27 | Nippon Steel Corp | Manufacturing method of semiconductor device |
| JP2008182261A (en) * | 1997-04-18 | 2008-08-07 | Pegre Semiconductors Llc | Semiconductor device and method of manufacturing the same |
| JP2004031950A (en) * | 2002-06-27 | 2004-01-29 | Samsung Electronics Co Ltd | Semiconductor memory element and manufacturing method thereof |
| KR100816533B1 (en) * | 2006-05-11 | 2008-03-26 | 박영진 | Multi layer capacitor device and multi layer varistor device and method for manufacturing the same |
| JP2011258763A (en) * | 2010-06-09 | 2011-12-22 | Lapis Semiconductor Co Ltd | Fuse structure of semiconductor device and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3252780B2 (en) | Silicon layer etching method | |
| JPH11330245A (en) | Method for contact formation of semiconductor device | |
| JPH0818017A (en) | Capacitor preparation of semiconductor element | |
| JPH0697386A (en) | Fabrication of capacitor | |
| JPH11186127A (en) | Semiconductor device and manufacture thereof | |
| JP2695689B2 (en) | Etching method of multilayer interlayer insulating film | |
| JP3176311B2 (en) | Silicon layer etching method | |
| JPH0669351A (en) | Manufacture of contact of multilayer metal interconnection structure | |
| JPH0313744B2 (en) | ||
| KR100466192B1 (en) | Method for manufacturing semiconductor device | |
| JPH11330045A (en) | Method for etching laminated film of oxide film and silicon layer | |
| KR100525106B1 (en) | method for forming a storage node pattern in a semiconductor device | |
| KR100618679B1 (en) | Capacitor forming method | |
| JPH098007A (en) | Method for flattening insulation film | |
| JPH0766178A (en) | Fabrication of semiconductor device | |
| JPS63258020A (en) | Formation of element isolation pattern | |
| JPH03101229A (en) | Manufacture of semiconductor integrated circuit device | |
| JP2694777B2 (en) | Method for manufacturing semiconductor device | |
| JP2787903B2 (en) | Method for manufacturing semiconductor device | |
| JPH03268346A (en) | Semiconductor device and manufacture thereof | |
| JPH0220141B2 (en) | ||
| JPH08181115A (en) | Method of manufacturing integrated circuit | |
| JPH05114713A (en) | Semiconductor device and manufacture thereof | |
| JPH07263571A (en) | Semiconductor device and manufacture of semiconductor device | |
| JPH06196627A (en) | Semiconductor element and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19991130 |