JPH0697339A - Frame for array of electronic component - Google Patents
Frame for array of electronic componentInfo
- Publication number
- JPH0697339A JPH0697339A JP4246420A JP24642092A JPH0697339A JP H0697339 A JPH0697339 A JP H0697339A JP 4246420 A JP4246420 A JP 4246420A JP 24642092 A JP24642092 A JP 24642092A JP H0697339 A JPH0697339 A JP H0697339A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- array
- islands
- island
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ダイオード、トランジ
スタ等の電子部品（半導体チップ）のアレイを作製する
場合に使用するアレイ用フレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array frame used for producing an array of electronic parts (semiconductor chips) such as diodes and transistors.
【０００２】[0002]
【従来の技術】ダイオード、トランジスタ等の同一の電
子部品のアレイ、又は数種類の電子部品を組み合わせた
複合アレイを樹脂モールドしてなるパッケージ製品があ
る。このパッケージ製品のうち、少なくとも４ピン以上
を有し、ピンが対向配置されたものを作製する場合、半
導体チップを載せるためのチップマウント用アイランド
や、ワイヤボンディングするための配線用アイランドが
形成されたフレームが使用される。2. Description of the Related Art There are packaged products in which an array of the same electronic parts such as diodes and transistors, or a composite array in which several kinds of electronic parts are combined is resin-molded. In the case where a package product having at least 4 pins or more and having pins arranged facing each other is manufactured, a chip mounting island for mounting a semiconductor chip and a wiring island for wire bonding are formed. Frames are used.
【０００３】このフレームは、例えば図８に示すよう
に、フレーム１００の両側からマウント用アイランド１
０１と配線用アイランド１０２が一定間隔を置いて各対
毎に相対するように延び、双方のアイランド１０１，１
０２の対向端部がパッド１０３，１０４になっている。
この例では、アイランド１０１のパッド１０３上に半導
体チップを載せ、所定の配線に従ってチップをアイラン
ド１０２のパッド１０４にワイヤボンディングすること
により、半導体チップをフレーム上に実装している。勿
論、チップの実装後は、アイランド９１，９２はフレー
ム１００から切り離される。As shown in FIG. 8, for example, this frame is mounted on the mounting island 1 from both sides of the frame 100.
01 and the wiring island 102 are spaced apart from each other and extend so as to face each other in each pair.
Opposite ends of 02 are pads 103 and 104.
In this example, a semiconductor chip is mounted on the pad 103 of the island 101, and the chip is wire-bonded to the pad 104 of the island 102 according to a predetermined wiring to mount the semiconductor chip on the frame. Of course, the islands 91 and 92 are separated from the frame 100 after the chip is mounted.
【０００４】このようなフレームでは、チップマウント
用及び配線用のアイランドが役割別に構成されており、
このためパッドを含めたアイランドの形状も実装する電
子部品やその種類、及び配線の仕方に応じて図８の如く
様々である。そして、パッケージ製品に応じて設計され
たフレームを用いることで、各機種毎のパッケージにお
いて省スペース化を実現している。In such a frame, islands for chip mounting and wiring are constructed by role.
Therefore, the shape of the island including the pad also varies as shown in FIG. 8 depending on the electronic component to be mounted, its type, and the wiring method. By using a frame designed according to the packaged product, space saving is realized in the package for each model.
【０００５】[0005]
【発明が解決しようとする課題】ところで、上記のよう
なフレームでは、実装する電子部品、延いては機種毎に
アイランドの形状を一定に決めてあるため、異なる種類
の電子部品を実装したり、配線の仕方を変えたりしよう
とすると、実装不可能であったり、電子部品の配線に自
由度がなかったりする。このため、例えば２個のダイオ
ードＤ１，Ｄ２をアレイ状に配する４ピン構造のパッケ
ージ製品であって、図９の（ａ）に示すようにダイオー
ドＤ１，Ｄ２を同方向に配線したアレイ、又は図９の
（ｂ）のように異方向に配線したアレイを作製する場
合、前記した如くマウント用と配線用でアイランドの大
きさ・形状が決まっているため、各々の場合でそれに適
したアイランドを有するフレームを用意しなければなら
ない。By the way, in the frame as described above, since the shape of the electronic parts to be mounted, and hence the shape of the island is fixed for each model, different types of electronic parts can be mounted, If you try to change the wiring method, it may not be possible to mount it or you may not have the freedom to wire the electronic components. Therefore, for example, it is a package product having a 4-pin structure in which two diodes D1 and D2 are arranged in an array, and an array in which the diodes D1 and D2 are wired in the same direction as shown in FIG. 9A, or When manufacturing an array in which wirings are provided in different directions as shown in FIG. 9B, the size and shape of the islands for mounting and wiring are determined as described above. You must prepare the frame you have.
【０００６】しかしながら、特に少量多品種の製品を得
るには、同一フレームを共用することが難しいため、フ
レームの種類がどうしても多くなり、それだけフレーム
の管理に非常に手間が掛かることになる。従って、本発
明の目的は、上記問題点に鑑み、実装する電子部品の種
類や数、及び配線の仕方に依らず、できるだけ多数のア
レイ構造に共用できる電子部品のアレイ用フレームを提
供することにある。However, since it is difficult to share the same frame in order to obtain a large number of products in small quantities, the number of types of frames is inevitably increased, and the management of the frames is very troublesome. Therefore, in view of the above problems, an object of the present invention is to provide an array frame for electronic components that can be shared by as many array structures as possible, regardless of the type and number of electronic components to be mounted and the wiring method. is there.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するため
に、本発明の電子部品のアレイ用フレームは、少なくと
も４ピン以上を有し、ピンが対向配置されたフラットパ
ッケージ用のフレームにおいて、各ピンを構成するアイ
ランドの形状を同一形、対称形又は類似形に形成してな
ることを特徴とする。In order to achieve the above object, an electronic component array frame according to the present invention has at least 4 pins or more. It is characterized in that the islands forming the pins are formed in the same shape, symmetrical shape or similar shape.
【０００８】上記のようにフレームを構成すること、即
ちフレームのアイランド形状を統一することにより、チ
ップマウント用及び配線用を問わず、どのアイランドに
もチップを載せることができると同時に、どのアイラン
ドにもワイヤボンディングを施すことができる。従っ
て、フレームの汎用性が高まり、フレームの種類が大幅
に少なくて済み、フレームの管理が容易となり、少量多
品種のパッケージ製品にとって好都合となる。By constructing the frame as described above, that is, by unifying the island shape of the frame, chips can be mounted on any island regardless of whether they are for chip mounting or wiring, and at the same time, for which island. Can also be wire bonded. Therefore, the versatility of the frame is increased, the number of types of the frame is significantly reduced, the frame is easily managed, and it is convenient for a small amount and a wide variety of package products.
【０００９】なお、フレームに設けるアイランドの大き
さに関して付言すると、パッケージに収容することが可
能な最大寸法の半導体チップを載せることができるよう
に、アイランドの最小寸法を設定することが好ましい。
こうすることで、パッケージの大きさを特に変えなくて
も、大きさが一定のパッケージ内にサイズの異なる半導
体チップを収めることが可能となり、フレームの汎用性
が更に高くなる。In addition, regarding the size of the island provided in the frame, it is preferable to set the minimum size of the island so that the semiconductor chip having the maximum size that can be accommodated in the package can be mounted.
By doing so, it becomes possible to accommodate semiconductor chips of different sizes in a package of a constant size without particularly changing the size of the package, and the versatility of the frame is further enhanced.
【００１０】[0010]
【実施例】以下、本発明の電子部品のアレイ用フレーム
を実施例に基づいて説明する。図１に、一実施例に係る
フレームを用いてアイランドに半導体チップを載せてワ
イヤボンディングした６ピン構造のパッケージ製品の平
面図を示す。即ち、一定間隔を置いて相対する３対のア
イランド１０，１１，１２，１３，１４，１５は、それ
ぞれ相対端部に同じ大きさで四角形のパッド１０ａ，１
１ａ，１２ａ，１３ａ，１４ａ，１５ａを有し、アイラ
ンド１０，１２，１４のパッド１０ａ，１２ａ，１４ａ
上にそれぞれダイオードチップ２１，２２，２３がダイ
ボンディングされ、各チップ２１，２２，２３と対応ア
イランド１１，１３，１５のパッド１１ａ，１３ａ，１
５ａとがＡｕワイヤ３１，３２，３３でワイヤボンディ
ングされている。更に、各フレーム１０〜１５のパッド
１０ａ〜１５ａはＡｕワイヤ３１，３２，３３を含めて
パッケージとなる樹脂モールド４０で封止されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An electronic component array frame of the present invention will be described below based on embodiments. FIG. 1 is a plan view of a package product having a 6-pin structure in which a semiconductor chip is placed on an island and wire-bonded using a frame according to an embodiment. That is, the three pairs of islands 10, 11, 12, 13, 14, 15 that face each other at a constant interval have square pads 10a, 1 of the same size at their relative ends.
1a, 12a, 13a, 14a, 15a, and pads 10a, 12a, 14a of the islands 10, 12, 14
The diode chips 21, 22, and 23 are die-bonded on the respective chips, and pads 11a, 13a, 1 of the respective chips 21, 22, 23 and the corresponding islands 11, 13, 15 are die-bonded.
5a is wire-bonded with Au wires 31, 32, 33. Further, the pads 10a to 15a of each of the frames 10 to 15 including the Au wires 31, 32, and 33 are sealed with a resin mold 40 that serves as a package.
【００１１】このような６ピン構造のパッケージ製品の
外観図を図６（平面図）及び図７（図６の矢視Ａから見
た側面図）に示す。ここで、参考までにこの製品の寸法
例を示すと、横の長さａが２．９ｍｍ、縦の長さｂが
１．６ｍｍ、高さｃが１．１ｍｍである。上記のような
製品は、一般に図５に示すような連続フレーム９０を用
いて作製される。この連続フレーム９０は、上記の如き
３対のアイランド１０〜１５が等間隔で並設されると共
に、フレームの両端縁側に位置決め及び送り用の孔９
１，９２が一定間隔で穿設されたものである。このフレ
ーム９０にて、前記のようにアイランド１０，１２，１
４のパッド上にダイオードチップをダイボンディング
し、各チップとアイランド１１，１３，１５のパッドと
をワイヤボンディングし、更にパッド領域に樹脂モール
ドを施した後、アイランド１０〜１５をフレーム９０か
ら切り離すことにより、図１に示したようなパッケージ
製品が得られる。An external view of such a package product having a 6-pin structure is shown in FIG. 6 (plan view) and FIG. 7 (side view seen from the arrow A in FIG. 6). Here, as an example of the dimensions of this product for reference, the horizontal length a is 2.9 mm, the vertical length b is 1.6 mm, and the height c is 1.1 mm. Products such as those described above are typically made using a continuous frame 90 as shown in FIG. In the continuous frame 90, the above-mentioned three pairs of islands 10 to 15 are arranged in parallel at equal intervals, and the holes 9 for positioning and feeding are provided on both end edges of the frame.
1, 92 are provided at regular intervals. In this frame 90, as described above, the islands 10, 12, 1
Die-bonding the diode chip on the pad of No. 4 and wire-bonding each chip to the pad of the islands 11, 13 and 15 and further resin-molding the pad area, and then separating the islands 10 to 15 from the frame 90. As a result, a packaged product as shown in FIG. 1 is obtained.
【００１２】上記のようなフレーム９０を使用すれば、
例えば図２の（ａ）に示すようにダイオード２１，２３
を同じ方向に、ダイオード２２を反対方向に配線したダ
イオードアレイや、図２の（ｂ）のような全てのダイオ
ード２１，２２，２３を同じ方向に配線したダイオード
アレイを、アレイ構造に依らず同一フレームで製作する
ことができる。Using the frame 90 as described above,
For example, as shown in FIG.
In the same direction and the diode array in which the diodes 22 are wired in the opposite direction, and the diode array in which all the diodes 21, 22, and 23 are wired in the same direction as shown in FIG. 2B are the same regardless of the array structure. It can be made with a frame.
【００１３】更に別実施例を図３に示す。この実施例の
パッケージ製品では、フレーム上に実装する半導体チッ
プがＮＰＮ形トランジスタ、スイッチングダイオード、
ツェナーダイオードであり、異種の３個のチップを設け
てある。使用するフレームは図５に示すものと全く同じ
で、アイランド５１，５３，５４のパッド５１ａ，５３
ａ，５４ａ上にそれぞれＮＰＮ形トランジスタ６１、ス
イッチングダイオード６２、ツェナーダイオード６３が
ダイボンディングされている。トランジスタ６１のエミ
ッタはアイランド５０のパッド５０ａにＡｕワイヤ７１
で、トランジスタ６１のベースはアイランド５２のパッ
ド５２ａにＡｕワイヤ７２でワイヤボンディングされる
と共に、ダイオード６２，６３はそれぞれ対応アイラン
ド５２，５５のパッド５２ａ，５５ａにＡｕワイヤ７
３，７４でワイヤボンディングされている。そして、樹
脂モールド８０でパッド全体が被覆され、パッケージ製
品が構成されている。なお、この実施例の配線図を図４
に示す。又、製品の外観は図６及び図７に示す通りであ
る。Another embodiment is shown in FIG. In the package product of this embodiment, the semiconductor chip mounted on the frame is an NPN transistor, a switching diode,
It is a Zener diode, and is provided with three different types of chips. The frame used is exactly the same as that shown in FIG. 5, and the pads 51a, 53 of the islands 51, 53, 54 are used.
An NPN transistor 61, a switching diode 62, and a Zener diode 63 are die-bonded on a and 54a, respectively. The emitter of the transistor 61 connects the pad 50a of the island 50 to the Au wire 71.
The base of the transistor 61 is wire-bonded to the pad 52a of the island 52 with the Au wire 72, and the diodes 62 and 63 are connected to the pads 52a and 55a of the corresponding islands 52 and 55 by the Au wire 7 respectively.
Wire bonding is performed at 3,74. The entire pad is covered with the resin mold 80 to form a packaged product. The wiring diagram of this embodiment is shown in FIG.
Shown in. The appearance of the product is as shown in FIGS. 6 and 7.
【００１４】これらの実施例から分かるように、各対の
アイランドが相対し、特にアイランドのパッドが同一形
状（四角形）であるため、同一の半導体チップのアレイ
は勿論のこと、たとえ異なる種類の半導体チップのアレ
イであっても、チップマウント用と配線用の区別無く、
どのアイランドのパッドにチップを載せても、またどの
ように配線しても良く、アイランドを有するフレームの
汎用性が機種に依らず大幅に向上する。As can be seen from these examples, since the islands of each pair are opposed to each other, and in particular, the pads of the islands have the same shape (rectangular shape), the array of the same semiconductor chip as well as the semiconductors of different types can be used. Even if it is an array of chips, there is no distinction between chip mount and wiring.
The chip may be mounted on any island pad or may be wired in any way, and the versatility of the frame having the island is significantly improved regardless of the model.
【００１５】上記実施例は、いずれも単なる一例に過ぎ
ず、種々の変更が可能である。例えば、上記実施例は６
ピンのアレイ構造に関するが、４ピンでも或いは８ピン
以上のアレイ構造でも同様に半導体チップをフレームの
アイランド上にかなりの自由度で搭載し配線することが
できる。又、特にアイランドのパッドの形状は、四角形
の同一形状に限定されることはなく、対称形や類似形で
あっても同等の効果が得られる。The above embodiments are merely examples, and various modifications can be made. For example, the above embodiment has 6
Regarding the pin array structure, a semiconductor chip can be mounted and wired on the island of the frame with a considerable degree of freedom in the same manner even with an array structure of 4 pins or 8 pins or more. In addition, the shape of the pad of the island is not limited to the same rectangular shape, and the same effect can be obtained even if it is symmetrical or similar.
【００１６】[0016]
【発明の効果】以上説明したように、本発明の電子部品
のアレイ用フレームは、相対する全てのアイランドの形
状を同一形、対称形又は類似形に形成してなるため、下
記の効果を有する。 （１）実装する電子部品（半導体チップ）の種類や数、
及び配線の仕方に依らず、同一フレームを様々なアレイ
構造に共用でき、少量多品種の製造が容易になる。 （２）同一フレームで機種のバリエーションが豊富にな
る。 （３）電子部品のダイボンディングやワイヤボンディン
グを比較的自由に行うことができるため、機種の変更が
し易くなる。 （４）アイランドの許容寸法以内の大きさの半導体チッ
プであれば、任意のアイランドに任意のチップをダイボ
ンディングできるため、非常に多機種のアレイを形成で
きる。As described above, the array frame of the electronic component of the present invention has the following effects because all the opposing islands are formed in the same shape, symmetrical shape or similar shape. . (1) Type and number of electronic components (semiconductor chips) to be mounted,
In addition, the same frame can be commonly used for various array structures regardless of the wiring method, which facilitates the production of a large number of small quantities. (2) A wide variety of models with the same frame. (3) Since die bonding and wire bonding of electronic components can be performed relatively freely, it is easy to change the model. (4) As long as the semiconductor chip has a size within the allowable dimension of the island, any chip can be die-bonded to any island, so that an array of a great variety of models can be formed.
【図１】本発明の一実施例に係るフレームを用いて作製
したパッケージ製品の平面図である。FIG. 1 is a plan view of a packaged product manufactured using a frame according to an embodiment of the present invention.
【図２】図１に示す製品における電子部品のアレイの仕
方を説明する配線図である。FIG. 2 is a wiring diagram illustrating a method of arraying electronic components in the product shown in FIG.
【図３】図１に示す製品と同じフレームを用いて作製し
た別実施例に係るパッケージ製品の平面図である。FIG. 3 is a plan view of a packaged product according to another embodiment manufactured by using the same frame as the product shown in FIG.
【図４】図３に示す製品における電子部品のアレイの配
線図である。FIG. 4 is a wiring diagram of an array of electronic components in the product shown in FIG.
【図５】図１及び図３に示す製品に使用したフレームを
示す部分平面図である。5 is a partial plan view showing a frame used in the product shown in FIGS. 1 and 3. FIG.
【図６】図１及び図３に示す製品の平面図である。6 is a plan view of the product shown in FIGS. 1 and 3. FIG.
【図７】図６に示す製品を矢視Ａから見た側面図であ
る。FIG. 7 is a side view of the product shown in FIG. 6 viewed from an arrow A.
【図８】従来例に係るフレームの部分平面図である。FIG. 8 is a partial plan view of a frame according to a conventional example.
【図９】２個の電子部品（ダイオード）のアレイの仕方
を説明する配線図である。FIG. 9 is a wiring diagram illustrating a method of arraying two electronic components (diodes).
１０〜１５，５０〜５５ アイランド １０ａ〜１５ａ パッド ５０ａ〜５５ａ パッド ２１〜２３，６１〜６３ 半導体チップ（電子部品） ３１〜３３，７１〜７４ Ａｕワイヤ ４０，８０ 樹脂モールド ９０ フレーム 10-15, 50-55 Island 10a-15a Pad 50a-55a Pad 21-23, 61-63 Semiconductor chip (electronic component) 31-33, 71-74 Au wire 40,80 Resin mold 90 Frame
Claims (1)
配置されたフラットパッケージ用のフレームにおいて、 各ピンを構成するアイランドの形状を同一形、対称形又
は類似形に形成してなることを特徴とする電子部品のア
レイ用フレーム。1. In a frame for a flat package having at least 4 pins and facing each other, the islands forming each pin are formed in the same shape, symmetrical shape or similar shape. A frame for an array of characteristic electronic components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4246420A JPH0697339A (en) | 1992-09-16 | 1992-09-16 | Frame for array of electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4246420A JPH0697339A (en) | 1992-09-16 | 1992-09-16 | Frame for array of electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0697339A true JPH0697339A (en) | 1994-04-08 |
Family
ID=17148218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4246420A Pending JPH0697339A (en) | 1992-09-16 | 1992-09-16 | Frame for array of electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0697339A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3721025A1 (en) * | 1986-07-01 | 1988-01-14 | Diesel Kiki Co | FUEL INJECTION DEVICE |
| JP2012099842A (en) * | 2011-12-29 | 2012-05-24 | Mitsubishi Electric Corp | Semiconductor module |
-
1992
- 1992-09-16 JP JP4246420A patent/JPH0697339A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3721025A1 (en) * | 1986-07-01 | 1988-01-14 | Diesel Kiki Co | FUEL INJECTION DEVICE |
| JP2012099842A (en) * | 2011-12-29 | 2012-05-24 | Mitsubishi Electric Corp | Semiconductor module |
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