JPH069220B2 - Multilayer wiring - Google Patents
Multilayer wiringInfo
- Publication number
- JPH069220B2 JPH069220B2 JP60199711A JP19971185A JPH069220B2 JP H069220 B2 JPH069220 B2 JP H069220B2 JP 60199711 A JP60199711 A JP 60199711A JP 19971185 A JP19971185 A JP 19971185A JP H069220 B2 JPH069220 B2 JP H069220B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal film
- multilayer wiring
- metal
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は集積回路の高密度化，高速化を図る上で重要な
多層配線に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring which is important for increasing the density and speed of integrated circuits.
従来の技術 近年、多層配線は集積回路の高密度化，高速化を図る上
で重要な技術になっており、歩留りを決める上でも重要
な技術となっている。液晶ディスプレイに用いられる薄
膜トランジスタアレイの場合にも、層間絶縁膜をはさん
でなる第１の配線電極と第２の配線電極をスルーホール
を介してコンタクトさせ配線抵抗の低減、断線箇所の修
復などを行うという多層配線技術が利用されている。2. Description of the Related Art In recent years, multilayer wiring has become an important technology for increasing the density and speed of integrated circuits, and also for determining the yield. Also in the case of a thin film transistor array used for a liquid crystal display, the first wiring electrode and the second wiring electrode sandwiching the interlayer insulating film are brought into contact with each other through the through hole to reduce the wiring resistance and to repair the broken portion. The multi-layer wiring technology of performing is used.
以下図面を参照しながら、上述した従来の多層配線の一
例について説明する。An example of the above-described conventional multilayer wiring will be described below with reference to the drawings.
第２図は従来の多層配線の断面図を示すものである。第
２図において、１は絶縁性基板（または、基板上の絶縁
性膜）、２は第１の金属膜、３は絶縁性膜、５は第２の
金属膜である。絶縁性基板１の上に第１の金属膜を形成
およびパターニングし、絶縁性膜３を形成した後、パタ
ーニングしてスルーホールを形成し、その上に第２の金
属膜５を形成しパターニングを行う。一例として、液晶
ディスプレイ用の薄膜トランジスタアレイの場合、１は
ガラスまたはSiO2被膜付きガラス、２はＣｒ膜、３はプ
ラズマＣＶＤなどによって作られるSiNx膜、５はAl膜な
どである。Ｃｒ膜を薄膜トランジスタアレイのゲート電
極として用いる場合、信号の遅延時間を少くするには配
線抵抗が低いほうが好ましいので、第２図のような多層
配線により、抵抗の高いＣｒ膜２を抵抗の低いＡｌ膜５
で補強することが行われる。また、Ｃｒ膜がスルーホー
ル間で断線している場合、Ａｌ膜の補強による断線修復
作用もある。（例えば、「最新ＬＳＩプロセス技術」工
場調査会発行３６３ページ〜３７２ページ、あるいは、
「日経エレクトロニクス」１９８２年１２月２０日号，
１０５〜１７９ページ。） 発明が解決しようとする問題点 しかしながら上記のような構成では、第１の金属膜と第
２の金属膜のコンタクトが十分低い値のコンタクト抵抗
を持ち、安定なものとなるとは限らない。絶縁膜にスル
ーホールを開口するときに絶縁膜と第１の金属膜との中
間生成物がエッチングされずにスルーホール下部に残存
したり、第１の金属膜の表面が酸化等により絶縁性にな
ったりする場合があるからである。FIG. 2 shows a sectional view of a conventional multilayer wiring. In FIG. 2, 1 is an insulating substrate (or an insulating film on the substrate), 2 is a first metal film, 3 is an insulating film, and 5 is a second metal film. A first metal film is formed and patterned on the insulating substrate 1, an insulating film 3 is formed, and then a through hole is formed by patterning, and a second metal film 5 is formed on the through hole and patterned. To do. As an example, in the case of a thin film transistor array for a liquid crystal display, 1 is glass or glass with a SiO 2 coating, 2 is a Cr film, 3 is a SiNx film formed by plasma CVD or the like, and 5 is an Al film. When the Cr film is used as the gate electrode of the thin film transistor array, it is preferable that the wiring resistance be low in order to reduce the signal delay time. Therefore, by using the multilayer wiring as shown in FIG. Membrane 5
Is reinforced with. Further, when the Cr film is broken between the through holes, there is also a function of repairing the break by reinforcing the Al film. (For example, “Latest LSI Process Technology” published by the Factory Study Group, pages 363 to 372, or
Nikkei Electronics, December 20, 1982 issue,
Pages 105-179. ) PROBLEMS TO BE SOLVED BY THE INVENTION However, in the above-mentioned configuration, the contact between the first metal film and the second metal film does not always have a sufficiently low value of contact resistance and becomes stable. When the through hole is opened in the insulating film, the intermediate product between the insulating film and the first metal film is not etched and remains in the lower portion of the through hole, or the surface of the first metal film becomes insulating due to oxidation or the like. This is because there is a possibility that
本発明は上記問題点に鑑み、安定で信頼性が高く、コン
タクト抵抗の低い多層配線を提供するものである。In view of the above problems, the present invention provides a multilayer wiring which is stable, highly reliable, and has low contact resistance.
問題点を解決するための手段 上記問題点を解決するために本発明の多層配線は、第２
の金属膜がＴｉあるいはＺｒよりなる膜を第１の金属膜
への接触膜とするという構成を備えたものである。Means for Solving the Problems In order to solve the above problems, the multilayer wiring of the present invention is
The metal film of No. 1 is a film made of Ti or Zr as a contact film with the first metal film.
作用 本発明は上記した構成によって、活性の強いＴｉあるい
はＺｒが金属膜の間に介在しているため、金属膜間のオ
ーム性コンタクトを阻害するスルーホール下部の残存膜
や下層の金属膜表面に存在する酸化膜などが少々残って
いても、ＴｉやＺｒが化合物として取り込んでしまうた
め、安定で信頼性の高い、低いコンタクト抵抗の多層配
線を実現できる。Effect The present invention has the above-described structure, in which highly active Ti or Zr is present between the metal films, so that the residual film under the through hole and the surface of the lower metal film that obstruct the ohmic contact between the metal films. Even if some of the existing oxide film remains, Ti and Zr are taken in as compounds, so that stable and highly reliable multilayer wiring with low contact resistance can be realized.
実施例 以下本発明の一実施例の多層配線について、図面を参照
しながら説明する。Example A multilayer wiring according to an example of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例における多層配線の断面図を
示すものである。第１図において１,２,３および５は第
２図の従来例の場合と同様のものである。４はＴｉ，あ
るいはＺｒよりなる金属膜である。ＴｉあるいはＺｒよ
りなる膜は通常のスパッタ蒸着，電子ビーム加熱蒸着な
どによって容易に得られる。実施例では、絶縁性基板と
してガラス，第１の金属膜としてＣｒ膜，層間絶縁膜と
して、プラズマＣＶＤ法で作成したSiNx膜，第２の金属
膜としてＴｉ，Ａｌの２層膜を用いている。FIG. 1 shows a cross-sectional view of a multi-layer wiring in one embodiment of the present invention. In FIG. 1, 1, 2, 3 and 5 are the same as those in the conventional example of FIG. 4 is a metal film made of Ti or Zr. The film made of Ti or Zr can be easily obtained by ordinary sputter deposition, electron beam heating deposition, or the like. In the embodiment, glass is used as the insulating substrate, Cr film is used as the first metal film, SiNx film is formed by plasma CVD method as the interlayer insulating film, and two-layer film of Ti and Al is used as the second metal film. .
第３図は本発明の多層配線の一実施例と、従来例の場合
のスルーホール部でのコンタクト抵抗値の熱処理温度依
存性を示すものである。第３図において、６は従来例の
構造のＣｒ−Ａｌコンタクトの場合、７は構造は前記１
と同様のＣｒ−Ａｌコンタクトであるが、Ａｌ蒸着前に
Ｏ２プラズマによるスパッタクリーニングを施した場
合、８は本実施例の場合であり、Ｃｒ−Ｔｉ−Ａｌコン
タクト構造の特性を示している。スルーホールの大きさ
は上記３つの場合、全て同一形状であり、３０μｍ×６
０μｍである。FIG. 3 shows an embodiment of the multilayer wiring of the present invention and the heat treatment temperature dependence of the contact resistance value in the through hole portion in the case of the conventional example. In FIG. 3, 6 is a Cr-Al contact having the structure of the conventional example, and 7 is the structure described in 1 above.
The Cr-Al contact is the same as the above, but when sputter cleaning is performed by O 2 plasma before Al vapor deposition, 8 is the case of this embodiment, which shows the characteristics of the Cr-Ti-Al contact structure. In the above three cases, the size of the through hole is the same, and the size is 30 μm × 6.
It is 0 μm.
第３図より明らかなように本実施例によれば、ＣｒとＡ
ｌの間にＴｉを介在させることにより、Ｔｉのない場合
に比べて低いコンタクト抵抗と、コンタクト特性の優れ
た耐熱安定性を得ることができる。As is clear from FIG. 3, according to this embodiment, Cr and A
By interposing Ti between l, it is possible to obtain a contact resistance lower than that in the case where Ti is not contained and a heat resistance stability excellent in contact characteristics.
次に本発明の第２の実施例では第１の実施例で用いたＴ
ｉのかわりに、Ｚｒを用いる。この場合も第１の実施例
と同様の効果が得られる。Next, in the second embodiment of the present invention, the T used in the first embodiment is used.
Zr is used instead of i. Also in this case, the same effect as that of the first embodiment can be obtained.
発明の効果 以上のように本発明は、第１の金属膜への接触膜として
ＴｉあるいはＺｒよりなる膜を用いることにより、低い
コンタクト抵抗とコンタクト特性の耐熱安定性を得るこ
とができる。さらに、Ａｌ膜を作成する場合、下地膜と
してＴｉ膜があると、下地膜がSiN膜やSiO2膜の場合に
比べてＡｌ膜表面のヒロック形成が抑制さえ表面平坦性
が良くなるという効果もある。EFFECTS OF THE INVENTION As described above, according to the present invention, low contact resistance and heat stability of contact characteristics can be obtained by using a film made of Ti or Zr as a contact film for the first metal film. Further, when an Al film is formed, if a Ti film is used as a base film, the hillock formation on the surface of the Al film is suppressed and the surface flatness is improved as compared with the case where the base film is a SiN film or a SiO 2 film. is there.
第１図は本発明の実施例における多層配線の断面図、第
２図は従来例の場合の多層配線の断面図、第３図は本発
明の実施例と従来例の場合でのスルーホール部でのコン
タクト抵抗の熱処理温度依存性を示す特性図である。 １……絶縁性基板、２……第１の金属膜、３……絶縁性
膜、４……ＴｉあるいはＺｒよりなる金属膜、５……金
属膜。FIG. 1 is a cross-sectional view of the multilayer wiring in the embodiment of the present invention, FIG. 2 is a cross-sectional view of the multilayer wiring in the case of the conventional example, and FIG. 3 is a through hole portion in the embodiment of the present invention and the conventional example. 6 is a characteristic diagram showing the heat treatment temperature dependence of the contact resistance in FIG. 1 ... Insulating substrate, 2 ... First metal film, 3 ... Insulating film, 4 ... Metal film made of Ti or Zr, 5 ... Metal film.
Claims (3)
あるＣｒ膜と上記絶縁性基板上に形成された絶縁性膜と
を備え、前記絶縁性膜に開口したスルーホールを介して
上記第１の金属膜上に第２の金属膜を備え、上記第２の
金属膜がＴｉあるいはＺｒよりなる膜を上記第１の金属
膜への接触膜とする多層金属膜である多層配線。1. A Cr film, which is a first metal film formed on an insulating substrate, and an insulating film formed on the insulating substrate, and a through hole opened in the insulating film. And a second metal film on the first metal film, wherein the second metal film is a multilayer metal film in which a film made of Ti or Zr is a contact film to the first metal film. .
ｉ，Ａｌの２層膜あるいはＺｒ，Ａｌの２層膜である特
許請求の範囲第１項記載の多層配線。2. An insulating film is SiNx and a second metal film is Tn.
The multilayer wiring according to claim 1, which is a two-layer film of i, Al or a two-layer film of Zr, Al.
ｒを用いることを特徴とする特許請求の範囲第１項また
は第２項記載の多層配線。3. A gate electrode of a thin film transistor array having C
The multi-layer wiring according to claim 1 or 2, wherein r is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60199711A JPH069220B2 (en) | 1985-09-10 | 1985-09-10 | Multilayer wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60199711A JPH069220B2 (en) | 1985-09-10 | 1985-09-10 | Multilayer wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6260240A JPS6260240A (en) | 1987-03-16 |
| JPH069220B2 true JPH069220B2 (en) | 1994-02-02 |
Family
ID=16412336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60199711A Expired - Lifetime JPH069220B2 (en) | 1985-09-10 | 1985-09-10 | Multilayer wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH069220B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6482547A (en) * | 1987-09-24 | 1989-03-28 | Tadahiro Omi | Semiconductor device |
| US4828356A (en) * | 1987-12-22 | 1989-05-09 | Hughes Aircraft Company | Method for fabrication of low efficiency diffraction gratings and product obtained thereby |
| JPH01287625A (en) * | 1988-05-16 | 1989-11-20 | Seikosha Co Ltd | Top stagger type amorphous silicon thin-film transistor array |
| US5316974A (en) * | 1988-12-19 | 1994-05-31 | Texas Instruments Incorporated | Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT979264B (en) * | 1973-02-20 | 1974-09-30 | Nuovo Pignone Spa | PROCEDURE AND DEVICE FOR HANDLING PIECES OF TES SUTO DURING AUTOMATIC PROCESSING |
| JPS5365088A (en) * | 1976-11-22 | 1978-06-10 | Nec Corp | Semiconductor device |
| JPS58204558A (en) * | 1982-05-25 | 1983-11-29 | Nec Corp | Wiring method |
-
1985
- 1985-09-10 JP JP60199711A patent/JPH069220B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6260240A (en) | 1987-03-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |