JPH0686560A - Self-excited inverter - Google Patents
Self-excited inverterInfo
- Publication number
- JPH0686560A JPH0686560A JP4234007A JP23400792A JPH0686560A JP H0686560 A JPH0686560 A JP H0686560A JP 4234007 A JP4234007 A JP 4234007A JP 23400792 A JP23400792 A JP 23400792A JP H0686560 A JPH0686560 A JP H0686560A
- Authority
- JP
- Japan
- Prior art keywords
- output
- self
- loop filter
- excited inverter
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Supply And Distribution Of Alternating Current (AREA)
- Inverter Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、自励式インバータに係
り、特に連系する交流系統との同期検出回路を改良した
自励式インバータに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-excited inverter, and more particularly to a self-excited inverter having an improved synchronous detection circuit with an interconnected AC system.
【0002】[0002]
【従来の技術】図3は、交流系統と連系されている従来
の自励式インバータの一例を示す主回路単線結線図であ
る。図3において、21は交流系統、22は自励式インバー
タ、23は自励式インバータ22と交流系統21を接続する遮
断器、24は交流系統21と自励式インバータ22に接続され
た負荷、25は自励式インバータの制御装置、26は自励式
インバータの制御装置25に組み込まれた同期検出回路、
27は同期検出回路26に対して交流系統21に同期させるた
めの同期信号を検出する計器用変圧器を示す。2. Description of the Related Art FIG. 3 is a main circuit single wire connection diagram showing an example of a conventional self-exciting inverter connected to an AC system. In FIG. 3, 21 is an AC system, 22 is a self-excited inverter, 23 is a circuit breaker that connects the self-excited inverter 22 and the AC system 21, 24 is a load connected to the AC system 21 and the self-excited inverter 22, and 25 is a self-excited load. Excitation-type inverter control device, 26 is a synchronization detection circuit incorporated in self-excitation-type inverter control device 25,
Reference numeral 27 denotes an instrument transformer that detects a synchronization signal for synchronizing the alternating current system 21 with the synchronization detection circuit 26.
【0003】図1において、交流系統21からの電力の供
給が喪失した場合には、それまでこの交流系統21に接続
されていた負荷24への電力の供給を維持するために、遮
断器23を開くとともに、自励式インバータ22から単独で
負荷24に電力を供給する。その後、交流系統21の電源が
復帰すると、自励式インバータ22の出力電圧の周波数を
同期検出回路26で再び交流系統21の周波数に同期させ、
遮断器23を投入して自励式インバータ22と交流系統21を
接続し、この交流系統21と自励式インバータ22を並列で
運転して負荷24に電力を供給する。以下、自励式インバ
ータ22が単独で負荷24に電力を供給している状態を単独
運転、交流系統21と自励式インバータ22を並列で負荷24
に電力を供給している状態を連系運転と呼ぶ。In FIG. 1, when the power supply from the AC system 21 is lost, the circuit breaker 23 is provided to maintain the power supply to the load 24 connected to the AC system 21 until then. While opening, electric power is independently supplied to the load 24 from the self-excited inverter 22. After that, when the power supply of the AC system 21 is restored, the frequency of the output voltage of the self-excited inverter 22 is synchronized with the frequency of the AC system 21 again by the synchronization detection circuit 26,
The breaker 23 is turned on to connect the self-excited inverter 22 and the AC system 21, and the AC system 21 and the self-excited inverter 22 are operated in parallel to supply power to the load 24. In the following, the self-excited inverter 22 operates independently while it is supplying power to the load 24.
The state in which power is being supplied to the system is called interconnection operation.
【0004】次に、従来の同期検出回路の一例を示すブ
ロック図を図4に示す。この図4は、特許第131495号に
開示されており、1は入力電圧によって出力周波数を変
える可変周波数発信器、2はこの可変周波数発信器1の
出力をカウントするカウンタ、3は入力信号と内部発信
信号との位相差を比較する位相比較器、34は位相比較器
3からの位相差信号が入力され位相差を調整するループ
フィルタ、5はカウンタ2のデータで内部信号を発信す
る内部信号発信器を示す。Next, a block diagram showing an example of a conventional synchronization detection circuit is shown in FIG. This FIG. 4 is disclosed in Japanese Patent No. 131495, where 1 is a variable frequency oscillator that changes the output frequency according to the input voltage, 2 is a counter that counts the output of the variable frequency oscillator 1, and 3 is an input signal and an internal signal. A phase comparator for comparing the phase difference with the transmission signal, 34 is a loop filter for receiving the phase difference signal from the phase comparator 3 and adjusting the phase difference, 5 is an internal signal transmission for transmitting an internal signal with the data of the counter 2. Shows a container.
【0005】図5は、図4で示したループフィルタ34の
詳細を示す接続図である。なお、図5において図4と同
一要素は同一符号を付して説明を省略する。図5におい
て、41は単独運転時にループフィルタ34の出力信号を零
にするためのスイッチ、42はループフィルタ34の出力の
最大値と最小値を決定するツェナーダイオード、33は同
期検出回路26が同期する中心周波数を決定するバイアス
設定器を示す。FIG. 5 is a connection diagram showing details of the loop filter 34 shown in FIG. In FIG. 5, the same elements as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 5, 41 is a switch for zeroing the output signal of the loop filter 34 during islanding operation, 42 is a Zener diode that determines the maximum and minimum values of the output of the loop filter 34, and 33 is the synchronization detection circuit 26 6 shows a bias setter that determines the center frequency to be set.
【0006】図5において、単独運転時には、スイッチ
41は閉じられており、ループフィルタ34の出力を零に
し、バイアス設定器33で設定されている周波数に固定す
る。単独運転から連系運転に切り替わると、スイッチ41
を開き、図4で示した位相比較器3から出力された位相
差信号を入力し、可変周波数発信器1の発信周波数を調
整し、図3で示した交流系統21の電源周波数に同期する
ように、ループフィルタ34の出力を動作させる。In FIG. 5, the switch is operated during the isolated operation.
41 is closed, and the output of the loop filter 34 is set to zero and fixed to the frequency set by the bias setter 33. When switching from independent operation to interconnection operation, switch 41
Open, input the phase difference signal output from the phase comparator 3 shown in FIG. 4, adjust the oscillation frequency of the variable frequency oscillator 1, and synchronize with the power supply frequency of the AC system 21 shown in FIG. Then, the output of the loop filter 34 is operated.
【0007】[0007]
【発明が解決しようとする課題】上述したように、自励
式インバータ22が単独で負荷に電力を供給している状態
から連系運転に切り替えるときには、図5においてルー
プフィルタ34のスイッチ41が閉じている状態から開く。
このため、入力信号と内部発信信号の位相差により、ル
ープフィルタ34の出力信号が大きく変化し、自励式イン
バータ22から出力される電圧の周波数が大きく変化し
て、図3で示した負荷24を損傷したり、変換器用変圧器
の偏磁などの事故が発生するおそれがある。As described above, when switching from the state in which the self-excited inverter 22 alone supplies power to the load to the interconnection operation, the switch 41 of the loop filter 34 in FIG. 5 is closed. Open from the state.
Therefore, due to the phase difference between the input signal and the internal oscillation signal, the output signal of the loop filter 34 changes greatly, the frequency of the voltage output from the self-excited inverter 22 changes greatly, and the load 24 shown in FIG. There is a risk of damage or an accident such as magnetic bias of the transformer for the converter.
【0008】そのため、ループフィルタ34の動作を極端
に遅くする方法も考えられるが、すると、定常時に、も
し、系統の電源の位相が急に変化するような事態が発生
したときには、自励式インバータが追従できないため、
交流系統21から自励式インバータ22に大電流が流入する
おそれもある。Therefore, a method of extremely slowing the operation of the loop filter 34 may be considered. However, in a steady state, if a situation in which the phase of the power supply of the system suddenly changes occurs, the self-excited inverter is used. I can't follow, so
A large current may flow from the AC system 21 to the self-excited inverter 22.
【0009】そこで、本発明は、上記課題を解決するた
め、ループフィルタの動作が定常時には早く、単独運転
から再度連系運転に移行するときのみ遅くして、単独運
転から連系運転への移行時の負荷及び自己の損傷を防ぐ
ことのできる自励式インバータを得ることを目的とす
る。Therefore, in order to solve the above-mentioned problems, the present invention makes the operation of the loop filter fast at the steady state and delayed only when the operation is changed from the independent operation to the interconnection operation again, and the operation is changed from the independent operation to the interconnection operation. It is an object of the present invention to obtain a self-excited inverter that can prevent load and self-damage at the time.
【0010】[0010]
【課題を解決するための手段】本発明は、交流系統と連
系して負荷に電力を供給する連系運転と、交流系統と切
り放して単独で負荷に電力を供給する単独運転とに切り
替えて運転する自励式インバータの同期検出回路の入力
信号の電圧に応じて発信周波数を変える可変周波数発信
器と、この可変周波数発信器の出力周波数を計数するカ
ウンタと、このカウンタからの出力に応じて所定の信号
を発信する内部信号発信器と、この内部信号発信器の出
力と交流系統の位相の誤差を検出する位相比較器と、こ
の位相比較器の出力信号から直流成分を取り出すループ
フィルタとで構成され、このループフィルタの出力信号
を可変周波数発信器の入力信号として交流系統の位相を
カウンタの出力信号をする同期検出回路を備えた自励式
インバータにおいて、同期検出回路にループフィルタの
出力を制限する最大値リミッタと最小値リミッタを付加
したことを特徴とする。SUMMARY OF THE INVENTION The present invention switches between an interconnected operation in which electric power is supplied to a load by being connected to an AC system and an independent operation in which electric power is separately supplied to the AC system by disconnecting from the AC system. A variable frequency oscillator that changes the oscillation frequency according to the voltage of the input signal of the synchronous detection circuit of the self-excited inverter that operates, a counter that counts the output frequency of this variable frequency oscillator, and a predetermined value according to the output from this counter. It is composed of an internal signal oscillator that transmits the signal of, a phase comparator that detects the error between the output of this internal signal oscillator and the phase of the AC system, and a loop filter that extracts the DC component from the output signal of this phase comparator. In a self-excited inverter equipped with a synchronous detection circuit that uses the output signal of this loop filter as the input signal of the variable frequency oscillator and the phase of the AC system as the output signal of the counter. , Characterized in that by adding the maximum value limiter and minimum limiter for limiting the output of the loop filter to the synchronous detection circuit.
【0011】[0011]
【作用】単独運転から連系運転に切り替わるときには、
最大値リミッタと最小値リミッタが設定された時定数で
ループフィルタの出力信号が広がり、自励式インバータ
から出力される電圧の周波数の大きな変化が抑制される
ことになる。[Operation] When switching from independent operation to interconnection operation,
The output signal of the loop filter spreads with the time constants for which the maximum value limiter and the minimum value limiter are set, and a large change in the frequency of the voltage output from the self-excited inverter is suppressed.
【0012】[0012]
【実施例】以下、本発明の一実施例を図面を参照して説
明する。図1は、本発明の自励式インバータの同期検出
回路に組み込まれたループフィルタを示す接続図で、従
来技術を示す図5に対応する図である。なお、図1にお
いて、図5と同一要素は、同一符号を付して説明を省略
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a connection diagram showing a loop filter incorporated in a synchronization detection circuit of a self-excited inverter according to the present invention, and is a diagram corresponding to FIG. 5 showing a conventional technique. Note that, in FIG. 1, the same elements as those in FIG.
【0013】図1において、4はループフィルタ、41は
リミッタをリセットするスイッチ、42はリミッタの上限
を決定するツェナーダイオード、11Aはループフィルタ
4の最大値リミッタ、11Bはループフィルタ4の最小値
リミッタである。図2は、図1で示したループフィルタ
4の作用を説明するためのタイムチャートである。In FIG. 1, 4 is a loop filter, 41 is a switch for resetting the limiter, 42 is a Zener diode for determining the upper limit of the limiter, 11A is a maximum value limiter of the loop filter 4, and 11B is a minimum value limiter of the loop filter 4. Is. FIG. 2 is a time chart for explaining the operation of the loop filter 4 shown in FIG.
【0014】以下、図1及び図2をもとに、実施例の作
用を説明する。図2において、時点t0 は、連系運転か
ら単独運転に切り替わってスイッチ41が閉になる時点、
時点t1 は、単独運転から連系運転に切り替わり同期検
出回路が交流系統に同期し始める時点を示す。C0 は、
単独運転指令ONのときの最大値リミッタ11Aの出力、
同じくD0 は、単独運転指令ONのときの最小値リミッ
タ11Bの出力を示す。また、斜線Cは、単独運転指令O
FFのときの最大値リミッタ11Aの出力の推移を、斜線
Dは、単独運転指令OFFのときの最小値リミッタ11B
の出力の推移を示す。曲線Bは、ループフィルタ4の出
力信号の推移を示す。The operation of the embodiment will be described below with reference to FIGS. 1 and 2. In FIG. 2, a time point t0 is a time point when the switch 41 is closed by switching from the interconnected operation to the isolated operation,
Time point t1 indicates a time point when the independent operation is switched to the interconnected operation and the synchronization detection circuit starts synchronizing with the AC system. C0 is
Output of the maximum value limiter 11A when the islanding operation command is ON,
Similarly, D0 represents the output of the minimum value limiter 11B when the islanding operation command is ON. The diagonal line C indicates the islanding operation command O.
The transition of the output of the maximum value limiter 11A when FF is shown, the shaded line D is the minimum value limiter 11B when the individual operation command is OFF.
Shows the transition of the output of. The curve B shows the transition of the output signal of the loop filter 4.
【0015】図2において、時点T1 で単独運転から連
系運転に切り替わるときに、インバータの出力電圧と交
流系統の位相がずれているため、ループフィルタ4の出
力を点線の曲線Aで示す立ち上りの高い波形で出力しよ
うとするが、最大値リミッタ11Aの出力信号Cと最小値
リミッタ11Bの出力信号Dによってループフィルタ4の
出力がリミットされるために、曲線Bに示すように立ち
上りが緩やかで徐々に減衰した波形の出力になる。In FIG. 2, when the operation is switched from the isolated operation to the interconnection operation at the time T1, the output voltage of the inverter is out of phase with the AC system. Although an attempt is made to output with a high waveform, the output of the loop filter 4 is limited by the output signal C of the maximum value limiter 11A and the output signal D of the minimum value limiter 11B, so that the rising edge is gentle and gradually as shown by the curve B. The output is a waveform that is attenuated.
【0016】このように、ループフィルタ4の出力を制
限する最大値リミッタ11Aと最小値リミッタ11Bを同期
検出回路に付加して、これらの最大値リミッタ11Aと最
小値リミッタ11Bを、自励式インバータの単独運転時に
はループフィルタ4の出力が所定値に固定されるよう設
定しておき、自励式インバータを単独運転から連系運転
に移行させる前に、最大値リミッタ11Aと最小値リミッ
タ11Bの値を各々所定値まで徐々に変化させるようにす
ることにより、単独運転から連系運転に移行するときの
交流系統に接続されている負荷だけでなく、自己の本体
の故障を防ぐことができる。As described above, the maximum value limiter 11A and the minimum value limiter 11B for limiting the output of the loop filter 4 are added to the synchronization detection circuit, and the maximum value limiter 11A and the minimum value limiter 11B are connected to the self-excited inverter. The output of the loop filter 4 is set to a predetermined value during the isolated operation, and the values of the maximum value limiter 11A and the minimum value limiter 11B are respectively set before shifting the self-excited inverter from the independent operation to the interconnected operation. By gradually changing to a predetermined value, it is possible to prevent not only the load connected to the AC system at the time of shifting from the isolated operation to the interconnected operation but also the failure of its own body.
【0017】なお、上記実施例では、ループフィルタ及
び最大値リミッタと最小値リミッタを電子回路を用いて
構成したときで説明したが、マイクロコンピュータなど
を用いてソフトウェアで行うようにしてもよい。この場
合には、最大値リミッタ11A及び最小値リミッタ11Bを
ソフトウェアで処理することにより、本発明の自励式イ
ンバータの同期検出回路に組み込んだループフィルタを
容易に機器に組み込むことができる。In the above embodiment, the loop filter, the maximum value limiter and the minimum value limiter are described as electronic circuits, but they may be implemented by software using a microcomputer or the like. In this case, by processing the maximum value limiter 11A and the minimum value limiter 11B by software, the loop filter incorporated in the synchronization detection circuit of the self-excited inverter of the present invention can be easily incorporated in the device.
【0018】[0018]
【発明の効果】以上、本発明によれば、交流系統と連系
して負荷に電力を供給する連系運転と、交流系統と切り
放して単独で負荷に電力を供給する単独運転とに切り替
えて運転する自励式インバータの同期検出回路の入力信
号の電圧に応じて発信周波数を変える可変周波数発信器
と、この可変周波数発信器の出力周波数を計数するカウ
ンタと、このカウンタからの出力に応じて所定の信号を
発信する内部信号発信器と、この内部信号発信器の出力
と交流系統の位相の誤差を検出する位相比較器と、この
位相比較器の出力信号から直流成分を取り出すループフ
ィルタとで構成され、このループフィルタの出力信号を
可変周波数発信器の入力信号として交流系統の位相をカ
ウンタの出力信号をする同期検出回路を備えた自励式イ
ンバータにおいて、同期検出回路にループフィルタの出
力を制限する最大値リミッタと最小値リミッタを付加す
ることで単独運転から連系運転に切り替わるときには、
最大値リミッタと最小値リミッタが設定された時定数で
ループフィルタの出力信号を広げ、自励式インバータか
ら出力される電圧の周波数の大きな変化を抑制して、自
励式インバータを単独運転から連系運転に移行させる前
に、最大値リミッタと最小値リミッタの値を各々所定値
まで徐々に変化させるようにしたので、単独運転から連
系運転への移行時の負荷及び自己の損傷を防ぐことので
きる自励式インバータを得ることができる。As described above, according to the present invention, it is possible to switch between an interconnected operation in which power is supplied to a load by being connected to an AC system and an independent operation in which power is separately supplied to the AC system by disconnecting from the AC system. A variable frequency oscillator that changes the oscillation frequency according to the voltage of the input signal of the synchronous detection circuit of the self-excited inverter that operates, a counter that counts the output frequency of this variable frequency oscillator, and a predetermined value according to the output from this counter. It is composed of an internal signal oscillator that transmits the signal of, a phase comparator that detects the error between the output of this internal signal oscillator and the phase of the AC system, and a loop filter that extracts the DC component from the output signal of this phase comparator. In a self-excited inverter equipped with a synchronous detection circuit that uses the output signal of this loop filter as the input signal of the variable frequency oscillator and the output signal of the counter for the phase of the AC system When by adding a maximum value limiter and minimum limiter for limiting the output of the loop filter to the synchronous detection circuit switched to interconnected operation of a single operation,
The output signal of the loop filter is expanded with the time constants for which the maximum value limiter and the minimum value limiter are set, and large changes in the frequency of the voltage output from the self-excited inverter are suppressed, allowing the self-excited inverter to operate from independent operation to interconnected operation. Since the maximum limiter and the minimum limiter values are gradually changed to predetermined values before shifting to, it is possible to prevent the load and self-damage at the time of shifting from isolated operation to interconnection operation. A self-excited inverter can be obtained.
【図1】本発明の自励式インバータの一実施例を示す同
期検出回路の要部を示す接続図。FIG. 1 is a connection diagram showing a main part of a synchronization detection circuit showing an embodiment of a self-excited inverter of the present invention.
【図2】本発明の自励式インバータの作用を示すグラ
フ。FIG. 2 is a graph showing the operation of the self-excited inverter of the present invention.
【図3】従来の自励式インバータの一例を示す主回路単
線結線図。FIG. 3 is a main circuit single wire connection diagram showing an example of a conventional self-excited inverter.
【図4】従来の自励式インバータに組み込まれた同期検
出回路の一例を示すブロック図。FIG. 4 is a block diagram showing an example of a synchronization detection circuit incorporated in a conventional self-excited inverter.
【図5】従来の自励式インバータに組み込まれた同期検
出回路のループフィルタを示す接続図。FIG. 5 is a connection diagram showing a loop filter of a synchronization detection circuit incorporated in a conventional self-excited inverter.
【符号の説明】 1…可変周波数発信器、2…カウンタ、3…位相比較
器、4…ループフィルタ、5…内部信号発信器、11A…
最大値リミッタ、11B…最小値リミッタ、33…バイアス
設定器、41…スイッチ、42…ツェナーダイオード。[Explanation of Codes] 1 ... Variable frequency oscillator, 2 ... Counter, 3 ... Phase comparator, 4 ... Loop filter, 5 ... Internal signal oscillator, 11A ...
Maximum value limiter, 11B ... Minimum value limiter, 33 ... Bias setter, 41 ... Switch, 42 ... Zener diode.
Claims (1)
る連系運転と、前記交流系統と切り放して単独で負荷に
電力を供給する単独運転とに切り替えて運転する自励式
インバータの同期検出回路の入力信号の電圧に応じて発
信周波数を変える可変周波数発信器と、この可変周波数
発信器の出力周波数を計数するカウンタと、このカウン
タからの出力に応じて所定の信号を発信する内部信号発
信器と、この内部信号発信器の出力と前記交流系統の位
相の誤差を検出する位相比較器と、この位相比較器の出
力信号から直流成分を取り出すループフィルタとで構成
され、このループフィルタの出力信号を前記可変周波数
発信器の入力信号として前記交流系統の位相を前記カウ
ンタの出力信号をする同期検出回路を備えた自励式イン
バータにおいて、前記同期検出回路に前記ループフィル
タの出力を制限する最大値リミッタと最小値リミッタを
付加したことを特徴とする自励式インバータ。1. A synchronization of a self-excited inverter that is switched between an interconnected operation in which electric power is supplied to a load by being connected to an AC system and an isolated operation in which electric power is independently supplied to the load by disconnecting from the AC system. A variable frequency oscillator that changes the oscillation frequency according to the voltage of the input signal of the detection circuit, a counter that counts the output frequency of this variable frequency oscillator, and an internal signal that emits a predetermined signal according to the output from this counter. The oscillator, a phase comparator that detects an error between the output of the internal signal oscillator and the phase of the AC system, and a loop filter that extracts a DC component from the output signal of the phase comparator, and the loop filter In a self-excited inverter equipped with a synchronization detection circuit that uses an output signal as an input signal of the variable frequency oscillator and the phase of the AC system as an output signal of the counter, A self-excited inverter characterized in that a maximum value limiter and a minimum value limiter for limiting the output of the loop filter are added to the synchronization detection circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04234007A JP3115115B2 (en) | 1992-09-02 | 1992-09-02 | Self-excited inverter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04234007A JP3115115B2 (en) | 1992-09-02 | 1992-09-02 | Self-excited inverter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0686560A true JPH0686560A (en) | 1994-03-25 |
JP3115115B2 JP3115115B2 (en) | 2000-12-04 |
Family
ID=16964096
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP04234007A Expired - Lifetime JP3115115B2 (en) | 1992-09-02 | 1992-09-02 | Self-excited inverter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3115115B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109256806A (en) * | 2018-10-26 | 2019-01-22 | 中国电力科学研究院有限公司 | A kind of low based on Hybrid Real Time Simulation encourages long-term method for establishing model and system in limitation |
WO2023112234A1 (en) * | 2021-12-16 | 2023-06-22 | 株式会社東芝 | Electric power conversion device and program |
WO2023112231A1 (en) * | 2021-12-15 | 2023-06-22 | 株式会社東芝 | Power conversion device and program |
-
1992
- 1992-09-02 JP JP04234007A patent/JP3115115B2/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109256806A (en) * | 2018-10-26 | 2019-01-22 | 中国电力科学研究院有限公司 | A kind of low based on Hybrid Real Time Simulation encourages long-term method for establishing model and system in limitation |
CN109256806B (en) * | 2018-10-26 | 2021-09-17 | 中国电力科学研究院有限公司 | Low excitation limit medium and long term model building method and system based on digital-analog hybrid real-time simulation |
WO2023112231A1 (en) * | 2021-12-15 | 2023-06-22 | 株式会社東芝 | Power conversion device and program |
WO2023112234A1 (en) * | 2021-12-16 | 2023-06-22 | 株式会社東芝 | Electric power conversion device and program |
Also Published As
Publication number | Publication date |
---|---|
JP3115115B2 (en) | 2000-12-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4641042A (en) | Power supply system and a control method thereof | |
US4510401A (en) | Processes and devices for providing a load with an electric AC supply without discontinuity of the AC signal | |
US5771161A (en) | Uninterruptable capability for an active power line conditioner | |
US5130561A (en) | Switching mode power supplies with controlled synchronization | |
US6657319B2 (en) | Electric power system interconnection device | |
US5559686A (en) | Stepped waveform inverter control | |
JPH09247952A (en) | Uninterrupted operation method and uninterrupted power supply apparatus | |
US4480297A (en) | Synchronizing circuit for push-pull inverter | |
JPH0686560A (en) | Self-excited inverter | |
JP3550573B2 (en) | Power converter | |
JP4374605B2 (en) | PWM cycloconverter | |
JPS6181180A (en) | Driving method of parallel inverter | |
JPH0753390Y2 (en) | Uninterruptible power system | |
JPS61109429A (en) | Inverter control circuit | |
JP3217435B2 (en) | Commercial Synchronous Parallel System | |
JPS6118405B2 (en) | ||
JPS6053531B2 (en) | Inverter control method | |
JP3055267B2 (en) | Electric motor commercial operation-inverter operation switching method | |
JPS5812818B2 (en) | Seishigata Invertano Kafkahogohoushiki | |
JPH1094264A (en) | Uninterruptible power supply | |
JPS59209073A (en) | Starting method of self-excited power converter | |
JPS59153426A (en) | Methdo of operating self-excited power converter | |
SU1086502A1 (en) | Automatic load switching device | |
JPH0357116Y2 (en) | ||
JPH05207681A (en) | Switching method for power source |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
RD07 | Notification of extinguishment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: R3D07 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20070929 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080929 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080929 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090929 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090929 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100929 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100929 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110929 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120929 Year of fee payment: 12 |
|
EXPY | Cancellation because of completion of term |