JPH0683473A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0683473A JPH0683473A JP4233207A JP23320792A JPH0683473A JP H0683473 A JPH0683473 A JP H0683473A JP 4233207 A JP4233207 A JP 4233207A JP 23320792 A JP23320792 A JP 23320792A JP H0683473 A JPH0683473 A JP H0683473A
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- power supply
- wiring
- clock
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路に関
し、特に、クロック信号配線に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to clock signal wiring.
【０００２】[0002]
【従来の技術】従来の半導体集積回路では、図２に示す
ように、クロックドライバ９から、そのクロック信号専
用の配線を用いてそれぞれクロック信号の必要な内部回
路ブロック６にクロック信号を供給していた。また、近
年の半導体集積回路のプロセス微細化に伴うアルミニウ
ム配線遅延の増大によるクロックスキュー問題への対策
として、図３に示すように、クロック信号配線をＨ形ツ
リー状に形成することにより、クロックドライバ９から
それぞれの内部回路ブロック６までの配線長をほぼ同じ
にすることができ、クロックスキューを小さくしてい
る。2. Description of the Related Art In a conventional semiconductor integrated circuit, as shown in FIG. 2, a clock signal is supplied from a clock driver 9 to an internal circuit block 6 requiring a clock signal by using a wiring dedicated to the clock signal. It was Further, as a countermeasure against the clock skew problem due to the increase in aluminum wiring delay due to the recent process miniaturization of semiconductor integrated circuits, as shown in FIG. 3, by forming the clock signal wiring in an H-shaped tree shape, the clock driver is formed. The wiring length from 9 to each internal circuit block 6 can be made substantially the same, and the clock skew is reduced.
【０００３】[0003]
【発明が解決しようとする課題】前述した従来の半導体
集積回路の第１の例では、クロックドライバから内部回
路ブロックまでの配線長がそれぞれ異なるため、特にア
ルミニウム配線の微細化により配線遅延の影響でクロッ
クスキューが大きくなり、最悪の場合回路が誤動作を起
こしてしまうという欠点がある。In the above-mentioned first example of the conventional semiconductor integrated circuit, the wiring lengths from the clock driver to the internal circuit block are different from each other. There is a drawback that the clock skew becomes large and the circuit malfunctions in the worst case.
【０００４】上記の欠点を補うために、クロック信号を
伝搬する配線を配線遅延が小さくなるように太くしてク
ロックスキューを小さくするという方法があるが、この
方法では近年の半導体集積回路の高集積化に反し、かな
り大きな配線領域を要する。また、クロックスキュー対
策をほどこした従来の半導体集積回路の第２の例では広
い配線領域を必要とし、さらに、チップ上にマクロが配
置されるスタンダードセルでは、この方式を用いること
ができないという欠点がある。In order to make up for the above-mentioned drawbacks, there is a method of reducing the clock skew by thickening the wiring for propagating the clock signal so that the wiring delay becomes small. In this method, however, high integration of recent semiconductor integrated circuits has been proposed. Contrary to this, a considerably large wiring area is required. Further, the second example of the conventional semiconductor integrated circuit provided with a measure against clock skew requires a large wiring area, and further, this method cannot be used in the standard cell in which the macro is arranged on the chip. is there.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体集積回路
は、半導体基板上に設けて直流電圧とクロック信号を合
成した合成信号を供給する主電源配線と、前記主電源配
線に接続して前記合成信号より直流電圧を分離し内部電
源配線に供給する低域フィルタと、前記主電源配線に接
続して前記合成信号よりクロック信号を分離し、内部回
路ブロックに供給するコンパレータとを有する。A semiconductor integrated circuit according to the present invention is provided with a main power supply line which is provided on a semiconductor substrate and which supplies a combined signal obtained by combining a DC voltage and a clock signal, and the main power supply line connected to the main power supply line. It has a low-pass filter for separating the DC voltage from the combined signal and supplying it to the internal power supply line, and a comparator connected to the main power supply line for separating the clock signal from the combined signal and supplying it to the internal circuit block.
【０００６】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【０００７】図１は本発明の一実施例を説明するための
模式図である。FIG. 1 is a schematic diagram for explaining one embodiment of the present invention.
【０００８】図１に示すように、半導体チップ１０上に
設けて直流電圧ＶDDとクロック信号８を合成した合成信
号を供給する主電源配線２と、主電源配線２に接続して
合成信号より直流電圧を分離し内部電源配線３に供給す
る低域フィルタ５と、主電源配線２に接続して合成信号
よりクロック信号を分離して整形し内部回路ブロック６
に供給するコンパレータ４とを備えて構成される。As shown in FIG. 1, a main power supply wiring 2 which is provided on the semiconductor chip 10 and supplies a composite signal obtained by combining the DC voltage V DD and the clock signal 8, and a main power supply wiring 2 connected to the main power supply wiring 2 The low-pass filter 5 that separates the DC voltage and supplies it to the internal power supply wiring 3 and the main power supply wiring 2 that separates and shapes the clock signal from the composite signal and internal circuit block 6
And a comparator 4 for supplying
【０００９】ここで、合成信号は直流電圧ＶDD＝５Ｖに
トランジスタのしきい値電圧等を考慮して±０．５Ｖの
振幅を有するクロック周波数のクロック正弦波８を重畳
しており、クロック信号を供給する内部回路ブロック６
の配置により、信号配線の長さが短くなるようにコンパ
レータ４の配置を選択する。Here, the synthesized signal is obtained by superposing a clock sine wave 8 of a clock frequency having an amplitude of ± 0.5 V on the DC voltage V DD = 5 V in consideration of the threshold voltage of the transistor and the like. Circuit block 6 for supplying
The placement of the comparator 4 is selected so that the length of the signal wiring becomes shorter.
【００１０】[0010]
【発明の効果】以上、説明したように本発明は、クロッ
ク信号を主電源配線に乗せることにより、信号配線より
太い電源配線を使用して配線抵抗を小さくすることがで
きるので配線遅延によるクロックスキューを低減できる
という効果を有する。As described above, according to the present invention, by placing the clock signal on the main power supply wiring, it is possible to reduce the wiring resistance by using the power supply wiring thicker than the signal wiring. It has an effect that can reduce.
【００１１】また、クロック周波数波をディジタルクロ
ック信号に整形するコンパレータを多く用いたり、その
配置を効果的に取ることにより、クロックスキューをか
なり小さくコントロールできるという効果を有する。Further, the clock skew can be controlled to be considerably small by using many comparators for shaping the clock frequency wave into a digital clock signal and effectively arranging the comparators.
【００１２】また、クロック信号供給のための専用配線
が不要となるので集積度を向上できるという効果を有す
る。Further, since there is no need for a dedicated wiring for supplying a clock signal, there is an effect that the degree of integration can be improved.
【図１】本発明の一実施例を説明するための模式図。FIG. 1 is a schematic diagram for explaining an embodiment of the present invention.
【図２】従来の半導体集積回路の第１の例を説明するた
めの模式図。FIG. 2 is a schematic diagram for explaining a first example of a conventional semiconductor integrated circuit.
【図３】従来の半導体集積回路の第２の例を説明するた
めの模式図。FIG. 3 is a schematic diagram for explaining a second example of a conventional semiconductor integrated circuit.
２ 主電源配線 ３ 内部電源配線 ４ コンパレータ ５ 低域フィルタ ６ 内部回路ブロック ８ クロック正弦波 ９ クロックドライバ １０ 半導体チップ 2 Main power supply wiring 3 Internal power supply wiring 4 Comparator 5 Low-pass filter 6 Internal circuit block 8 Clock sine wave 9 Clock driver 10 Semiconductor chip
Claims (1)
ク信号を合成した合成信号を供給する主電源配線と、前
記主電源配線に接続して前記合成信号より直流電圧を分
離し内部電源配線に供給する低域フィルタと、前記主電
源配線に接続して前記合成信号よりクロック信号を分離
し内部回路ブロックに供給するコンパレータとを有する
ことを特徴とする半導体集積回路。1. A main power supply wiring which is provided on a semiconductor substrate and supplies a synthesized signal obtained by synthesizing a DC voltage and a clock signal, and a main power wiring which is connected to the main power wiring to separate a DC voltage from the synthesized signal to form an internal power wiring. A semiconductor integrated circuit comprising: a low-pass filter to be supplied; and a comparator connected to the main power supply line to separate a clock signal from the composite signal and supply the separated clock signal to an internal circuit block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4233207A JP2806166B2 (en) | 1992-09-01 | 1992-09-01 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4233207A JP2806166B2 (en) | 1992-09-01 | 1992-09-01 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0683473A true JPH0683473A (en) | 1994-03-25 |
| JP2806166B2 JP2806166B2 (en) | 1998-09-30 |
Family
ID=16951439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4233207A Expired - Lifetime JP2806166B2 (en) | 1992-09-01 | 1992-09-01 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2806166B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008504720A (en) * | 2004-05-24 | 2008-02-14 | ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア | High-speed clock distribution transmission line network |
| JP2015211068A (en) * | 2014-04-24 | 2015-11-24 | ローム株式会社 | Semiconductor device |
-
1992
- 1992-09-01 JP JP4233207A patent/JP2806166B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008504720A (en) * | 2004-05-24 | 2008-02-14 | ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア | High-speed clock distribution transmission line network |
| JP2015211068A (en) * | 2014-04-24 | 2015-11-24 | ローム株式会社 | Semiconductor device |
| US10008284B2 (en) | 2014-04-24 | 2018-06-26 | Rohm Co., Ltd. | Semiconductor device including an interface arranged to perform external data communications |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2806166B2 (en) | 1998-09-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980623 |