JPH0677464A - Schottky barrier semiconductor device - Google Patents

Schottky barrier semiconductor device

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Publication number
JPH0677464A
JPH0677464A JP24875592A JP24875592A JPH0677464A JP H0677464 A JPH0677464 A JP H0677464A JP 24875592 A JP24875592 A JP 24875592A JP 24875592 A JP24875592 A JP 24875592A JP H0677464 A JPH0677464 A JP H0677464A
Authority
JP
Japan
Prior art keywords
metal layer
schottky
schottky metal
barrier
barrier height
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24875592A
Other languages
Japanese (ja)
Inventor
Tsukasa Kuroda
司 黒田
Hiroaki Iwaguro
弘明 岩黒
Junichi Ono
純一 大野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP24875592A priority Critical patent/JPH0677464A/en
Publication of JPH0677464A publication Critical patent/JPH0677464A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve the forward characteristic and the reverse characteristic of the title semiconductor device by a method wherein the width on the main surface of a second Schottky metal layer, having a small barrier height, which is sandwiched by a first Schottky metal layer having a large barrier height is set at a specific value or lower. CONSTITUTION:Then, regarding a first Schottky metal layer 7 and a second Schottky metal layer 8 whose barrier height is different from each other, Al is selected for the layer 7 and Ti is selected for the layer R, the barrier height of the first Schottky metal layer 7 becomes larger than that of the second Schottky metal layer 8. A metal barrier layer 9 is formed of TEN or the like. The width W on the main surface of a single-crystal substrate 2 of the second Schottky metal layer 8, having a small barrier height, which is sandwiched by the first Schottky metal layer 7 having a large barrier height is set at 1mum. Thereby, a Schottky barrier semiconductor device whose forward loss and reverse loss are extremely small and whose loss is low can be constituted with high integration density.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、ショットキバリア半導
体装置の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a Schottky barrier semiconductor device.

【０００２】[0002]

【従来の技術】従来から、順方向特性が優れ、高速、か
つ低損失の整流ダイオ−ドとして、ショットキバリア半
導体装置が知られている。2. Description of the Related Art Conventionally, a Schottky barrier semiconductor device has been known as a rectifying diode having excellent forward characteristics, high speed and low loss.

【０００３】図１は、従来構造のショットキバリアダイ
オ−ドの断面構造図であり、１はシリコン単結晶基板、
２はエピタキシアル成長層等のシリコン単結晶基体、３
はショットキバリア金属、４は酸化膜等の表面保護用絶
縁膜、６は２のシ（２）リコン単結晶基体の導電型と逆
の導電型を有するガ−ドリング領域、Ａはアノ−ド、Ｃ
はカソ−ドである。FIG. 1 is a cross-sectional structural view of a conventional Schottky barrier diode, wherein 1 is a silicon single crystal substrate,
2 is a silicon single crystal substrate such as an epitaxial growth layer, 3
Is a Schottky barrier metal, 4 is a surface protection insulating film such as an oxide film, 6 is a guard ring region having a conductivity type opposite to that of the silicon (2) silicon single crystal substrate of 2, A is an anode, C
Is a cat.

【０００４】図１のような従来構造により、低損失のシ
ョットキバリアダイオ−ドを実現するためには順方向電
圧降下と逆方向電流が現在のものより小さく、ダイオ−
ドの損失即ち順方向損失と逆方向損失の和の小さい整流
特性の良好なものの実現が必要がある。しかし、ショッ
トキバリアダイオ−ドの順方向電圧降下と逆方向電流は
図２に示す定性的な関係図のように、ショットキ接合を
形成するバリアメタルの材質によって決定される。一般
には順方向電圧降下が小さいものは逆方向漏れ電流が大
きく、逆方向漏れ電流が小さいものは順方向電圧降下が
大きいという順逆相反する性質を有する。例えば順方向
電圧降下を従来知られているメタルで見れば、図２のよ
うにチタン（Ｔｉ）、クロム（Ｃｒ）、現在最も多く用
いられているモリブデン（Ｍｏ）の順序で大となって順
方向損失を大とする傾向をもつ。従って損失が順方向と
逆方向の和で与えられるダイオ−ドにおいては、順逆方
向損失の兼ね合いによっても最も低損失が実現される材
質を選ばざるを得ず、現状ではモリブデン（Ｍｏ）が最
も多く用いられている。In order to realize a Schottky barrier diode having a low loss with the conventional structure as shown in FIG. 1, the forward voltage drop and the reverse current are smaller than those of the current one, and the diode is
It is necessary to realize a good rectification characteristic with a small loss of charge, that is, the sum of forward loss and reverse loss. However, the forward voltage drop and the reverse current of the Schottky barrier diode are determined by the material of the barrier metal forming the Schottky junction as shown in the qualitative relationship diagram shown in FIG. In general, the one having a small forward voltage drop has a large reverse leakage current, and the one having a small reverse leakage current has a large forward voltage drop. For example, when looking at the forward voltage drop in a conventionally known metal, as shown in FIG. 2, titanium (Ti), chromium (Cr), and molybdenum (Mo), which are most often used at present, become larger in order. It tends to increase the directional loss. Therefore, in the diode where the loss is given by the sum of the forward and reverse directions, it is inevitable to select a material that realizes the lowest loss due to the trade-off between the forward and reverse losses. Currently, molybdenum (Mo) is the most common material. It is used.

【０００５】その他、主として、逆方向特性の改善のた
め、図１のショットキ金属３と接触するシリコン単結晶
基体２の表面を凹凸状とし、凹部に逆導電型半導体領域
を形成する構造のショットキダイオ−ドが提案されてい
る。又、バリアハイトの異なる二種類のショットキ金属
をシリコン単結晶基体上に設けて、順方向損失と逆方向
損失の改善を意図した構造も提案されている。In addition, mainly, in order to improve the reverse characteristics, the surface of the silicon single crystal substrate 2 in contact with the Schottky metal 3 of FIG. 1 is made uneven, and a Schottky diode having a structure in which a reverse conductivity type semiconductor region is formed in the recess. -De is proposed. Also proposed is a structure in which two types of Schottky metals having different barrier heights are provided on a silicon single crystal substrate to improve forward loss and backward loss.

【０００６】[0006]

【発明の解決しようとする課題】ショットキ金属が一種
類の従来構造では、順方向および逆方向特性の両方を満
足させる構造を得ることが困難である。又、単結晶半導
体基体表面に凹凸を設ける従来構造は、製造が厄介であ
る。又、二種類のショットキ金属を設（３）けた従来構
造では、十分な低損失特性のものを高集積度により実現
することが困難であり、さらに厚さが０.１μｍ以下の
薄いショットキ金属の形成による構造が製造しにくく、
従って、微細加工精度の面でも問題があった。In the conventional structure having one type of Schottky metal, it is difficult to obtain a structure satisfying both forward and backward characteristics. Further, the conventional structure in which unevenness is provided on the surface of the single crystal semiconductor substrate is difficult to manufacture. Further, in the conventional structure having two kinds of Schottky metals (3), it is difficult to realize a sufficiently low loss property with a high degree of integration, and further, a thin Schottky metal having a thickness of 0.1 μm or less is used. The structure by forming is difficult to manufacture,
Therefore, there is a problem in terms of precision of fine processing.

【０００７】[0007]

【課題を解決するための手段】本発明は、（１）平面状
をなす単結晶半導体基体の主表面上に、バリアハイトの
異なる第１および第２のショットキ金属層を隣接して設
け、かつ、バリアハイトの大きい第１（又は第２）のシ
ョットキ金属層がはさむバリアハイトの小さい第２（又
は第１）のショットキ金属層の前記主表面上の幅を１μ
ｍ以下としたこと。According to the present invention, (1) first and second Schottky metal layers having different barrier heights are provided adjacent to each other on the main surface of a planar single crystal semiconductor substrate, and The width of the second (or first) Schottky metal layer having a small barrier height sandwiched by the first (or second) Schottky metal layer having a large barrier height on the main surface is 1 μm.
Must be m or less.

【０００８】（２）平面状をなす単結晶半導体基体の主
表面上に、バリアハイトの異なる第１および第２のショ
ットキ金属層が隣接し、かつ、第１（又は第２）のショ
ットキ金属層は、第２（又は第１）のショットキ金属層
の少なくとも頂部に形成した金属障壁層を介し、全面を
被うように設けたこと。(2) The first and second Schottky metal layers having different barrier heights are adjacent to each other on the main surface of the planar single crystal semiconductor substrate, and the first (or second) Schottky metal layer is , The second (or first) Schottky metal layer is provided so as to cover the entire surface through the metal barrier layer formed on at least the top portion.

【０００９】（３）前項の第１又は第２のショットキ金
属層の内、バリアハイトの小さい方のショットキ金属層
の単結晶半導体基体の主表面上の幅を１μｍ以下とした
こと。これらにより、集積度および微細加工精度が高
く、かつ、低損失特性をもった、特に、単位セルを多数
個並列接続して構成する電力用等のショットキバリア半
導体装置に好適な構造を実現する。(3) The width on the main surface of the single crystal semiconductor substrate of the Schottky metal layer having the smaller barrier height of the first or second Schottky metal layers in the preceding paragraph is set to 1 μm or less. As a result, it is possible to realize a structure having a high degree of integration and fine processing accuracy and a low loss characteristic, which is particularly suitable for a Schottky barrier semiconductor device for electric power, which is formed by connecting a number of unit cells in parallel.

【００１０】[0010]

【実施例】図３（ａ）（ｂ）は本発明の実施例を示す平
面図および断面図であり、図１と同一符号は同等部分を
示す。７、８はバリアハイトの異なる第１および第２の
ショットキ金属層であり、例えば、７にＡｌ、８にＴｉ
を選択した場合は、７の第１のショットキ金属層は８の
第２のショットキ金属層よりバリアハイトが大となる。
９は例えばＴｉＮ、ＴｉＷ等の金属障壁層である。
（４）3 (a) and 3 (b) are a plan view and a sectional view showing an embodiment of the present invention, and the same reference numerals as those in FIG. 1 denote the same parts. Reference numerals 7 and 8 are first and second Schottky metal layers having different barrier heights. For example, 7 is Al and 8 is Ti.
In the case where is selected, the barrier height of the first Schottky metal layer 7 is larger than that of the second Schottky metal layer 8.
Reference numeral 9 is a metal barrier layer such as TiN or TiW.
(4)

【００１１】本発明構造の基本作用は、第１および第２
の二種類のショットキ金属層をシリコン単結晶基体２に
被着し、その間にショットキバリアを形成し、順方向特
性および逆方向特性の改善を図る点で、従来構造と同等
である。The basic operation of the structure of the present invention is as follows:
These two types of Schottky metal layers are adhered to the silicon single crystal substrate 2, and a Schottky barrier is formed between them to improve the forward characteristic and the reverse characteristic, which is the same as the conventional structure.

【００１２】しかしながら、本発明構造の重要な特徴の
第一は、バリアハイトの大きい第１のショットキ金属層
７がはさむバリアハイトの小さい第２のショットキ金属
層８の単結晶基体２の主表面上における幅Ｗを１μｍ以
下とすることである。又、０.０５〜０.５μｍが実験的
に幅Ｗの好ましい値であることがわかった。一方、その
とき、バリアハイトの大きい第１のショットキ金属層７
の主表面上の幅は、任意に選択できるが、８の幅Ｗと同
等程度までとして、集積度を上げ得るようにする。However, the first important feature of the structure of the present invention is the width of the second Schottky metal layer 8 having a small barrier height sandwiched by the first Schottky metal layer 7 having a large barrier height on the main surface of the single crystal substrate 2. W is to be 1 μm or less. Further, it has been experimentally found that the width W is preferably 0.05 to 0.5 μm. On the other hand, at that time, the first Schottky metal layer 7 having a large barrier height
Although the width on the main surface of can be arbitrarily selected, the width can be made approximately equal to the width W of 8 so that the degree of integration can be increased.

【００１３】このような、第一の特徴により、順方向お
よび逆方向損失の極めて小なる低損失のショットキバリ
ア半導体装置を高集積度により構成し得る。Due to the first feature as described above, a Schottky barrier semiconductor device having a low loss with extremely small forward and backward losses can be formed with a high degree of integration.

【００１４】重要な特徴の第二は、第１のショットキ金
属層７と第２のショットキ金属層８の隣接配置におい
て、８の金属層を、７の金属層が全面を被うように設け
る場合、８の金属層の少なくとも頂部に、金属障壁層９
を設けることである。この場合にも第一の特徴であるＷ
＝１μｍ以下とすることが好ましい。The second important feature is that when the first Schottky metal layer 7 and the second Schottky metal layer 8 are arranged adjacent to each other, the eight metal layers are provided so that the seven metal layers cover the entire surface. , 8 on at least the top of the metal layer, metal barrier layer 9
Is to be provided. Also in this case, the first feature W
= 1 μm or less is preferable.

【００１５】このような、第二の特徴は、８の金属層の
上に７の金属層が重なる部分において、製造又は使用上
の温度上昇等に起因して、７の金属が８の金属中に侵入
し、単結晶基体２の主表面に達し、８のショットキバリ
アに影響を及ぼす現象を有効に防止する。第２の金属層
８の厚みは、微細加工精度を上げるため、０.０１μｍ
〜０.０５μｍ程度に薄くすることが好ましく、従っ
て、前記の８の金属層への拡散現象を起こしやすい状態
にあるので、ＴｉＮ、ＴｉＷ等の金属障壁層９の設置効果
は極めて大きい。（５）Such a second feature is that, in the portion where the metal layer 7 is overlaid on the metal layer 8 and the metal 7 is in the metal 8 because of a temperature rise during manufacture or use. And effectively reaches the main surface of the single crystal substrate 2 and effectively affects the Schottky barrier. The thickness of the second metal layer 8 is 0.01 μm in order to improve the precision of fine processing.
It is preferable to reduce the thickness to about 0.05 μm. Therefore, since the diffusion phenomenon into the metal layer 8 described above is likely to occur, the effect of installing the metal barrier layer 9 such as TiN or TiW is extremely large. (5)

【００１６】図３以外の本発明構造の実施例としては、
種々の変形があり、以下に例示する。 （１）第１のショットキ金属層７の方を、バリアハイト
を小さく、第２のショットキ金属層８の方をバリアハイ
トの大きい金属とすることもできる。この場合は、単結
晶基体２の主表面上における金属層７の幅をＷ＝１μｍ
以下にして、前記第一の特徴を選択し得る。 （２）第１と第２のショットキ金属層の隣接させる形状
パタ−ンとしては、一方が他方を包囲する形状でなく、
ストライプ状に並列させるようにしてもよい。As an embodiment of the structure of the present invention other than FIG. 3,
There are various modifications, which are exemplified below. (1) It is also possible that the first Schottky metal layer 7 has a smaller barrier height and the second Schottky metal layer 8 has a larger barrier height. In this case, the width of the metal layer 7 on the main surface of the single crystal substrate 2 is W = 1 μm.
The first feature may be selected as follows. (2) As the shape pattern in which the first and second Schottky metal layers are adjacent to each other, one of the shape patterns does not surround the other,
The stripes may be arranged in parallel.

【００１７】図４（ａ）、（ｂ）に、図３の本発明構造
を図１の従来構造に対比したダイオ−ド特性図を示し、
（ａ）は順方向特性図、（ｂ）は逆方向特性図である。
図中、（イ）は従来例で、Ｔｉショットキバリアダイオ
−ド（バリアハイト０.５ｅＶ）、（ロ）は本発明構造
のＷを０.５μｍとした場合の実施例を示す。即ち本発
明構造の実施例による順方向特性（ロ）はＶF＝０.３５
volt（ａｔ ２００Ａｍｐ／ｃｍ2）であり、従来構造
（イ）のＴｉショットキバリアダイオ−ド ＶF＝０.３
０voltに近い順方向特性が得られた。一方逆方向特性に
おいて本実施例では特性（ロ）に示すように降伏電圧Ｖ
B≒３０voltの点ではＩＲ＝４.０ｍＡ程度の逆方向漏れ
電流（ＩR）を得た。従来構造のＴｉショットキバリア
ダイオ−ドではＩR＝３２ｍＡであり、ダイオ−ドのパ
ワ−の損失を約２／５にすることができた。FIGS. 4A and 4B are diode characteristic diagrams comparing the structure of the present invention of FIG. 3 with the conventional structure of FIG.
(A) is a forward characteristic chart, (b) is a reverse characteristic chart.
In the figure, (a) shows a conventional example, Ti Schottky barrier diode (barrier height 0.5 eV), and (b) shows an example in which W of the structure of the present invention is 0.5 μm. That is, the forward characteristic (b) according to the embodiment of the structure of the present invention is VF = 0.35.
volt (at 200 Amp / cm 2) and Ti Schottky barrier diode VF = 0.3 of the conventional structure (a).
A forward characteristic close to 0 volt was obtained. On the other hand, in the reverse direction characteristic, in this embodiment, as shown in the characteristic (B), the breakdown voltage V
At the point of B≈30 volt, the reverse leakage current (IR) of IR = 4.0 mA was obtained. In the conventional Schottky barrier diode, IR = 32 mA, and the power loss of the diode could be reduced to about 2/5.

【００１８】次に、前記の本発明構造の実施例につい
て、製造工程例を述べる。ヒ素不純物原子をド−プした
比抵抗０.００３Ω・ｃｍ厚さ４００μｍのシリコン基
板１上にリンを不純物原子とした比抵抗０.５Ω・ｃｍ
のエピタキシアルシリコン層２を６μｍ堆積させる。ス
チ−ム酸化処理で約０.７μｍ厚さのＳｉＯ2膜を形成
し、ガ−ドリング部（６）分のみの酸化膜を除去する第
１次の写真処理を行う。その後、フッ酸系のエッチング
液でガ−ドリング部を窓開けする。イオン注入でボロン
原子を約５×１０14ｃｍ-2を５０ｋｅＶで打ち込み、１
１００℃、１２０分、Ｏ2雰囲気でアニ−ル拡散してガ
−ドリング部６（Ｐ+拡散）２μｍを形成する。次に、
ショットキ金属を形成する部分のガ−ドリング部内側の
酸化膜を除去する第２次の写真処理を行う。さらに、Ｔ
ｉ膜とＴｉＮ膜をスパッタ堆積法を用いて連続的に堆積
させる。Ｔｉ膜の膜厚は１００オングストロ−ム、Ｔｉ
Ｎ膜の膜厚は５００オングストロ−ム堆積させる。Ｔｉ
膜は、アルゴン分圧を１０ｍＴｏｒｒだけ導入し、ＤＣ
パワ−を１.０ＫＷとすることで、約３０秒で１００オ
ングストロ−ムの膜厚が達成される。ＴｉＮ膜は、アル
ゴンの分圧を８ｍＴｏｒｒとし窒素の分圧を２ｍＴｏｒ
ｒとして、ＤＣパワ−を１.５ｋＷとすることで、約２
分で５００オングストロ−ムの膜厚が達成される。次
に、第３次の写真処理後、低いショットキバリアハイト
となる領域以外のＴｉ／ＴｉＮ堆積膜をエッチングす
る。Ｔｉの膜厚を１００オングストロ−ムとし、ＴｉＮ
の膜厚を５００オングストロ−ムとして、できる限り薄
い膜にした理由は、このエッチング時に生じるサイドエ
ッチング量を減少させて、マスク寸法の設計通りのエッ
チングを可能にするためである。このデバイスでは、こ
のような微細加工精度を高める工夫が必要である。Ｔｉ
Ｎ膜のエッチング液としてはＨＮＯ3とＣＨ3ＣＯＯＨと
ＨＦ（２０：２０：１）の混合液を用いた。５００オン
グストロ−ムのＴｉＮ膜は約２０秒でエッチングされ
る。さらに、Ｔｉは２％ＨＦを用いた。この場合、１０
０オングストロ−ムのＴｉ膜は約１０秒でエッチングさ
れる。その後、高いショットキバリアハイトのＡｌ金属
をスパッタ堆積法を用いて０.５μｍだけ堆積させ、引
き続きＮｉ蒸着を真空蒸着室内で通常方法にて行った。
また、Ｓｉウェハ−の裏面にもＣｒ／Ｎｉ蒸着を引き続
き処理する。次に、パタ−ン面のＡ電極必要領域にのみ
Ａｌ／Ｎｉが存在するように第４次写真を行う。Ｎｉの
エッチング液は塩化第２鉄系のエッチング液で、又、
（７）Ａｌは公知のＨ3ＰＯ4系のエッチング液でエッチ
ングした。その後、ウェハ−上のＮｉ面にＰｂ−Ｓｎ系
ハンダを溶融、チップをダイシングし、通常の工程に
て、ショットキバリアダイオ−ドチップを完成させた。Next, an example of manufacturing process will be described for the embodiment of the structure of the present invention. Specific resistance of doped arsenic impurity atoms 0.003 Ω · cm Specific resistance of 0.5 Ω · cm with phosphorus as an impurity atom on a silicon substrate 1 having a thickness of 400 μm.
Of the epitaxial silicon layer 2 of 6 μm is deposited. A SiO2 film having a thickness of about 0.7 .mu.m is formed by the steam oxidation process, and the first photographic process for removing the oxide film only in the guard ring portion (6) is performed. After that, the window of the guard ring is opened with a hydrofluoric acid-based etching solution. About 5 × 10 14 cm −2 of boron atom is implanted by ion implantation at 50 keV, and 1
Anneal diffusion is carried out at 100 DEG C. for 120 minutes in an O2 atmosphere to form a guard ring portion 6 (P @ + diffusion) 2 .mu.m. next,
A second photographic process is performed to remove the oxide film inside the guard ring portion where the Schottky metal is formed. Furthermore, T
The i film and the TiN film are continuously deposited by the sputter deposition method. The thickness of the Ti film is 100 angstrom, Ti
The film thickness of the N film is 500 Å. Ti
The membrane was introduced with an argon partial pressure of 10 mTorr and DC
By setting the power to 1.0 KW, a film thickness of 100 angstrom can be achieved in about 30 seconds. The TiN film has a partial pressure of argon of 8 mTorr and a partial pressure of nitrogen of 2 mTorr.
By setting the DC power to 1.5 kW as r, about 2
Film thicknesses of 500 Angstroms are achieved in minutes. Next, after the third photographic process, the Ti / TiN deposited film other than the region which becomes the low Schottky barrier height is etched. The film thickness of Ti is 100 angstrom and TiN
The reason why the film thickness is set to 500 angstroms and the film is made as thin as possible is to reduce the side etching amount generated at the time of etching and enable the etching as designed for the mask dimension. In this device, it is necessary to devise to improve the precision of such fine processing. Ti
As an etching solution for the N film, a mixed solution of HNO3, CH3COOH and HF (20: 20: 1) was used. The 500 Å TiN film is etched in about 20 seconds. Further, as Ti, 2% HF was used. In this case 10
The 0 angstrom Ti film is etched in about 10 seconds. Then, Al metal having a high Schottky barrier height was deposited to a thickness of 0.5 μm by the sputter deposition method, and then Ni vapor deposition was performed in a vacuum vapor deposition chamber by a normal method.
Further, Cr / Ni vapor deposition is also continuously processed on the back surface of the Si wafer. Next, a fourth photograph is taken so that Al / Ni is present only in the A electrode required area of the pattern surface. The etching solution of Ni is a ferric chloride-based etching solution.
(7) Al was etched with a known H3PO4 type etching solution. After that, Pb-Sn solder was melted on the Ni surface of the wafer and the chips were diced, and Schottky barrier diode chips were completed in the usual process.

【００１９】前記せる本発明の実施例で示した構造およ
び製造工程は、本発明の要旨の範囲で、変形、変換、付
加等の変更をなし得るものである。The structure and manufacturing process shown in the above-mentioned embodiment of the present invention can be modified, changed, added, etc. within the scope of the gist of the present invention.

【００２０】[0020]

【発明の効果】以上説明したように、順方向および逆方
向損失を低減すると共に、集積度および微細加工精度の
高いショットキバリア半導体装置を製造容易に得ること
ができるので、電力用をはじめ、各種用途に利用して、
産業上の効果、極めて大なるものである。As described above, since it is possible to easily manufacture a Schottky barrier semiconductor device having a high degree of integration and a fine processing precision while reducing the forward and backward losses, it is possible to obtain various kinds of electric power such as power. Used for purposes,
The industrial effect is extremely large.

【図面の簡単な説明】[Brief description of drawings]

【図１】従来構造の断面構造図である。FIG. 1 is a sectional structural view of a conventional structure.

【図２】従来構造の整流特性関係図である。FIG. 2 is a rectification characteristic relationship diagram of a conventional structure.

【図３】本発明構造の構造図であり、（ａ）は平面図、
（ｂ）は断面図である。FIG. 3 is a structural view of the structure of the present invention, (a) is a plan view,
(B) is a sectional view.

【図４】特性図であり、（ａ）は順方向特性図、（ｂ）
は逆方向特性図である。FIG. 4 is a characteristic diagram in which (a) is a forward characteristic diagram and (b) is a characteristic diagram.
Is a reverse characteristic diagram.

【符号の説明】[Explanation of symbols]

１ 単結晶基板 ２ 単結晶基体 ３ ショットキ金属 ４ 表面保護用絶縁膜 ５ 水素を含む半導体領域 ６ ガ−ドリング領域 （８） ７ 第１のショットキ金属 ８ 第２のショットキ金属 ９ 金属障壁層 Ａ アノ−ド Ｃ カソ−ド Ｗ バリアハイトの小さい方の第１又は第２のショ
ットキ金属層の幅1 Single Crystal Substrate 2 Single Crystal Substrate 3 Schottky Metal 4 Surface Protective Insulating Film 5 Semiconductor Region Containing Hydrogen 6 Guarding Region (8) 7 First Schottky Metal 8 Second Schottky Metal 9 Metal Barrier Layer A De C cathode W width of the first or second Schottky metal layer having a smaller barrier height

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 平面状をなす単結晶半導体基体の主表面
上に、バリアハイトの異なる第１および第２のショット
キ金属層を隣接して設け、かつ、バリアハイトの大きい
第１（又は第２）のショットキ金属層がはさむバリアハ
イトの小さい第２（又は第１）のショットキ金属層の前
記主表面上の幅を１μｍ以下としたことを特徴とするシ
ョットキバリア半導体装置。1. A first (or second) Schottky metal layer having a different barrier height is provided adjacently on a main surface of a planar single crystal semiconductor substrate, and a first (or second) large barrier height is provided. A Schottky barrier semiconductor device, wherein the width of the second (or first) Schottky metal layer having a small barrier height sandwiched by the Schottky metal layer on the main surface is 1 μm or less. 【請求項２】 平面状をなす単結晶半導体基体の主表面
上に、バリアハイトの異なる第１および第２のショット
キ金属層が隣接し、かつ、第１（又は第２）のショット
キ金属層は、第２（又は第１）のショットキ金属層の少
なくとも頂部に形成した金属障壁層を介し、全面を被う
ように設けたことを特徴とするショットキバリア半導体
装置。2. The first and second Schottky metal layers having different barrier heights are adjacent to each other on the main surface of a single crystal semiconductor substrate having a planar shape, and the first (or second) Schottky metal layer comprises: A Schottky barrier semiconductor device, which is provided so as to cover the entire surface of the second (or first) Schottky metal layer via a metal barrier layer formed on at least the top. 【請求項３】 第１又は第２のショットキ金属層の内、
バリアハイトの小さい方のショットキ金属層の単結晶半
導体基体の主表面上の幅を１μｍ以下としたことを特徴
とする請求項２のショットキバリア半導体装置。3. The first or second Schottky metal layer,
3. The Schottky barrier semiconductor device according to claim 2, wherein the width of the Schottky metal layer having a smaller barrier height on the main surface of the single crystal semiconductor substrate is 1 μm or less.
JP24875592A 1992-08-25 1992-08-25 Schottky barrier semiconductor device Pending JPH0677464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24875592A JPH0677464A (en) 1992-08-25 1992-08-25 Schottky barrier semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24875592A JPH0677464A (en) 1992-08-25 1992-08-25 Schottky barrier semiconductor device

Publications (1)

Publication Number Publication Date
JPH0677464A true JPH0677464A (en) 1994-03-18

Family

ID=17182899

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24875592A Pending JPH0677464A (en) 1992-08-25 1992-08-25 Schottky barrier semiconductor device

Country Status (1)

Country Link
JP (1) JPH0677464A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6452244B1 (en) * 1996-12-03 2002-09-17 Japan Science And Technology Corporation Film-like composite structure and method of manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6452244B1 (en) * 1996-12-03 2002-09-17 Japan Science And Technology Corporation Film-like composite structure and method of manufacture thereof

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