JPH0661827A - High withstanding voltage drive circuit for capacitive load - Google Patents

High withstanding voltage drive circuit for capacitive load

Info

Publication number
JPH0661827A
JPH0661827A JP20897492A JP20897492A JPH0661827A JP H0661827 A JPH0661827 A JP H0661827A JP 20897492 A JP20897492 A JP 20897492A JP 20897492 A JP20897492 A JP 20897492A JP H0661827 A JPH0661827 A JP H0661827A
Authority
JP
Japan
Prior art keywords
voltage
fet
channel fet
turned
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20897492A
Other languages
Japanese (ja)
Other versions
JP3181387B2 (en
Inventor
Hiroyuki Kadowaki
門脇広幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP20897492A priority Critical patent/JP3181387B2/en
Priority to US08/007,143 priority patent/US5687001A/en
Priority to CA002087885A priority patent/CA2087885C/en
Priority to CA002417125A priority patent/CA2417125C/en
Priority to EP99120972A priority patent/EP0982928A3/en
Priority to EP93100998A priority patent/EP0552803B1/en
Priority to DE69329350T priority patent/DE69329350T2/en
Publication of JPH0661827A publication Critical patent/JPH0661827A/en
Priority to US08/420,308 priority patent/US5541542A/en
Application granted granted Critical
Publication of JP3181387B2 publication Critical patent/JP3181387B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To attain high speed and to allow the circuit to high-voltage drive by devising the circuit such that an equivalent 2-terminal element shows a constant voltage characteristic in the rising state for the high speed processing and shows a constant resistance in the falling state so as to divide a voltage applied to a drive element. CONSTITUTION:In the rising state where a P-channel FET 21 is turned on and an N-channel FET 20 is turned off, a P-channel FET 22 is simultaneously turned on. Thus, an output resistance is only an ON-resistance of the FETs 21, 22 and a steep rising characteristic is obtained. In the case of a capacitive load, an output current is decreased, an output voltage is increased accordingly, a source-drain voltage of the FET 22 is decreased and when the voltage is less than a threshold voltage, the FET 22 is turned off. Then, the output voltage rises by a time constant depending on a resistance R2+R3 and a load capacitance. On the other hand, when the FET 21 is turned off, the FET 20 is turned on, since the FET 22 is turned off, the voltage applied to the FETs 21, 22 is divided by resistors R1, R2, R3 to allow the circuit to cope with high voltage drive.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は電界効果トランジスタ
（ＦＥＴ）を用いた相補型駆動回路に係わり、特に高速
動作が可能なイオンプリンタ等の容量性負荷用の高耐圧
駆動回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary drive circuit using a field effect transistor (FET), and more particularly to a high voltage drive circuit for a capacitive load such as an ion printer capable of high speed operation.

【０００２】[0002]

【従来の技術】従来、ＦＥＴを用いた負荷駆動回路が使
用されている。図８は相補型ＦＥＴを用いた駆動回路を
示す図で、ＮチャンネルＦＥＴ１とＰチャンネルＦＥＴ
２を直列に接続し、ゲート入力として、例えば０Ｖまた
は１５Ｖが加えられる。ＰチャンネルＦＥＴ２のゲート
にはレベルシフタ３が接続され、０Ｖ、１５ＶをＰチャ
ンネルＦＥＴ２のＯＮ／ＯＦＦ制御信号レベルに変換す
るようにしている。そして、０Ｖと１５Ｖのゲート入力
により、ＮチャンネルＦＥＴ１とＰチャンネルＦＥＴ２
を交互にＯＮ／ＯＦＦさせてＬＯＷレベルとＨＩＧＨレ
ベルの出力を得るようにしている。2. Description of the Related Art Conventionally, load drive circuits using FETs have been used. FIG. 8 is a diagram showing a driving circuit using a complementary FET, which is an N-channel FET 1 and a P-channel FET.
Two are connected in series and 0 V or 15 V, for example, is applied as a gate input. A level shifter 3 is connected to the gate of the P-channel FET 2 so as to convert 0V and 15V into ON / OFF control signal levels of the P-channel FET 2. And, by the gate input of 0V and 15V, N channel FET1 and P channel FET2
Are alternately turned on / off to obtain LOW level and HIGH level outputs.

【０００３】図９は抵抗負荷を用いた駆動回路を示す図
で、図９（ａ）に示すようにＮチャンネルＦＥＴ４のド
レイン側に抵抗Ｒを接続したものである。ゲート入力が
１５ＶのときＦＥＴ４がＯＮして出力は０、ゲート入力
が０ＶのときＦＥＴ４がＯＦＦとなりＬＯＷレベルとＨ
ＩＧＨレベルの出力を得るようにしている。FIG. 9 is a diagram showing a drive circuit using a resistance load. As shown in FIG. 9A, a resistor R is connected to the drain side of the N-channel FET 4. When the gate input is 15V, the FET4 is turned on and the output is 0. When the gate input is 0V, the FET4 is turned off and the LOW level and H
The IGH level output is obtained.

【０００４】図１０はＮチャンネルＦＥＴをトーテンポ
ール接続した例を示す図で、破線で示す図９（ａ）の抵
抗負荷型の回路にバッファを設けた形になっている。こ
の回路ではオフバッファ８により出力電流が大きくとれ
るととともに、立ち上がりを急峻にすることができる。FIG. 10 is a diagram showing an example in which N-channel FETs are connected to the totem pole, and a buffer is provided in the resistance load type circuit of FIG. 9A shown by the broken line. In this circuit, a large output current can be obtained by the off-buffer 8 and the rising can be made steep.

【０００５】図１１は耐圧の低いＰチャンネルＦＥＴ１
０、１１を直列に接続した高耐圧用の駆動回路を示す図
で、ＰチャンネルＦＥＴ１１がＯＦＦのとき、Ｐチャン
ネルＦＥＴ１１もＯＦＦであり、ＰチャンネルＦＥＴ１
１がＯＮしたとき、ＰチャンネルＦＥＴもＯＮするよう
に動作する。この回路ではＰチャンネルＦＥＴ１０、１
１が直列に接続されているため高耐圧化できる。FIG. 11 shows a P-channel FET 1 having a low breakdown voltage.
FIG. 3 is a diagram showing a high breakdown voltage drive circuit in which 0 and 11 are connected in series. When the P channel FET 11 is OFF, the P channel FET 11 is also OFF, and the P channel FET 1
When 1 is turned on, the P-channel FET also operates so as to be turned on. In this circuit, P-channel FETs 10 and 1
Since 1s are connected in series, high breakdown voltage can be achieved.

【０００６】[0006]

【発明が解決しようとする課題】図８に示すものは基本
的構成の駆動回路であるが、耐圧が３００Ｖ以上のＰチ
ャンネルＦＥＴの入手が現在では困難なため高電圧用駆
動回路としては不向きである。FIG. 8 shows a drive circuit having a basic structure, but it is currently difficult to obtain a P-channel FET having a withstand voltage of 300 V or more, and therefore it is not suitable as a drive circuit for high voltage. is there.

【０００７】図９に示すものは、出力波形の立ち下がり
については高速動作が可能であるが、立ち上がりについ
ては、図９（ｂ）に示すように抵抗Ｒの値と出力負荷に
依存するため一般的には良くない。また、立ち上がり改
善のため、Ｒの値を小さくすると、ＮチャンネルＦＥＴ
４がＯＮしたときの電流が増大し、消費電力が増大して
しまう。The one shown in FIG. 9 is capable of high-speed operation at the falling edge of the output waveform, but the rising edge generally depends on the value of the resistor R and the output load as shown in FIG. 9 (b). Is not good. In addition, if the value of R is reduced to improve the start-up, the N-channel FET
When 4 is turned on, the current increases and power consumption increases.

【０００８】図１０に示すものは、大容量負荷のときに
は有利であるが、ＦＥＴのゲート入力容量と同程度の容
量性負荷では図９の抵抗負荷型と同様の問題点が生ず
る。つまり、ＮチャンネルＦＥＴ８を高速に動作させる
には、抵抗Ｒの値を小さくする必要があり、そうすると
消費電力が増大してしまう。The structure shown in FIG. 10 is advantageous for a large capacity load, but a capacitive load of the same level as the gate input capacity of the FET causes the same problems as those of the resistance load type shown in FIG. That is, in order to operate the N-channel FET 8 at high speed, it is necessary to reduce the value of the resistor R, which increases power consumption.

【０００９】図１１に示すものは、ＰチャンネルＦＥＴ
を直列に接続しているので、高耐圧化は可能であるが、
抵抗ＲとＦＥＴのゲート容量に起因する時定数により高
速動作させることができず、高速化するためにＲを小さ
くすると、図９の回路の場合と同様にＮチャンネルＦＥ
Ｔ９がＯＮしたときの電流が増大し、消費電力が増大し
てしまう。FIG. 11 shows a P-channel FET.
Since it is connected in series, high breakdown voltage is possible,
It is not possible to operate at high speed due to the time constant due to the resistance R and the gate capacitance of the FET, and if R is made small in order to increase the speed, the N channel FE becomes similar to the case of the circuit of FIG.
The current when T9 is turned on increases, and power consumption increases.

【００１０】本発明は上記課題を解決するためもので、
ＰチャンネルＦＥＴを使用し、高速動作可能であるとと
もに、駆動電圧を高めることができる容量性負荷用高耐
圧駆動回路を提供することを目的とする。The present invention is to solve the above-mentioned problems.
An object of the present invention is to provide a high breakdown voltage drive circuit for a capacitive load, which uses a P-channel FET and can operate at high speed and can increase the drive voltage.

【００１１】[0011]

【課題を解決するための手段】本発明は、Ｐチャンネル
及びＮチャンネルＦＥＴ駆動素子を直列接続し、交互に
ＯＮ／ＯＦＦ制御して容量性負荷を駆動する相補型駆動
回路において、Ｐチャンネル及びＮチャンネルＦＥＴ駆
動素子の少なくとも一方のソース・ドレイン間に抵抗を
接続するとともに、ＰチャンネルＦＥＴ駆動素子とＮチ
ャンネルＦＥＴ駆動素子間に一定値以上の電流でＯＮし
て定電圧特性を示し、一定値以下の電流でＯＦＦして定
抵抗となる等価的２端子素子を１つ以上、各ＦＥＴ駆動
素子の少なくとも一方に直列接続したことをことを特徴
とする。SUMMARY OF THE INVENTION The present invention is a complementary drive circuit in which P-channel and N-channel FET drive elements are connected in series and alternately turned ON / OFF to drive a capacitive load. A resistor is connected between at least one of the source and drain of the channel FET drive element, and a constant voltage characteristic is exhibited by turning on the P-channel FET drive element and the N-channel FET drive element with a current of a certain value or more, and below a certain value. It is characterized in that one or more equivalent two-terminal elements that become OFF and become a constant resistance by the current of 1 are connected in series to at least one of the FET driving elements.

【００１２】また、本発明は、等価的２端子素子は、ド
レイン・ゲート間及びゲート・ソース間にそれぞれ抵抗
を接続したＦＥＴ、または抵抗を並列に接続したガス入
り放電管、または抵抗を並列に接続した定電圧ダイオー
ドからなることを特徴とする。According to the present invention, the equivalent two-terminal element is an FET in which a resistor is connected between the drain and the gate and a gate and the source, a gas-filled discharge tube in which the resistor is connected in parallel, or a resistor in parallel. It is characterized by consisting of a connected constant voltage diode.

【００１３】[0013]

【作用】本発明は相補型ＦＥＴ駆動回路の各駆動素子の
少なくとも一方に、一定値以上の電流でＯＮして定電圧
特性を示し、一定値以下の電流でＯＦＦして定抵抗とな
る等価的２端子素子を１つ以上直列接続し、立ち上がり
時には等価的２端子素子が定電圧特性を示すようにして
高速化し、立ち下がり時には等価的２端子素子が定抵抗
となるようにして、駆動素子にかかる電圧を分圧するこ
とにより、高速化を図るとともに高電圧駆動することが
可能となる。According to the present invention, at least one of the driving elements of the complementary FET driving circuit is turned on at a current of a certain value or more to exhibit a constant voltage characteristic, and is turned off at a current of a certain value or less to become a constant resistance. One or more two-terminal elements are connected in series, the equivalent two-terminal elements exhibit constant voltage characteristics at the time of rising to increase the speed, and the equivalent two-terminal elements have a constant resistance at the time of falling so that they become the driving elements. By dividing the voltage, it is possible to achieve high speed and high voltage driving.

【００１４】[0014]

【実施例】図１は本発明の駆動回路の基本構成を示す
図、図２は出力電圧特性を示す図である。図中、２０は
ＮチャンネルＦＥＴ、２１、２２はＰチャンネルＦＥ
Ｔ、Ｓ１はスイッチ、Ｒ１、Ｒ２、Ｒ３は抵抗である。
図１（ａ）はＮチャンネルＦＥＴ２０とＰチャンネルＦ
ＥＴ２１を直列に接続した相補型の駆動回路で、Ｐチャ
ンネルＦＥＴ２１のソース・ドレイン間に抵抗Ｒ１を接
続するとともに、ＰチャンネルＦＥＴ２１のドレインに
抵抗Ｒ２を接続し、スイッチＳ１で抵抗Ｒ２を短絡可能
にしたものである。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing the basic structure of a drive circuit of the present invention, and FIG. 2 is a diagram showing output voltage characteristics. In the figure, 20 is an N channel FET, 21 and 22 are P channel FEs.
T and S1 are switches, and R1, R2 and R3 are resistors.
FIG. 1A shows an N-channel FET 20 and a P-channel F.
In a complementary drive circuit in which ET21 is connected in series, a resistor R1 is connected between the source and drain of the P-channel FET21, a resistor R2 is connected to the drain of the P-channel FET21, and the resistor R2 can be short-circuited by the switch S1. It was done.

【００１５】先ず、図１（ａ）においてスイッチＳ１を
開放して駆動させた場合について説明すると、Ｐチャン
ネルＦＥＴ２１がＯＮ時にはＲ１は短絡されるので出力
抵抗はＲ２のみとなり、一方、ＮチャンネルＦＥＴ２０
ＯＮ（ＰチャンネルＦＥＴ２１ＯＦＦ）時には、Ｐチャ
ンネルＦＥＴ２１の電圧はＲ１／（Ｒ１＋Ｒ２）となる
ので低耐圧のＦＥＴでも対応可能となる。したがって、
Ｒ２を小さくすれば立ち上がりを速くすることができる
が、このときＰチャンネルＦＥＴ２１にかかる電圧が大
きくなってしまうため、それほどＲ２は小さくできな
い。そこで、ＰチャンネルＦＥＴ２１がＯＮ時にはスイ
ッチＳ１を閉じ、ＮチャンネルＦＥＴがＯＮ時にはスイ
ッチＳ１を開放するようにすれば、立ち上がりを速くす
るとともに、ＰチャンネルＦＥＴにかかる電圧も小さく
して耐圧を上げることが可能である。First, the case where the switch S1 is opened and driven in FIG. 1A will be described. When the P-channel FET 21 is ON, R1 is short-circuited so that the output resistance is only R2, while the N-channel FET 20 is on.
When ON (P-channel FET 21 OFF), the voltage of the P-channel FET 21 becomes R1 / (R1 + R2), so that a low breakdown voltage FET can be used. Therefore,
If R2 is made smaller, the rise can be made faster, but at this time, the voltage applied to the P-channel FET 21 becomes large, so R2 cannot be made so small. Therefore, if the switch S1 is closed when the P-channel FET 21 is ON and the switch S1 is opened when the N-channel FET is ON, the rise speed is increased and the voltage applied to the P-channel FET is reduced to increase the breakdown voltage. It is possible.

【００１６】図１（ａ）に示す回路を具体化したものを
図１（ｂ）に示す。図１（ｂ）はスイッチＳ１と抵抗Ｒ
２からなる回路を、ドレイン・ゲート間及びゲート・ソ
ース間にそれぞれ抵抗Ｒ２、Ｒ３を接続したＦＥＴで実
現したものである。すなわち、ＰチャンネルＦＥＴ２１
ＯＮ、ＮチャンネルＦＥＴ２０ＯＦＦの立ち上がり時に
は同時にＰチャンネルＦＥＴ２２がＯＮとなるので、出
力抵抗はＰチャンネルＦＥＴ２１、２２のＯＮ抵抗のみ
となり、図２に示すように、急峻な立ち上がり特性とな
る。そして容量負荷の場合、出力電流が減少してそれに
追随して出力電圧が大きくなるので、ＰチャンネルＦＥ
Ｔ２２のソース・ドレイン間にかかる電圧が小さくな
り、この電圧があるしきい値以下になるとＯＦＦし、以
後出力電圧は抵抗（Ｒ２＋Ｒ３）と負荷容量で決まる時
定数で上昇し、図２の特性Ａのようなカーブとなる。な
お、ＦＥＴ２２が無い場合には特性Ｂのようなカーブと
なる。A concrete implementation of the circuit shown in FIG. 1A is shown in FIG. FIG. 1B shows a switch S1 and a resistor R.
The circuit composed of 2 is realized by an FET in which resistors R2 and R3 are connected between the drain and the gate and between the gate and the source, respectively. That is, the P-channel FET 21
Since the P-channel FET 22 is turned ON at the same time when the ON and N-channel FETs 20 rise, the output resistance is only the ON resistance of the P-channel FETs 21 and 22, and a steep rise characteristic is obtained as shown in FIG. In the case of a capacitive load, the output current decreases and the output voltage increases accordingly, so that the P-channel FE
When the voltage applied between the source and drain of T22 becomes small and this voltage becomes below a certain threshold value, it turns off, and thereafter the output voltage rises with the time constant determined by the resistance (R2 + R3) and the load capacitance. It becomes a curve like. In addition, when the FET 22 is not provided, a curve like the characteristic B is obtained.

【００１７】一方、ＰチャンネルＦＥＴ２１がＯＦＦ、
ＮチャンネルＦＥＴ２０がＯＮになると、Ｐチャンネル
ＦＥＴ２２もＯＦＦするので、ＰチャンネルＦＥＴ２
１、２２にかかる電圧は抵抗Ｒ１、Ｒ２、Ｒ３で分圧さ
れ、高電圧駆動に対応することができる。On the other hand, the P-channel FET 21 is turned off,
When the N-channel FET 20 turns on, the P-channel FET 22 also turns off.
The voltage applied to Nos. 1 and 22 is divided by the resistors R1, R2, and R3, and high voltage driving can be supported.

【００１８】図３（図１（ｂ）の回路）に示すように、
電源電圧を５００Ｖ、Ｒ１＝３００ｋΩ、Ｒ２＝１．６
ｋΩ、Ｒ３＝２００ｋΩとしたときの端子ＴＰ１の電圧
（抵抗Ｒ１の両端の電圧）、端子ＴＰ２における電圧
（出力端子とグラウンド間の電圧）を図４（ａ）、
（ｂ）（横軸１目盛り１ｍｓ、縦軸１目盛り１００Ｖ）
に、また、図４（ｂ）に示す端子ＴＰ２における電圧波
形の立ち上がりの拡大波形を図５（横軸１目盛り２５μ
ｓ、縦軸１目盛り１００Ｖ）に示す。ＰチャンネルＦＥ
Ｔ２１で３００Ｖ、ＰチャンネルＦＥＴ２２で２００Ｖ
分担し、立ち上がりの急峻な出力電圧特性が得らている
ことが分かる。As shown in FIG. 3 (circuit of FIG. 1B),
Power supply voltage is 500V, R1 = 300kΩ, R2 = 1.6
FIG. 4A shows the voltage at the terminal TP1 (voltage across the resistor R1) and the voltage at the terminal TP2 (voltage between the output terminal and ground) when kΩ and R3 = 200 kΩ.
(B) (horizontal axis 1 scale 1 ms, vertical axis 1 scale 100 V)
In addition, the enlarged waveform of the rising of the voltage waveform at the terminal TP2 shown in FIG. 4B is shown in FIG.
s, vertical axis 1 scale 100V). P channel FE
300V for T21, 200V for P-channel FET22
It can be seen that the output voltage characteristics with a steep rise are obtained by sharing.

【００１９】図６は本発明の他の実施例を説明するため
の図である。本実施例は、低圧ＮチャンネルＦＥＴ２０
を使用して高耐圧化を図るもので、ＮチャンネルＦＥＴ
２０のソース・ドレイン間に抵抗Ｒ４を接続するととも
に、ＮチャンネルＦＥＴ２０のドレインにソース・ゲー
ト間およびゲート・ドレイン間に抵抗Ｒ２´、Ｒ３´を
接続したＮチャンネルＦＥＴ２３を接続する。FIG. 6 is a diagram for explaining another embodiment of the present invention. This embodiment is a low voltage N-channel FET 20.
N-channel FET for high withstand voltage using
A resistor R4 is connected between the source and the drain of the N channel FET 20, and an N channel FET 23 in which the resistors R2 'and R3' are connected between the source and the gate and between the gate and the drain is connected to the drain of the N channel FET 20.

【００２０】ＰチャンネルＦＥＴ２１ＯＮ、Ｎチャンネ
ルＦＥＴ２０ＯＦＦの立ち上がり時には出力抵抗はＰチ
ャンネルＦＥＴ２１のＯＮ抵抗のみとなり、急峻な立ち
上がり特性となる。このときＮチャンネルＦＥＴ２０、
ＮチャンネルＦＥＴ２３にかかる電圧は抵抗Ｒ２´、Ｒ
３´、Ｒ４で分圧される。At the rising of the P-channel FET 21ON and N-channel FET 20OFF, the output resistance is only the ON resistance of the P-channel FET 21 and has a steep rising characteristic. At this time, the N-channel FET 20,
The voltage applied to the N-channel FET 23 is the resistance R2 ', R
It is divided by 3'and R4.

【００２１】一方、ＰチャンネルＦＥＴ２１がＯＦＦ、
ＮチャンネルＦＥＴ２０がＯＮになる立ち下がり時は、
ＮチャンネルＦＥＴ２３もＯＮするので急峻に立ち下が
り、容量負荷の場合、放電電流が減少してそれに追随し
て出力電圧が小さくなるので、ＮチャンネルＦＥＴ２３
のソース・ドレイン間にかかる電圧が小さくなり、この
電圧があるしきい値以下になるとＯＦＦし、以後出力電
圧は抵抗（Ｒ２´＋Ｒ３´）と負荷容量で決まる時定数
で減少することになる。このように、ＰチャンネルＦＥ
Ｔ２１ＯＮ時にＮチャンネルＦＥＴ２０、Ｎチャンネル
ＦＥＴ２３にかかる電圧は抵抗Ｒ２´、Ｒ３´、Ｒ４で
分圧されるので、高電圧駆動に対応することができる。On the other hand, the P-channel FET 21 is turned off,
At the fall when the N-channel FET 20 turns on,
Since the N-channel FET 23 is also turned on, it falls sharply, and in the case of a capacitive load, the discharge current decreases and the output voltage decreases accordingly, so the N-channel FET 23
When the voltage applied between the source and drain of the device becomes smaller and becomes lower than a certain threshold value, it is turned off, and thereafter the output voltage decreases with a time constant determined by the resistance (R2 ′ + R3 ′) and the load capacitance. In this way, P channel FE
Since the voltage applied to the N-channel FET 20 and the N-channel FET 23 when T21 is ON is divided by the resistors R2 ', R3', and R4, high voltage driving can be supported.

【００２２】図７は本発明の他の実施例を示す図であ
る。本実施例は、ＮチャンネルＦＥＴ２０、Ｐチャンネ
ルＦＥＴ２１の両方にそのソース・ドレイン間に抵抗を
接続するとともに、ＮチャンネルＦＥＴ２０及びＰチャ
ンネルＦＥＴ２１のドレイン側にソース・ゲート間およ
びゲート・ドレイン間に抵抗を接続したＦＥＴを接続し
たものである。すなわち、ＰチャンネルＦＥＴ２１のド
レインには図１（ｂ）と同様に、ドレイン・ゲート間及
びゲート・ソース間にそれぞれ抵抗Ｒ２、Ｒ３を接続し
たＰチャンネルＦＥＴ２２を、ＮチャンネルＦＥＴ２０
のドレインには図６と同様に、ソース・ゲート間および
ゲート・ドレイン間に抵抗Ｒ２´、Ｒ３´を接続したＮ
チャンネルＦＥＴ２３を接続する。FIG. 7 is a diagram showing another embodiment of the present invention. In this embodiment, resistors are connected between the source and drain of both the N-channel FET 20 and the P-channel FET 21, and resistors are connected between the source and the gate and between the gate and the drain on the drain sides of the N-channel FET 20 and the P-channel FET 21. The connected FET is connected. That is, similarly to FIG. 1B, the drain of the P-channel FET 21 includes the P-channel FET 22 in which the resistors R2 and R3 are connected between the drain and the gate and between the gate and the source, respectively.
Similarly to FIG. 6, the drain of N is connected with resistors R2 ′ and R3 ′ between the source and the gate and between the gate and the drain.
The channel FET 23 is connected.

【００２３】このような構成とすることにより、Ｎチャ
ンネルＦＥＴ２０、ＰチャンネルＦＥＴ２１のどちらが
ＯＮになったときでも他方にかかる電圧は直列に入った
抵抗により分圧されるので低圧のＮチャンネルＦＥＴ及
びＰチャンネルＦＥＴを使用して高電圧駆動することが
でき、同時に立ち上がり時、立ち下がり時の急峻性を維
持することが可能である。With such a configuration, when either the N-channel FET 20 or the P-channel FET 21 is turned on, the voltage applied to the other is divided by the resistance in series, so the low-voltage N-channel FET and P It is possible to drive a high voltage by using a channel FET, and at the same time, it is possible to maintain steepness at the time of rising and falling.

【００２４】なお、上記各実施例ではＰチャンネルＦＥ
Ｔ側、ＮチャンネルＦＥＴ側にソース・ゲート間および
ゲート・ドレイン間を抵抗接続したＦＥＴを１個設けて
いるが、これを複数個直列に接続し、それぞれＯＦＦす
る両端の電圧値（しきい値電圧）を変えるようちすれ
ば、立ち上がり時にはすべて一斉にＯＮし、出力電圧が
上昇するにつれてＦＥＴが１つずつＯＦＦして階段状に
電源電圧またはグランドレベルに接近する出力波形が得
られ、より高速化と高耐圧化を実現することが可能とな
る。In the above embodiments, the P channel FE is used.
One FET with resistance connection between the source and gate and between the gate and drain is provided on the T side and the N channel FET side, but a plurality of these FETs are connected in series to turn off each voltage value (threshold value By changing the voltage), all of them are turned on at the same time at the time of rising, and the FETs are turned off one by one as the output voltage rises, so that an output waveform approaching the power supply voltage or the ground level in a stepwise manner can be obtained. And higher breakdown voltage can be realized.

【００２５】また、上記説明では図１（ｂ）のスイッチ
Ｓ１と抵抗Ｒ２とを、ドレイン・ゲート間及びゲート・
ソース間にそれぞれ抵抗Ｒ２、Ｒ３を接続したＦＥＴで
実現するようにしたが、この素子は一定値以上の電流で
ＯＮして定電圧特性を示し、一定値以下の電流でＯＦＦ
して定抵抗となる等価的２端子素子を構成しており、こ
の等価的２端子素子としては、抵抗を並列に接続した定
電圧放電管や表示用ネオンランプなどのガス入り放電
管、或いは抵抗を並列に接続した定電圧ダイオード等で
実現するようにしても同様な効果が得られる。In the above description, the switch S1 and the resistor R2 shown in FIG.
This is realized by FETs in which resistors R2 and R3 are connected between sources, but this element turns on at a current above a certain value and exhibits constant voltage characteristics, and turns off at a current below a certain value.
To form a constant resistance equivalent two-terminal element. As the equivalent two-terminal element, a constant voltage discharge tube in which resistors are connected in parallel, a gas-filled discharge tube such as a neon lamp for display, or a resistance is used. The same effect can be obtained by implementing a constant voltage diode or the like connected in parallel.

【００２６】[0026]

【発明の効果】以上のように本発明によれば、入手が容
易な低耐圧のＦＥＴを用いた相補型駆動回路を使用し
て、立ち上がり特性を急峻にすると共に、高電圧駆動を
行うことが可能な容量性負荷用高耐圧駆動回路を得るこ
とが可能となる。As described above, according to the present invention, it is possible to make the rising characteristic steep and drive a high voltage by using a complementary drive circuit using an easily available low breakdown voltage FET. It is possible to obtain a possible high-voltage drive circuit for capacitive load.

【図面の簡単な説明】[Brief description of drawings]

【図１】 図１は本発明の駆動回路の基本構成を示す図
である。FIG. 1 is a diagram showing a basic configuration of a drive circuit of the present invention.

【図２】 出力電圧特性を示す図である。FIG. 2 is a diagram showing output voltage characteristics.

【図３】 出力電圧波形を得るための具体的回路図であ
る。FIG. 3 is a specific circuit diagram for obtaining an output voltage waveform.

【図４】 電圧波形を示す図である。FIG. 4 is a diagram showing a voltage waveform.

【図５】 図４の波形の拡大図である。FIG. 5 is an enlarged view of the waveform of FIG.

【図６】 ＮチャンネルＦＥＴの耐圧を上げる具体的回
路図である。FIG. 6 is a specific circuit diagram for increasing the breakdown voltage of an N-channel FET.

【図７】 Ｎチャンネル及びＰチャンネルＦＥＴの耐圧
を上げる具体的回路図である。FIG. 7 is a specific circuit diagram for increasing the breakdown voltage of N-channel and P-channel FETs.

【図８】 従来の相補型駆動回路図である。FIG. 8 is a conventional complementary driving circuit diagram.

【図９】 抵抗負荷型の駆動回路図である。FIG. 9 is a resistance load type drive circuit diagram.

【図１０】 トーテンポール接続型の駆動回路図であ
る。FIG. 10 is a drive circuit diagram of a totem pole connection type.

【図１１】 従来の高耐圧駆動回路図である。FIG. 11 is a conventional high breakdown voltage drive circuit diagram.

【符号の説明】[Explanation of symbols]

２０、２３…ＮチャンネルＦＥＴ、２１、２２…Ｐチャ
ンネルＦＥＴ、Ｓ１…スイッチ、Ｒ１、Ｒ２、Ｒ３、Ｒ
２´、Ｒ３´、Ｒ４…抵抗。20, 23 ... N-channel FET, 21, 22 ... P-channel FET, S1 ... Switch, R1, R2, R3, R
2 ', R3', R4 ... Resistance.

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 Ｐチャンネル及びＮチャンネルＦＥＴ駆
動素子を直列接続し、交互にＯＮ／ＯＦＦ制御して容量
性負荷を駆動する相補型駆動回路において、Ｐチャンネ
ル及びＮチャンネルＦＥＴ駆動素子の少なくとも一方の
ソース・ドレイン間に抵抗を接続するとともに、Ｐチャ
ンネルＦＥＴ駆動素子とＮチャンネルＦＥＴ駆動素子間
に一定値以上の電流でＯＮして定電圧特性を示し、一定
値以下の電流でＯＦＦして定抵抗となる等価的２端子素
子を１つ以上、各ＦＥＴ駆動素子の少なくとも一方に直
列接続したことを特徴とする容量性負荷用高耐圧駆動回
路。1. A complementary driving circuit in which P-channel and N-channel FET driving elements are connected in series and alternately controlled ON / OFF to drive a capacitive load, and at least one of P-channel and N-channel FET driving elements is provided. A resistor is connected between the source and drain, and the P-channel FET driving element and the N-channel FET driving element are turned on with a current of a certain value or more to show constant voltage characteristics, and turned off with a current of a certain value or less to have a constant resistance. A high withstand voltage drive circuit for a capacitive load, characterized in that one or more equivalent two-terminal elements are connected in series to at least one of the FET drive elements. 【請求項２】 請求項１記載の駆動回路において、等価
的２端子素子は、ドレイン・ゲート間及びゲート・ソー
ス間にそれぞれ抵抗を接続したＦＥＴからなることを特
徴とする容量性負荷用高耐圧駆動回路。2. The drive circuit according to claim 1, wherein the equivalent two-terminal element is an FET having a resistance connected between the drain and the gate and between the gate and the source, respectively. Drive circuit. 【請求項３】 請求項１記載の駆動回路において、等価
的２端子素子は、抵抗を並列に接続したガス入り放電管
からなることを特徴とする容量性負荷用高耐圧駆動回
路。3. The high withstand voltage drive circuit for a capacitive load according to claim 1, wherein the equivalent two-terminal element comprises a gas-filled discharge tube in which resistors are connected in parallel. 【請求項４】 請求項１記載の駆動回路において、等価
的２端子素子は、抵抗を並列に接続した定電圧ダイオー
ドからなることを特徴とする容量性負荷用高耐圧駆動回
路。4. The high withstand voltage drive circuit for a capacitive load according to claim 1, wherein the equivalent two-terminal element comprises a constant voltage diode in which resistors are connected in parallel.
JP20897492A 1992-01-22 1992-08-05 High withstand voltage drive circuit for capacitive load Expired - Fee Related JP3181387B2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP20897492A JP3181387B2 (en) 1992-08-05 1992-08-05 High withstand voltage drive circuit for capacitive load
US08/007,143 US5687001A (en) 1992-01-22 1993-01-21 Halftone image ion printer
CA002417125A CA2417125C (en) 1992-01-22 1993-01-22 Halftone image device and its driving circuit
EP99120972A EP0982928A3 (en) 1992-01-22 1993-01-22 Halftone image device and its driving circuit
CA002087885A CA2087885C (en) 1992-01-22 1993-01-22 Halftone image device and its driving circuit
EP93100998A EP0552803B1 (en) 1992-01-22 1993-01-22 Halftone image recording device
DE69329350T DE69329350T2 (en) 1992-01-22 1993-01-22 Halftone imager
US08/420,308 US5541542A (en) 1992-01-22 1995-04-11 Halftone image device and its driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20897492A JP3181387B2 (en) 1992-08-05 1992-08-05 High withstand voltage drive circuit for capacitive load

Publications (2)

Publication Number Publication Date
JPH0661827A true JPH0661827A (en) 1994-03-04
JP3181387B2 JP3181387B2 (en) 2001-07-03

Family

ID=16565247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20897492A Expired - Fee Related JP3181387B2 (en) 1992-01-22 1992-08-05 High withstand voltage drive circuit for capacitive load

Country Status (1)

Country Link
JP (1) JP3181387B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100860688B1 (en) * 2002-03-26 2008-09-26 히다찌 플라즈마 디스플레이 가부시키가이샤 Electrode drive circuit of plasma display panel and plasma display apparatus
JP2009518730A (en) * 2005-12-08 2009-05-07 エヌエックスピー ビー ヴィ High voltage power switch using low voltage transistors
JP2020061820A (en) * 2018-10-05 2020-04-16 ローム株式会社 Drive device, insulation-type dc/dc converter, ac/dc converter, power supply adaptor, and electrical apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100860688B1 (en) * 2002-03-26 2008-09-26 히다찌 플라즈마 디스플레이 가부시키가이샤 Electrode drive circuit of plasma display panel and plasma display apparatus
JP2009518730A (en) * 2005-12-08 2009-05-07 エヌエックスピー ビー ヴィ High voltage power switch using low voltage transistors
JP4756138B2 (en) * 2005-12-08 2011-08-24 エスティー‐エリクソン、ソシエテ、アノニム High voltage power switch using low voltage transistors
JP2020061820A (en) * 2018-10-05 2020-04-16 ローム株式会社 Drive device, insulation-type dc/dc converter, ac/dc converter, power supply adaptor, and electrical apparatus

Also Published As

Publication number Publication date
JP3181387B2 (en) 2001-07-03

Similar Documents

Publication Publication Date Title
US6686899B2 (en) Display device having an improved voltage level converter circuit
US10790811B2 (en) Cascaded bootstrapping GaN power switch and driver
EP2706664A2 (en) Level shift device
KR19980047305A (en) Level shift circuit for liquid crystal display
KR100373941B1 (en) Display device, its driving circuit and sampling circuit
JP2000040924A (en) Constant current drive circuit
JP3702159B2 (en) Semiconductor integrated circuit device
US4219743A (en) Buffer circuit
US5057721A (en) Level shift circuit for controlling a driving circuit
EP0351820B1 (en) Output circuit
US5138186A (en) Solid state switch with last state memory
US4717845A (en) TTL compatible CMOS input circuit
US4967100A (en) Capacitive load driving apparatus
KR19990078102A (en) Voltage level converters
JPH098627A (en) Two-terminal to plurally common terminal matrix switch
JP3181387B2 (en) High withstand voltage drive circuit for capacitive load
JPH09230829A (en) Output circuit for source driver
KR910007260A (en) Devices to Reduce Spike Currents in CMOS Switch Drivers
EP1089433B1 (en) A method and apparatus for level shifting
JPH11308091A (en) Signal level conversion circuit
JPS61166223A (en) Composition type switch circuit
US4571527A (en) VFET Driving circuits for plasma panel display systems
EP1160983A2 (en) Differential type logic circuit
JP2766859B2 (en) Driving method of insulated gate thin film transistor logic circuit
JP2003338740A (en) High breakdown voltage switching circuit

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees