JPH0642546B2 - MOS semiconductor device - Google Patents
MOS semiconductor deviceInfo
- Publication number
- JPH0642546B2 JPH0642546B2 JP62113385A JP11338587A JPH0642546B2 JP H0642546 B2 JPH0642546 B2 JP H0642546B2 JP 62113385 A JP62113385 A JP 62113385A JP 11338587 A JP11338587 A JP 11338587A JP H0642546 B2 JPH0642546 B2 JP H0642546B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- insulating film
- substrate
- concentration
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Description
【発明の詳細な説明】 〈産業上の利用分野〉 本発明はＭＯＳ型半導体装置に関し、特には接合リーク
電流の少ないＭＯＳ型半導体装置に関する。The present invention relates to a MOS type semiconductor device, and more particularly to a MOS type semiconductor device having a small junction leak current.
〈従来の技術〉 電気的に書き込み消去が可能な読み出し専用メモリであ
るEEPROMや半導体上の容量に電荷を蓄えることで記憶を
行なうDRAM等のメモリセルには、半導体基板の空乏化を
防ぐために半導体基板に形成されたドレイン領域と素子
分離絶縁領域とに連続し、半導体基板上に絶縁膜を介し
て形成されたゲート領域下を覆う領域にドレイン領域と
同一導電型の不純物領域が形成されている。第３図はEE
PROMとして用いられるＭＯＳトランジスタの一部断面図
である。ｐ型Ｓｉ基板１にはｎ型不純物を拡散してドレ
イン領域２が形成され、また前記基板１の素子分離領域
にはフィールド絶縁膜３が形成される。ドレイン領域２
とフィールド絶縁膜３の間の基板１上には第１のゲート
絶縁膜４が形成され、該第１のゲート絶縁膜４上にはフ
ローティングゲート５、層間絶縁膜６及びコントロール
ゲート７が順次形成され、ゲートをなしている。このゲ
ートやドレイン領域２及びフィールド絶縁膜３を含むＳ
ｉ基板１は絶縁膜８で覆われ、保護されている。前記フ
ィールド絶縁膜３直下の基板１にはチャネル・ストッパ
としてｐ＋不純物領域９が形成され、隣接する素子間を
電気的に分離している。更に基板１のゲート直下には、
ｐ＋不純物領域９とドレイン領域２とに両側が隣接、ｎ
型不純物としてＡｓを７×1014cm-2程度注入した高濃度
ｎ＋不純物領域１０が形成され、該不純物領域１０がＳ
ｉ基板１の空乏化を防いでいる。<Prior Art> Memory cells such as EEPROM, which is a read-only memory that can be electrically written and erased, and DRAM, which stores data by storing charges in a semiconductor capacitor, are used to prevent depletion of the semiconductor substrate. An impurity region having the same conductivity type as that of the drain region is formed in a region which is continuous with the drain region and the element isolation insulating region formed on the substrate and covers the lower portion of the gate region formed on the semiconductor substrate with an insulating film interposed therebetween. . Figure 3 shows EE
It is a partial cross-sectional view of a MOS transistor used as a PROM. A drain region 2 is formed in the p-type Si substrate 1 by diffusing n-type impurities, and a field insulating film 3 is formed in the element isolation region of the substrate 1. Drain region 2
A first gate insulating film 4 is formed on the substrate 1 between the field insulating film 3 and the field insulating film 3, and a floating gate 5, an interlayer insulating film 6 and a control gate 7 are sequentially formed on the first gate insulating film 4. It is a gate. S including the gate and drain regions 2 and the field insulating film 3
The i substrate 1 is covered and protected by an insulating film 8. A p + impurity region 9 is formed as a channel stopper on the substrate 1 immediately below the field insulating film 3 to electrically separate adjacent elements. Furthermore, directly below the gate of the substrate 1,
Both sides are adjacent to the p + impurity region 9 and the drain region 2, and n
A high-concentration n + impurity region 10 in which As as a type impurity is implanted at about 7 × 10 14 cm -2 is formed.
The depletion of the i substrate 1 is prevented.
〈発明が解決しようとする問題点〉 EEPROM或いはDRAM等の半導体装置に用いられるＭＯＳト
ランジスタのゲート絶縁膜は半導体装置の高集積化・高
密度化に伴って従来に比べ薄くなっている。ところで、
上記第３図からも明らかなように、チャネル・ストッパ
をなすｐ＋不純物領域９と高濃度ｎ＋不純物領域１０と
のＰＮ接合はゲート絶縁膜４下に形成されている。この
ため、ゲート絶縁膜４が薄くなると、リークの発生する
電圧が低下し、使用電圧範囲内のゲート電圧を印加した
時にも前記ＰＮ接合にリーク電流が発生してしまう。リ
ーク電流はEEPROMでは書き込み消去時の電流損失とな
り、DRAMにおいてはメモリ保持特性の悪化の原因とな
る。<Problems to be Solved by the Invention> The gate insulating film of a MOS transistor used in a semiconductor device such as an EEPROM or a DRAM has become thinner than in the past due to higher integration and higher density of the semiconductor device. by the way,
As is clear from FIG. 3, the PN junction between the p + impurity region 9 and the high-concentration n + impurity region 10 forming the channel stopper is formed under the gate insulating film 4. Therefore, when the gate insulating film 4 becomes thin, the voltage at which leakage occurs decreases, and a leakage current occurs at the PN junction even when a gate voltage within the operating voltage range is applied. Leakage current causes a current loss during writing and erasing in EEPROM, and causes deterioration of memory retention characteristics in DRAM.
このリーク電流の発生を抑制させるにはＰＮ接合をより
厚い絶縁膜下に形成するとよい。そこで高濃度ｎ＋不純
物領域１０中のｎ型不純物をより高濃度にし、ｎ型不純
物をより広く拡散させることによってＰＮ接合をフィー
ルド絶縁膜３といったゲート絶縁膜４より厚い絶縁膜下
に形成する方法がある。しかし、この方法ではリーク電
流の発生を抑制することはできるが、第４図に示すよう
にｎ型不純物が高濃度化することによって高濃度ｎ＋不
純物領域１０上の絶縁膜の寿命等の特性が悪化するとい
う問題が生じる。In order to suppress the generation of this leak current, it is advisable to form a PN junction under a thicker insulating film. Therefore, a method of forming a PN junction below the gate insulating film 4 such as the field insulating film 3 by increasing the concentration of the n-type impurity in the high-concentration n + impurity region 10 and diffusing the n-type impurity more widely There is. However, although this method can suppress the generation of leakage current, as shown in FIG. 4, by increasing the concentration of the n-type impurity, the characteristics such as the life of the insulating film on the high concentration n + impurity region 10 can be reduced. A problem that is worse.
〈問題点を解決するための手段〉 本発明は上述する問題点を解決するためになされたもの
で、第１の導電型の半導体基板に形成された第２の導電
型のドレイン領域と、前記半導体基板に形成された素子
分離領域下に形成された第１の導電型のチャネル・スト
ッパ領域とに両端が連続し、且つ前記半導体基板上のゲ
ート絶縁膜及びゲート電極から成るゲート領域下に形成
された高濃度不純物領域は第２の導電型であり、且つ拡
散係数の異なる少なくとも２種の不純物種からなる少な
くとも２重構造を有し、且つ前記チャネル・ストッパ領
域と前記素子分離領域下でＰＮ接合していることを特徴
とするＭＯＳ型半導体装置を提供するものである。<Means for Solving Problems> The present invention has been made to solve the above problems, and includes a second conductivity type drain region formed on a first conductivity type semiconductor substrate, and Both ends are continuous with the first conductivity type channel stopper region formed under the element isolation region formed on the semiconductor substrate, and formed under the gate region formed of the gate insulating film and the gate electrode on the semiconductor substrate. The doped high-concentration impurity region is of the second conductivity type and has at least a double structure composed of at least two kinds of impurity species having different diffusion coefficients, and PN is formed under the channel stopper region and the element isolation region. The present invention provides a MOS type semiconductor device characterized by being joined.
〈作用〉 本発明の如く、半導体基板の空乏化を防ぐための高濃度
不純物領域を拡散係数の異なる少なくとも２種の不純物
種にて形成することにより、空乏化を防ぐに足りる従来
とほぼ同じ不純物量であっても、高濃度不純物領域をよ
り広く形成することが可能になる。<Operation> By forming the high-concentration impurity region for preventing depletion of the semiconductor substrate with at least two kinds of impurity species having different diffusion coefficients as in the present invention, almost the same impurities as in the conventional case sufficient for preventing depletion are formed. Even if the amount is large, the high concentration impurity region can be formed wider.
〈実施例〉 以下、図面を用いて本発明の実施例を説明するが、本発
明はこれに限定されるものではない。<Examples> Examples of the present invention will be described below with reference to the drawings, but the present invention is not limited thereto.
第１図(a)〜(d)は本発明の一実施例の製造プロセスを示
す断面図である。ｐ型Ｓｉ基板１の主面上を洗浄し、該
主面上にＳｉＯ2膜１３を300〜1000Åの厚さに、ＳｉＯ
3Ｎ4膜１２を1000〜2000Åの厚さに順次形成した後、Ｓ
ｉ基板１上の活性領域をレジスト１１で選択的に覆い、
前記レジスト１１をマスクにしてプラズマエッチングを
行なって、第１図(a)の如くＳｉＯ2膜１３とＳｉ3Ｎ4膜
１２とをパターニングする。次いでレジスト１１をマス
クとしてｐ型Ｓｉ基板１に寄生チャネル防止のための硼
素イオンを120ＫｅＶで１×1013cm2注入した後、レジス
ト１１を除去し、Ｓｉ3Ｎ4膜１２をマスクにして950℃
Ｈ2Ｏ雰囲気中で５〜10時間の熱酸化を行なうと、第１
図(b)の如くｐ＋不純物領域９及び0.7〜1.5μｍの膜厚
のフィールド絶縁膜３が形成される。次いで上記Ｓｉ3
Ｎ4膜１２とＳｉＯ2膜１３を除去し、Ｓｉ基板１上を新
たにレジスト１４で選択的に覆い、該レジスト１４をマ
スクとしてＳｉ基板１に砒素及びリンのイオン注入を行
なって、第１及び第２の高濃度ｎ＋不純物領域１５ａ，
ｂを形成する。次に前記レジスト１４を除去した後、第
１図(c)の如く熱酸化法によりＳｉ基板１上に500〜1000
Å程度のゲート絶縁膜４を形成し、該ゲート絶縁膜４上
に電荷注入用の窪みを形成する。このゲート絶縁膜４上
に、ポリシリコンからなるフローティングゲート５と層
間絶縁膜６、及びリンをドープしたポリシリコンからな
るコントロールゲート７を順次形成する。この後、第１
図(d)の如く前記コントロールゲート７をマスクとして
Ｓｉ基板１に砒素を高濃度にイオン注入してドレイン領
域２を形成し、Ｓｉ基板１全面をＰＳＧ等の絶縁膜８で
覆う。この絶縁膜８にコンタクトホール（図示せず）を
形成し、Ａｌ等からなる電極（図示せず）を形成する。1 (a) to 1 (d) are cross-sectional views showing a manufacturing process of an embodiment of the present invention. The main surface of the p-type Si substrate 1 is cleaned, and a SiO 2 film 13 is formed on the main surface to a thickness of 300 to 1000Å.
After sequentially forming the 3 N 4 film 12 to a thickness of 1000 to 2000 Å, S
selectively covering the active region on the i-substrate 1 with a resist 11;
Plasma etching is performed using the resist 11 as a mask to pattern the SiO 2 film 13 and the Si 3 N 4 film 12 as shown in FIG. Then, using the resist 11 as a mask, boron ions for preventing parasitic channels are implanted into the p-type Si substrate 1 at 120 KeV at 1 × 10 13 cm 2 and then the resist 11 is removed. The Si 3 N 4 film 12 is used as a mask for 950 ℃
When thermal oxidation is performed for 5 to 10 hours in an H 2 O atmosphere, the first
As shown in FIG. 6B, the p + impurity region 9 and the field insulating film 3 having a film thickness of 0.7 to 1.5 μm are formed. Then the above Si 3
The N 4 film 12 and the SiO 2 film 13 are removed, the Si substrate 1 is newly covered with a resist 14 selectively, and arsenic and phosphorus ions are implanted into the Si substrate 1 using the resist 14 as a mask. And the second high-concentration n + impurity region 15a,
b is formed. Next, after removing the resist 14, 500-1000 is deposited on the Si substrate 1 by the thermal oxidation method as shown in FIG. 1 (c).
A gate insulating film 4 having a thickness of about Å is formed, and a recess for charge injection is formed on the gate insulating film 4. A floating gate 5 made of polysilicon, an interlayer insulating film 6, and a control gate 7 made of phosphorus-doped polysilicon are sequentially formed on the gate insulating film 4. After this, the first
As shown in FIG. 3D, arsenic is ion-implanted at a high concentration into the Si substrate 1 using the control gate 7 as a mask to form the drain region 2, and the entire surface of the Si substrate 1 is covered with an insulating film 8 such as PSG. A contact hole (not shown) is formed in the insulating film 8 and an electrode (not shown) made of Al or the like is formed.
上述の如く高濃度ｎ＋不純物領域の不純物種として拡散
係数の大きいリンと小さい砒素の２種を用いることによ
り、リンにより第１の高濃度ｎ＋不純物領域１５ａが形
成され、ゲート絶縁膜４より厚いフィールド絶縁膜３の
下で前記第１の高濃度ｎ＋不純物領域１５ａとチャネル
・ストッパ用のｐ＋不純物領域９とによるＰＮ接合が形
成されるため、リーク電流の発生を抑制できる。更に砒
素により第２の高濃度ｎ＋不純物領域１５ｂが従来と同
様に形成され、基板の空乏化を防ぐことが可能になる。By using two large phosphorus and less arsenic diffusion coefficient as an impurity species as described above the high-concentration n + impurity region, the first high concentration n + impurity regions 15a is formed by phosphorus, than the gate insulating film 4 Since a PN junction is formed under the thick field insulating film 3 by the first high-concentration n + impurity region 15a and the p + impurity region 9 for the channel stopper, generation of leak current can be suppressed. Further, the second high-concentration n + impurity region 15b is formed by arsenic as in the conventional case, and it becomes possible to prevent the depletion of the substrate.
上記本実施例において、ｎ型不純物を基板にイオン注入
したが、本発明はこれに限定されるものではなく、拡散
等他の方法であってもよい。Although the n-type impurity is ion-implanted into the substrate in the present embodiment, the present invention is not limited to this, and other methods such as diffusion may be used.
第２図は高濃度ｎ＋不純物領域を形成する際、砒素注入
量を７×1014cm-2にし、リン注入量を変化させた時のＰ
Ｎ接合のリーク電流の変化を表した図である。同図か
ら、リンを注入するとリーク電流が低下することは明ら
かである。また、砒素を７×1014cm-2とリンを１×1014
cm-2とを注入する、つまりｎ型不純物を８×1014cm-2程
度Ｓｉ基板に注入し、高濃度ｎ＋不純物領域を形成して
も、第４図から明らかなように該高濃度ｎ＋不純物領域
上のゲート絶縁膜の寿命は従来とほぼ変わらない。FIG. 2 shows P when the arsenic implantation amount is set to 7 × 10 14 cm -2 and the phosphorus implantation amount is changed when the high-concentration n + impurity region is formed.
It is a figure showing the change of the leak current of N junction. From the figure, it is clear that the injection of phosphorus reduces the leakage current. Also, arsenic is 7 × 10 14 cm -2 and phosphorus is 1 × 10 14 cm 2.
cm −2 , that is, even if a high-concentration n + impurity region is formed by injecting n-type impurities into the Si substrate at about 8 × 10 14 cm −2 , as shown in FIG. The life of the gate insulating film on the n + impurity region is almost the same as the conventional one.
上記本実施例において高濃度ｎ＋不純物領域をなし、拡
散係数の異なるｎ型不純物としてリンと砒素を用いた
が、本発明はこれに限定されるものではなく、リンとア
ンチモンの組合せ、或いはリンと砒素とアンチモンの組
合せであってもよく、また他のｎ型不純物であっても上
記と同様の効果が得られるならば、それを用いてもよ
い。Although phosphorus and arsenic are used as the n-type impurities having the high-concentration n + impurity region and different diffusion coefficients in the present embodiment, the present invention is not limited to this, and a combination of phosphorus and antimony or phosphorus. And arsenic and antimony may be used, and other n-type impurities may be used as long as the same effect as described above can be obtained.
〈発明の効果〉 本発明により、高濃度不純物領域の濃度を増加させるこ
となくＰＮ接合部がフィールド酸化膜下に形成されてい
るので、リーク電流の減少をゲート絶縁膜の特性を悪化
させることなく実施することが可能になる。したがっ
て、本発明は信頼性の高いＭＯＳ型半導体装置の製造に
寄与するものである。<Effects of the Invention> According to the present invention, since the PN junction is formed under the field oxide film without increasing the concentration of the high-concentration impurity region, it is possible to reduce the leakage current without deteriorating the characteristics of the gate insulating film. It becomes possible to carry out. Therefore, the present invention contributes to the manufacture of a highly reliable MOS semiconductor device.
第１図(a)〜(d)は本発明の一実施例の製造プロセスを示
す断面図、第２図はリン注入量に対するリーク電流の変
化を示す図、第３図は従来例を示す断面図、第４図は高
濃度ｎ＋不純物領域をなすｎ＋不純物濃度に対する前記
高濃度ｎ＋不純物領域上のゲート絶縁膜の寿命の変化を
示す図である。 １…ｐ型Ｓｉ基板 ２…ドレイン領域 ３…フィールド
絶縁膜 ４…ゲート絶縁膜 ５…フローティングゲート
６…層間絶縁膜 ７…コントロールゲート ８…絶縁
膜 ９…ｐ＋不純物領域 １５ａ…第１の高濃度ｎ＋不
純物領域 １５ｂ…第２の高濃度ｎ＋不純物領域1 (a) to 1 (d) are cross-sectional views showing a manufacturing process of an embodiment of the present invention, FIG. 2 is a view showing a change in leak current with respect to a phosphorus implantation amount, and FIG. 3 is a cross-sectional view showing a conventional example. FIG. 4 and FIG. 4 are views showing changes in the life of the gate insulating film on the high concentration n + impurity region with respect to the n + impurity concentration forming the high concentration n + impurity region. DESCRIPTION OF SYMBOLS 1 ... P-type Si substrate 2 ... Drain region 3 ... Field insulating film 4 ... Gate insulating film 5 ... Floating gate 6 ... Interlayer insulating film 7 ... Control gate 8 ... Insulating film 9 ... P + impurity region 15a ... 1st high concentration n + impurity region 15b ... second high-concentration n + impurity region
Claims (2)
２の導電型のドレイン領域と前記半導体基板に形成され
た素子分離領域下に形成された第１の導電型のチャネル
・ストッパ領域とに両端が連続し、且つ前記半導体基板
上のゲート絶縁膜及びゲート電極から成るゲート領域下
に形成された高濃度不純物領域は、第２の導電型であ
り、且つ拡散係数の異なる少なくとも２種の不純物種か
らなる少なくとも２重構造を有し、且つ前記チャネル・
ストッパ領域と前記素子分離領域下でＰＮ接合している
ことを特徴とするＭＯＳ型半導体装置。1. A channel stopper of a first conductivity type formed below a drain region of a second conductivity type formed on a semiconductor substrate of a first conductivity type and an element isolation region formed on the semiconductor substrate. The high-concentration impurity region which is continuous with the region at both ends and is formed under the gate region formed of the gate insulating film and the gate electrode on the semiconductor substrate is of the second conductivity type and has at least 2 different diffusion coefficients. The channel has at least a double structure of two impurity species,
A MOS semiconductor device characterized in that a PN junction is formed between the stopper region and the element isolation region.
素及び／またはアンチモンであることを特徴とする特許
請求の範囲第１項記載のＭＯＳ型半導体装置。2. The MOS type semiconductor device according to claim 1, wherein one of the impurity species is phosphorus and the other is arsenic and / or antimony.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62113385A JPH0642546B2 (en) | 1987-05-08 | 1987-05-08 | MOS semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62113385A JPH0642546B2 (en) | 1987-05-08 | 1987-05-08 | MOS semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63278276A JPS63278276A (en) | 1988-11-15 |
| JPH0642546B2 true JPH0642546B2 (en) | 1994-06-01 |
Family
ID=14610963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62113385A Expired - Lifetime JPH0642546B2 (en) | 1987-05-08 | 1987-05-08 | MOS semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0642546B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5539217A (en) * | 1993-08-09 | 1996-07-23 | Cree Research, Inc. | Silicon carbide thyristor |
| US5719409A (en) * | 1996-06-06 | 1998-02-17 | Cree Research, Inc. | Silicon carbide metal-insulator semiconductor field effect transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60223165A (en) * | 1984-04-19 | 1985-11-07 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6276676A (en) * | 1985-09-30 | 1987-04-08 | Toshiba Corp | Mos type semiconductor integrated circuit device |
-
1987
- 1987-05-08 JP JP62113385A patent/JPH0642546B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63278276A (en) | 1988-11-15 |
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