JPH06350358A - Balanced conversion circuit - Google Patents
Balanced conversion circuitInfo
- Publication number
- JPH06350358A JPH06350358A JP24201492A JP24201492A JPH06350358A JP H06350358 A JPH06350358 A JP H06350358A JP 24201492 A JP24201492 A JP 24201492A JP 24201492 A JP24201492 A JP 24201492A JP H06350358 A JPH06350358 A JP H06350358A
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- JP
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- Prior art keywords
- resistors
- emitter
- potential
- resistor
- trs
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は不平衡平衡変換回路に関
し、特にバイポーラトランジスタを用いた不平衡平衡変
換回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an unbalanced / balanced conversion circuit, and more particularly to an unbalanced / balanced conversion circuit using a bipolar transistor.
【０００２】[0002]
【従来の技術】従来の平衡変換回路には、図３に示すよ
うにＦＥＴ（電界効果形トランジスタ）を用いたものが
ある。これはＦＥＴ１３，１４，１５と抵抗３７，３
８，３９により構成した差動増幅器の二つの入力端子の
一方に信号接地用容量４３を接続し、他方の端子に不平
衡信号を入力して出力端子１０３，１０４から平衡信号
を出力させる平衡変換回路であり、入力段には二つのＦ
ＥＴ１１，１２のゲート電極同士を接続して入力端子１
０１とし、ソース電極同士を直接接続して抵抗３６を介
して接地し、各ドレイン電極を平衡信号出力端子とした
増幅回路を用い、この入力段増幅回路の平衡信号出力端
子を前述の差動増幅器の二つの入力端子に接続したもの
である。2. Description of the Related Art Some conventional balanced conversion circuits use FETs (field effect transistors) as shown in FIG. This is FET13,14,15 and resistance 37,3
Balanced conversion in which the signal grounding capacitance 43 is connected to one of the two input terminals of the differential amplifier composed of 8 and 39, the unbalanced signal is input to the other terminal, and the balanced signal is output from the output terminals 103 and 104. It is a circuit, and the input stage has two F
Input terminal 1 by connecting the gate electrodes of ET11, 12
01, the source electrodes are directly connected to each other and grounded via the resistor 36, and an amplifier circuit using each drain electrode as a balanced signal output terminal is used. The balanced signal output terminal of this input stage amplifier circuit is used as the differential amplifier described above. It is connected to the two input terminals of.
【０００３】入力端子１０１に入力された不平衡信号
は、ＦＥＴ１１，１２のゲートにそれぞれ入力され、Ｆ
ＥＴ１１のドレインから増幅された信号が出力される。
ＦＥＴ１２のドレインに出力される高周波信号は容量４
３により接地されるのでＦＥＴ１４のゲートには入力さ
れない。このように、ＦＥＴ１２と抵抗３５による増幅
回路は信号の増幅動作はしないが直流的にはＦＥＴ１１
と抵抗３４によるバイアス回路と同様に動作する。The unbalanced signal input to the input terminal 101 is input to the gates of the FETs 11 and 12, respectively, and F
The amplified signal is output from the drain of ET11.
The high frequency signal output to the drain of the FET 12 has a capacitance of 4
Since it is grounded by 3, it is not input to the gate of the FET 14. As described above, the amplifier circuit including the FET 12 and the resistor 35 does not perform the signal amplifying operation, but the FET 11 does not operate as a direct current.
And the resistor 34 operates similarly to the bias circuit.
【０００４】この種の回路で関連するものには例えば特
開平１−１６４１０９号公報が挙げられる。A related circuit of this type is, for example, Japanese Patent Laid-Open No. 1-164109.
【０００５】[0005]
【発明が解決しようとする課題】この従来の平衡変換回
路では、入力端子に単一の不平衡信号を加えた場合、高
い周波数帯域においてその差動出力にレベル差および１
８０°を超える位相差が生じるという欠点があった。In this conventional balanced conversion circuit, when a single unbalanced signal is applied to the input terminals, the differential output has a level difference and 1 in the high frequency band.
There is a drawback that a phase difference of more than 80 ° occurs.
【０００６】平衡信号を扱う過程において発生したレベ
ル差，位相差は、次段の平衡回路に対し、雑音，波形歪
のもととなるため、極力低減することが望ましい。Since the level difference and the phase difference generated in the process of handling the balanced signal cause noise and waveform distortion in the balanced circuit of the next stage, it is desirable to reduce them as much as possible.
【０００７】なお、これを改善するために、使用する回
路の電流を増やし、周波数帯域を広くすることが考えら
れるがその場合は消費電力が増えてしまうという欠点が
あった。In order to improve this, it is conceivable to increase the current of the circuit to be used and widen the frequency band, but in that case, there is a drawback that the power consumption increases.
【０００８】[0008]
【課題を解決するための手段】本発明によれば、不平衡
信号を入力して差動信号を出力する差動増幅部と、この
差動信号をそれぞれ入力し、異なる抵抗負荷を有する２
つのエミッタホロワ部とを備えた平衡変換回路を得る。According to the present invention, a differential amplifier for receiving an unbalanced signal and outputting a differential signal, and a differential amplifier for receiving the differential signal and having different resistance loads are provided.
A balanced conversion circuit having two emitter followers is obtained.
【０００９】または、本発明の他の形態によれば、不平
衡信号を入力して差動信号を出力する差動増幅器におい
て、この差動増幅器を構成する差動トランジスタの一方
のコレクタには直列接続された２個の抵抗が接続されて
いてこれら２個の抵抗の接続点から出力信号を得、他方
のコレクタには単一の抵抗が接続されていてこの他方の
コレクタと抵抗との接続点から出力信号を得る平衡変換
回路を得る。According to another aspect of the present invention, in a differential amplifier which inputs an unbalanced signal and outputs a differential signal, one collector of one of the differential transistors forming the differential amplifier is connected in series. Two connected resistors are connected and an output signal is obtained from the connecting point of these two resistors, and a single resistor is connected to the other collector and the connecting point of the other collector and the resistor A balanced conversion circuit for obtaining an output signal from is obtained.
【００１０】[0010]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【００１１】図１は本発明の第１の実施例の回路図であ
る。本実施例では第１と第２のトランジスタ１，２のコ
レクタ，エミッタ，ベースには同じように抵抗２１〜２
８および容量４１，４２が接続され、その容量の一方４
１は入力端子１０１に接続され、もう一方４２は接地さ
れている。抵抗２３，２４の片側は定電流原１００に接
続され、定電流原１００の片側は接地されている。各ト
ランジスタ１，２のコレクタは、第３，第４のトランジ
スタ３，４のベースに接続され、第３のトランジスタ３
のエミッタには抵抗２９，３０が直列に接続され、第４
のトランジスタ４のエミッタには抵抗３１が接続されて
いる。トランジスタ３，４のコレクタは電源に接続され
ており、抵抗３０，３１の一端が各差動出力になって出
力端子１０３，１０４に接続されている。FIG. 1 is a circuit diagram of a first embodiment of the present invention. In the present embodiment, the collectors, emitters, and bases of the first and second transistors 1 and 2 have resistors 21 to 2 similarly.
8 and capacitors 41 and 42 are connected, and one of the capacitors 4
One is connected to the input terminal 101 and the other 42 is grounded. One side of the resistors 23 and 24 is connected to the constant current source 100, and one side of the constant current source 100 is grounded. The collectors of the respective transistors 1 and 2 are connected to the bases of the third and fourth transistors 3 and 4, and the third transistor 3
The resistors 29 and 30 are connected in series to the emitter of the
The resistor 31 is connected to the emitter of the transistor 4. The collectors of the transistors 3 and 4 are connected to a power supply, and one ends of the resistors 30 and 31 serve as differential outputs and are connected to the output terminals 103 and 104.
【００１２】不平衡の高周波信号は入力端子１０１に加
えられると、容量４１を通してトランジスタ１のベース
に与えられ、トランジスタ１のエミッタの電位を変化さ
せる。このエミッタ電位の変化は抵抗２１，２３に流れ
る電流を変化させ、定電流源１００に流れ込むもう一方
の電流つまり抵抗２２，２４に流れる電流をも変化させ
る。これらの電流の変化によりトランジスタ１，２のコ
レクタ電位は変化する。When an unbalanced high frequency signal is applied to the input terminal 101, it is given to the base of the transistor 1 through the capacitor 41 and changes the potential of the emitter of the transistor 1. This change in the emitter potential changes the current flowing through the resistors 21 and 23, and also changes the other current flowing into the constant current source 100, that is, the current flowing through the resistors 22 and 24. The collector potentials of the transistors 1 and 2 change due to changes in these currents.
【００１３】ここで、トランジスタ１，２のベースに入
力される信号は不平衡であるため、トランジスタ１，２
のコレクタ電位の変化は、高周波域においてレベル差お
よび１８０度を超える位相差を持つ信号になる。これら
のコレクタ電位の変化はトランジスタ３，４のベース電
位，エミッタ電位の変化となり、トランジスタ３は抵抗
２９，３０に流れる電流値を変化させ、トランジスタ４
は抵抗３１に流れる電流値を変化させる。ここで抵抗３
０と３１は同値であり、抵抗２９の分だけトランジスタ
３の負荷が大きくなっている。出力端子１０３はトラン
ジスタ３のエミッタ電位を抵抗２９と３０で分割した分
割点に接続されており、出力端子１０４はトランジスタ
４のエミッタ電位をそのまま出力するようにトランジス
タ４のエミッタに接続されている。この抵抗２９と３０
による出力レベルの分割は、トランジスタ１と２に生じ
ていたレベル差をなくし、抵抗２９に内在する寄生容量
は進みすぎていた一方の信号の位相を抑える作用とな
り、差動出力１０３，１０４間の相対位相差を１８０度
に近づける作用をする。Here, since the signals input to the bases of the transistors 1 and 2 are unbalanced, the transistors 1 and 2 are
The change in the collector potential of the signal becomes a signal having a level difference and a phase difference exceeding 180 degrees in a high frequency range. Changes in the collector potential of these transistors result in changes in the base potential and the emitter potential of the transistors 3 and 4, and the transistor 3 changes the value of the current flowing through the resistors 29 and 30.
Changes the value of the current flowing through the resistor 31. Resistance 3 here
0 and 31 have the same value, and the load of the transistor 3 is increased by the amount of the resistor 29. The output terminal 103 is connected to the dividing point where the emitter potential of the transistor 3 is divided by the resistors 29 and 30, and the output terminal 104 is connected to the emitter of the transistor 4 so as to output the emitter potential of the transistor 4 as it is. This resistance 29 and 30
The division of the output level by means of eliminating the level difference generated between the transistors 1 and 2 has the effect of suppressing the phase of one of the signals which the parasitic capacitance inherent in the resistor 29 has advanced too much, and between the differential outputs 103 and 104. It acts to bring the relative phase difference close to 180 degrees.
【００１４】図２は本発明の第２の実施例の回路図であ
る。本実施例によればバイポーラトランジスタ１，２の
各エミッタは抵抗２３，２４を介して定電流源１００に
共通に接続され、トランジスタ１のベースは抵抗２５と
２６とでバイアスされるとともに入力端子１０１から容
量４１を介して入力信号が加えられ、トランジスタ２の
ベースは直流的には抵抗２７と２８とでバイアスされ交
流的には容量４２で接地されている。トランジスタ１の
コレクタには抵抗３２と３３とが直列に接続され、これ
ら抵抗３２と３３との共通接続点に出力端子１０３が接
続されている。トランジスタ２のコレクタには抵抗２２
と出力端子１０４とが接続されている。これら出力端子
１０３，１０４の出力がそのまま平衡変換出力となって
いる。本回路では、第１のトランジスタ１のコレクタ抵
抗３２，３３を分割することにより、トランジスタ１，
２のコレクタ電位に生じるレベル差、位相誤差を補正し
ており、他の動作は第１の実施例と同様である。FIG. 2 is a circuit diagram of the second embodiment of the present invention. According to the present embodiment, the emitters of the bipolar transistors 1 and 2 are commonly connected to the constant current source 100 via the resistors 23 and 24, and the base of the transistor 1 is biased by the resistors 25 and 26 and the input terminal 101. The input signal is applied from the capacitor via the capacitor 41, the base of the transistor 2 is biased by the resistors 27 and 28 in terms of direct current, and is grounded by the capacitance 42 in terms of alternating current. Resistors 32 and 33 are connected in series to the collector of the transistor 1, and an output terminal 103 is connected to a common connection point between these resistors 32 and 33. A resistor 22 is provided at the collector of the transistor 2.
And the output terminal 104 are connected. The outputs of these output terminals 103 and 104 are directly converted into balanced outputs. In this circuit, by dividing the collector resistances 32 and 33 of the first transistor 1,
The level difference and the phase error occurring in the collector potential of 2 are corrected, and other operations are the same as those in the first embodiment.
【００１５】[0015]
【発明の効果】以上説明したように、本発明は差動増幅
器を用いて不平衡信号が入力される場合、その差動出力
にエミッタホロワを付加し、その一方の付加をもう一方
の付加より重く（または軽く）することにより、また
は、コレクタに生ずる差動出力の一方のみ負荷の抵抗分
割を介して出力することにより、高周波域での差動出力
信号のレベル差をなくし、相対位相差を１８０度に近づ
けるという効果を有する。本回路の使用により１ＧＨｚ
でのシミュレーションにおいて、レベル差１．２ｄＢが
０．１４ｄＢとなり、相対位相差１９３．１３度が１８
４．８３度に改善された。なお、本シミュレーション結
果は、定数の選び方により更に改善できる。通常、バイ
ポーラトランジスタ回路では差動増幅器で差動信号に変
換した場合には、次段への駆動能力を上げるためエミッ
タホロワ段が付加されるが、本発明によれば、このエミ
ッタホロワに抵抗１個を付加するだけで簡単に構成で
き、消費電力を増やすこともなくバイポーラトランジス
タで構成される平衡変換回路に適している。As described above, according to the present invention, when an unbalanced signal is input using a differential amplifier, an emitter follower is added to the differential output, and one of the additions is made heavier than the other. (Or lighter), or by outputting only one of the differential outputs generated in the collector through resistance division of the load, the level difference of the differential output signals in the high frequency range is eliminated, and the relative phase difference is 180 degrees. It has the effect of approaching the frequency. 1 GHz by using this circuit
In the simulation, the level difference of 1.2 dB was 0.14 dB, and the relative phase difference of 193.13 degrees was 18 dB.
It was improved to 4.83 degrees. The simulation result can be further improved by selecting a constant. Normally, in a bipolar transistor circuit, when a differential signal is converted by a differential amplifier, an emitter follower stage is added in order to increase the driving capability to the next stage. However, according to the present invention, one resistor is added to this emitter follower. It can be configured simply by adding it and is suitable for a balanced conversion circuit composed of bipolar transistors without increasing power consumption.
【図１】本発明の第１の実施例を示す回路図。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す回路図。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
【図３】従来の平衡変換回路を示す回路図。FIG. 3 is a circuit diagram showing a conventional balanced conversion circuit.
１〜４ バイポーラトランジスタ １１〜１５ 電界効果形トランジスタ（ＦＥＴ） ２１〜３９ 抵抗 ４１〜４３ 容量 １００ 定電流源 １０１ 入力端子 １０２ 電源端子 １０３，１０４ 出力端子 1 to 4 Bipolar transistors 11 to 15 Field effect transistors (FET) 21 to 39 Resistors 41 to 43 Capacitance 100 Constant current source 101 Input terminal 102 Power supply terminals 103, 104 Output terminals
Claims (3)
構成される差動増幅器を有し、一方のバイポーラトラン
ジスタのベースに不平衡入力信号が印加される平衡変換
回路に於いて、一方の出力信号は抵抗分割回路で信号レ
ベルが調整された後出力されることを特徴とする平衡変
換回路。1. In a balanced conversion circuit having a differential amplifier including a pair of bipolar transistors, wherein an unbalanced input signal is applied to the base of one bipolar transistor, one output signal is a resistance. A balanced conversion circuit, which is output after a signal level is adjusted by a division circuit.
ッタフォロワ段に接続され、該エミッタフォロワ段の一
方のエミッタ抵抗は前記抵抗分割回路を構成しているこ
とを特徴とする請求項１記載の平衡変換回路。2. The respective outputs of the differential amplifier are respectively connected to an emitter follower stage, and one emitter resistor of the emitter follower stage constitutes the resistance division circuit. Balance conversion circuit.
ンジスタの一方のコレクタ負荷抵抗に前記抵抗分割回路
を構成していることを特徴とする請求項１記載の平衡変
換回路。3. The balanced conversion circuit according to claim 1, wherein the resistance division circuit is formed in a collector load resistance of one of a pair of bipolar transistors of the differential amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24201492A JPH0821820B2 (en) | 1992-09-10 | 1992-09-10 | Balance conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24201492A JPH0821820B2 (en) | 1992-09-10 | 1992-09-10 | Balance conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06350358A true JPH06350358A (en) | 1994-12-22 |
| JPH0821820B2 JPH0821820B2 (en) | 1996-03-04 |
Family
ID=17082986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24201492A Expired - Lifetime JPH0821820B2 (en) | 1992-09-10 | 1992-09-10 | Balance conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0821820B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006030513A1 (en) * | 2004-09-16 | 2006-03-23 | Fujitsu Limited | Unbalance-balance converter |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5828069B2 (en) | 2011-07-27 | 2015-12-02 | パナソニックＩｐマネジメント株式会社 | Power distribution circuit |
-
1992
- 1992-09-10 JP JP24201492A patent/JPH0821820B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006030513A1 (en) * | 2004-09-16 | 2006-03-23 | Fujitsu Limited | Unbalance-balance converter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0821820B2 (en) | 1996-03-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19960827 |