JPH06349295A - Sample & hold circuit - Google Patents
Sample & hold circuitInfo
- Publication number
- JPH06349295A JPH06349295A JP5131547A JP13154793A JPH06349295A JP H06349295 A JPH06349295 A JP H06349295A JP 5131547 A JP5131547 A JP 5131547A JP 13154793 A JP13154793 A JP 13154793A JP H06349295 A JPH06349295 A JP H06349295A
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- JP
- Japan
- Prior art keywords
- capacitor
- output
- terminal
- electrode
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Analogue/Digital Conversion (AREA)
- Filters That Use Time-Delay Elements (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明のサンプルホールド回路に
関し、特にアナログ入力信号を差動信号に変換する全差
動型サンプルホールド回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a fully differential sample and hold circuit for converting an analog input signal into a differential signal.
【０００２】[0002]
【従来の技術】従来のサンプルホールド回路では、図４
に示すように入力端子１と入力端子２とがそれぞれスイ
ッチＳ１およびＳ２を介して集積回路上に形成されるキ
ャパシタＣＩの上部電極５および下部電極６に接続さ
れ、出力端子３および４もそれぞれスイッチＳ３および
Ｓ４を介してキャパシタＣＩの上部電極５および下部電
極６に接続される。2. Description of the Related Art A conventional sample and hold circuit is shown in FIG.
, The input terminal 1 and the input terminal 2 are connected to the upper electrode 5 and the lower electrode 6 of the capacitor CI formed on the integrated circuit via the switches S1 and S2, respectively, and the output terminals 3 and 4 are also switched, respectively. It is connected to the upper electrode 5 and the lower electrode 6 of the capacitor CI via S3 and S4.
【０００３】このサンプルホールド回路の動作を説明す
ると、クロック信号（φＳ）に同期して、アナログ入力
端子１からアナログ信号を入力し、アナログ基準端子２
の基準電圧との電位差をキャパシタＣＩに記憶するが、
このとき集積回路上に形成するキャパシタには下部電極
６と基板９との間に寄生容量ＣＳが存在する（図６参
照）。この寄生容量ＣＳに基板電圧と上記基準電圧との
電位差分の電荷が蓄積される。Explaining the operation of this sample hold circuit, an analog signal is input from the analog input terminal 1 in synchronization with the clock signal (φS), and the analog reference terminal 2 is input.
The potential difference from the reference voltage of is stored in the capacitor CI,
At this time, the capacitor formed on the integrated circuit has a parasitic capacitance CS between the lower electrode 6 and the substrate 9 (see FIG. 6). In the parasitic capacitance CS, electric charges having a potential difference between the substrate voltage and the reference voltage are accumulated.
【０００４】次に、クロック信号（φＨ）に同期して差
動出力３および４から差動信号が出力されるが、このと
き寄生容量ＣＳに蓄積されている電荷が出力される差動
信号に対して影響を与える。これを図５のモデルを参照
して説明すると、端子１から電位Ｖ１、端子２から電位
Ｖ２が印加される場合この系に保存される全電荷Ｑ１
は、 Ｑ１＝ＣＩ・（Ｖ２−Ｖ１）＋ＣＳ・Ｖ２ となる。Next, a differential signal is output from the differential outputs 3 and 4 in synchronization with the clock signal (φH). At this time, the charge accumulated in the parasitic capacitance CS is output to the differential signal. Affect against. This will be described with reference to the model of FIG. 5. When a potential V1 is applied from the terminal 1 and a potential V2 is applied from the terminal 2, the total charge Q1 stored in this system is
Becomes Q1 = CI · (V2-V1) + CS · V2.
【０００５】次に出力端子側へ接続されたときに、端子
３はＶ３、端子４はＶ４の電位になるものとするとその
ときの電荷Ｑ２は Ｑ２＝ＣＩ・（Ｖ４−Ｖ３）＋ＣＳ・Ｖ４ となる。２つの系では電荷が保存されるから ＣＩ・（Ｖ２−Ｖ１）＋ＣＳ・Ｖ２＝ＣＩ・（Ｖ４−Ｖ
３）＋ＣＳ・Ｖ４ となる。出力差電位（Ｖ４−Ｖ３）は入力差電位（Ｖ２
−Ｖ１）がそのまま出力差電位となるのが理想的である
が、寄生容量ＣＳによる影響により、 （Ｖ４−Ｖ３）＝（Ｖ２−Ｖ１）＋（ＣＳ／ＣＩ）・
（Ｖ４−Ｖ２） となり、（ＣＳ／ＣＩ）・（Ｖ４−Ｖ２）の誤差分を含
むことになる。Next, when connected to the output terminal side, assuming that the terminal 3 has a potential of V3 and the terminal 4 has a potential of V4, the charge Q2 at that time is Q2 = CI. (V4-V3) + CS.V4 Become. Since charge is stored in the two systems, CI · (V2-V1) + CS · V2 = CI · (V4-V
3) + CS · V4. The output difference potential (V4-V3) is equal to the input difference potential (V2
It is ideal that −V1) becomes the output difference potential as it is, but due to the influence of the parasitic capacitance CS, (V4-V3) = (V2-V1) + (CS / CI).
(V4-V2), which includes the error of (CS / CI). (V4-V2).
【０００６】[0006]
【発明が解決しようとする課題】この従来のサンプルホ
ールド回路では、キャパシタの集積回路上に形成する下
部電極と基板との間に寄生容量が存在するために、サン
プル動作時には下部電極に与えられる電位と基板電位と
の電位差分の電荷が蓄積される。ホールド動作時には、
この寄生容量による電荷のために、出力端子２に対して
出力端子４に電位差ΔＶが生じた場合に、出力電位に （ＣＳ／ＣＩ）・ΔＶ の誤差分が含まれてしまうという問題点があった。In this conventional sample-hold circuit, since the parasitic capacitance exists between the lower electrode formed on the integrated circuit of the capacitor and the substrate, the potential applied to the lower electrode during the sample operation. The electric charge of the potential difference between the substrate potential and the substrate potential is accumulated. During hold operation,
There is a problem that when the potential difference ΔV is generated between the output terminal 2 and the output terminal 4 due to the charge due to the parasitic capacitance, the output potential includes an error amount of (CS / CI) · ΔV. It was
【０００７】[0007]
【課題を解決するための手段】本発明のサンプルホール
ド回路は、アナログ入力端子より入力したアナログ信号
電圧と、アナログ基準端子より入力したアナログ基準電
圧との電位差を半導体基板に設けられたキャパシタに充
電して前記電位差を差動信号として出力するサンプルホ
ールド回路において、前記アナログ入力端子と前記キャ
パシタの第１の電極とを接続する第１のクロック信号に
同期して制御される第１のスイッチを備え前記キャパシ
タの第２の電極をアナログ基準端子に接続する前記キャ
パシタへの記憶手段と、前記キャパシタの第１の電極と
第１の出力端子とを接続する第２のクロック信号に同期
して制御される第２のスイッチを備え前記キャパシタの
第２の電極を第２の出力端子とする前記差動信号として
の出力手段と、前記キャパシタの第２の電極の電位が、
前記記憶の手段におけるアナログ基準端子のときと前記
出力手段における第２の出力端子のときとで一定に保つ
手段とを有する。また、本発明のサンプルホールド回路
は、前記第１の出力端子に差動入力差動出力型の演算増
幅器の一方の差動入力端子を接続し、前記第２の出力に
前記演算増幅器の他方の差動入力端子を接続する構成と
することもできる。The sample and hold circuit of the present invention charges a capacitor provided on a semiconductor substrate with a potential difference between an analog signal voltage input from an analog input terminal and an analog reference voltage input from an analog reference terminal. In the sample-and-hold circuit that outputs the potential difference as a differential signal, a first switch controlled in synchronization with a first clock signal that connects the analog input terminal and the first electrode of the capacitor is provided. The storage means for connecting the second electrode of the capacitor to the analog reference terminal and the second clock signal connecting the first electrode of the capacitor and the first output terminal are controlled in synchronization with each other. An output means as the differential signal having a second electrode of the capacitor as a second output terminal, Potential of the second electrode of the capacitor,
It has a means for keeping it constant when the analog reference terminal in the storage means and the second output terminal in the output means. In the sample hold circuit of the present invention, one of the differential input terminals of a differential input differential output type operational amplifier is connected to the first output terminal, and the other output of the operational amplifier is connected to the second output. It is also possible to adopt a configuration in which differential input terminals are connected.
【０００８】[0008]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【０００９】図１は本発明の第１の実施例である。FIG. 1 shows a first embodiment of the present invention.
【００１０】入力端子１とキャパシタの上部電極とを接
続するスイッチＳ１と、演算増幅器Ａ１の正入力端子と
キャパシタの上部電極とを接続するスイッチＳ３が交互
に切り換えられ信号が出力側へ伝達される。A switch S1 connecting the input terminal 1 and the upper electrode of the capacitor and a switch S3 connecting the positive input terminal of the operational amplifier A1 and the upper electrode of the capacitor are alternately switched to transmit a signal to the output side. .
【００１１】一方、キャパシタの下部電極は演算増幅器
Ａ１の負入力端子に常時接続され位相の反転した信号が
出力側へ伝達される。演算増幅器Ａ１の入出力間には、
図１に示すように入力側に下部電極が接続されたホール
ドキャパシタＣＨ１およびＣＨ２と演算増幅器Ａ１の入
出力間とを接続し、キャパシタＣＨ１およびＣＨ２をリ
セットするためのスイッチＳ５およびＳ６が設けられて
いる。On the other hand, the lower electrode of the capacitor is always connected to the negative input terminal of the operational amplifier A1 so that the signal whose phase is inverted is transmitted to the output side. Between the input and output of the operational amplifier A1,
As shown in FIG. 1, switches S5 and S6 are provided for connecting the hold capacitors CH1 and CH2 whose lower electrodes are connected to the input side and the input and output of the operational amplifier A1 and resetting the capacitors CH1 and CH2. There is.
【００１２】次に、この実施例の動作について図２を参
照しながら説明すると、クロック信号（φＳ）によりス
イッチＳ１、Ｓ５およびＳ６がオンとなり、このとき演
算増幅器Ａ１の入出力電位は、アナログ回路の基準電圧
レベルとなるので、キャパシタＣＩには入力信号とアナ
ログ回路の基準電圧レベルの電位差が記憶され、クロッ
ク信号（φＨ）により、スイッチＳ１，Ｓ５よおびＳ６
はオフ、スイッチＳ３がオンになり、キャパシタＣＩに
蓄積された電荷は全て、キャパシタＣＨ１およびＣＨ２
に転送され、出力端子３および３，４からそれぞれ位相
が反対の信号を出力し、差動信号が得られる。Next, the operation of this embodiment will be described with reference to FIG. 2. The clock signal (φS) turns on the switches S1, S5 and S6. At this time, the input / output potential of the operational amplifier A1 is an analog circuit. , The potential difference between the input signal and the reference voltage level of the analog circuit is stored in the capacitor CI, and the switches S1, S5, and S6 are set by the clock signal (φH).
Is turned off, the switch S3 is turned on, and the charges accumulated in the capacitor CI are all stored in the capacitors CH1 and CH2.
And output signals having opposite phases from the output terminals 3 and 3 and 4 to obtain a differential signal.
【００１３】このとき、従来問題となっていた下部電極
の寄生容量による効果は、下部電極電位が常にアナログ
回路の共通基準電圧レベルに保たれているため、その影
響を受けない。At this time, the effect of the parasitic capacitance of the lower electrode, which has been a problem in the related art, is not affected because the lower electrode potential is always kept at the common reference voltage level of the analog circuit.
【００１４】次に、本発明の第２の実施例について説明
する。Next, a second embodiment of the present invention will be described.
【００１５】図３は本発明の第２の実施例である。FIG. 3 shows a second embodiment of the present invention.
【００１６】基本動作は第１の実施例とほぼ同じであ
り、キャパシタＣＩがＣＩ１およびＣＩ２の２つに分離
したものと考えれば良い。この実施例の動作は、基準端
子２からアナログ回路の共通基準電圧レベルを与え、ク
ロック信号（φＳ）により入力信号をキャパシタＣＩ１
およびＣＩ２に記憶し、クロック信号（φＨ）によりキ
ャパシタＣＩ１に蓄積された電荷はキャパシタＣＨ１
に、キャパシタＣＩ２に蓄積された電荷はキャパシタＣ
Ｉ１とは逆の極性の電荷がキャパシタＣＨ２に転送され
る。出力端子３および４からそれぞれ位相が反対の信号
を出力し、差動信号が得られる。第２の実施例において
も、キャパシタＣＩ１およびＣＩ２のそれぞれの下部電
極の電位がいずれも基準電位として一定に保たれている
ので寄生容量による影響が出力に現われない。The basic operation is almost the same as that of the first embodiment, and it can be considered that the capacitor CI is separated into two capacitors CI1 and CI2. In the operation of this embodiment, the common reference voltage level of the analog circuit is given from the reference terminal 2 and the input signal is supplied to the capacitor CI1 by the clock signal (φS).
And the charge stored in CI2 and stored in the capacitor CI1 by the clock signal (φH) is stored in the capacitor CH1.
In addition, the charge accumulated in the capacitor CI2 is
The charge having the opposite polarity to I1 is transferred to the capacitor CH2. Signals having opposite phases are output from the output terminals 3 and 4, and a differential signal is obtained. Also in the second embodiment, since the potentials of the lower electrodes of the capacitors CI1 and CI2 are kept constant as the reference potential, the influence of the parasitic capacitance does not appear in the output.
【００１７】[0017]
【発明の効果】以上説明したように本発明は、入力信号
を記憶するための集積回路上のキャパシタの下部電極に
常に一定のアナログ基準電圧が与えられるようにしたの
で、サンプル動作時にキャパシタの下部電極と基板との
間に存在する寄生容量に蓄えられた電荷が、ホールド動
作時に出力端子側へ放出されることなく一定に保たれる
ので、出力電位に誤差が生じないという効果を有する。As described above, according to the present invention, a constant analog reference voltage is always applied to the lower electrode of the capacitor on the integrated circuit for storing the input signal. Since the electric charge stored in the parasitic capacitance existing between the electrode and the substrate is kept constant without being discharged to the output terminal side during the hold operation, there is an effect that no error occurs in the output potential.
【図１】本発明の第１の実施例のサンプルホールド回路
の構成図である。FIG. 1 is a configuration diagram of a sample and hold circuit according to a first embodiment of the present invention.
【図２】図１に示す本発明の第１の実施例のサンプルホ
ールド回路の動作を説明するタイムチャート図である。FIG. 2 is a time chart diagram for explaining the operation of the sample hold circuit of the first embodiment of the present invention shown in FIG.
【図３】本発明の第２の実施例のサンプルホールド回路
の構成図である。FIG. 3 is a configuration diagram of a sample hold circuit according to a second embodiment of the present invention.
【図４】従来例のサンプルホールド回路の構成図であ
る。FIG. 4 is a configuration diagram of a conventional sample and hold circuit.
【図５】従来例の動作を説明するための図である。FIG. 5 is a diagram for explaining the operation of a conventional example.
【図６】集積回路上キャパシタの構造を説明するための
図である。FIG. 6 is a diagram for explaining a structure of a capacitor on an integrated circuit.
１，２ 入力端子 ３，４ 出力端子 ＣＩ，ＣＩ１，ＣＩ２，ＣＨ１，ＣＨ２ キャパシタ ＣＳ 寄生容量 Ｓ１〜Ｓ４，Ｓ１′〜Ｓ４′，Ｓ５，Ｓ６ スイッチ Ａ１ 演算増幅器 1, 2 input terminals 3, 4 output terminals CI, CI1, CI2, CH1, CH2 capacitors CS parasitic capacitances S1 to S4, S1 'to S4', S5, S6 switches A1 operational amplifiers
Claims (2)
信号電圧と、アナログ基準端子より入力したアナログ基
準電圧との電位差を半導体基板に設けられたキャパシタ
に充電して前記電位差を差動信号として出力するサンプ
ルホールド回路において、前記アナログ出力端子と前記
キャパシタの第１の電極とを接続する第１のクロック信
号に同期して制御される第１のスイッチを備え前記キャ
パシタの第２の電極をアナログ基準端子に接続する前記
キャパシタへの記憶手段と、前記キャパシタの第１の電
極と第１の出力端子とを接続する第２のクロック信号に
同期して制御される第２のスイッチを備え前記キャパシ
タの第２の電極を第２の出力端子とする前記差動信号と
しての出力手段と、前記キャパシタの第２の電極の電位
が、前記記憶の手段におけるアナログ基準端子のときと
前記出力手段における第２の出力端子のときとで一定に
保つ手段とを有することも特徴とするサンプルホールド
回路。1. A sample in which a capacitor provided on a semiconductor substrate is charged with a potential difference between an analog signal voltage input from an analog input terminal and an analog reference voltage input from an analog reference terminal, and the potential difference is output as a differential signal. The hold circuit includes a first switch that is controlled in synchronization with a first clock signal that connects the analog output terminal and the first electrode of the capacitor, and uses the second electrode of the capacitor as an analog reference terminal. A second switch of the capacitor, which comprises storage means for connecting the capacitor, and a second switch controlled in synchronization with a second clock signal connecting the first electrode and the first output terminal of the capacitor. Means for storing the differential signal having the second electrode as the second output terminal and the potential of the second electrode of the capacitor are stored in the storage means. And a means for keeping constant at the time of the analog reference terminal and the time of the second output terminal of the output means.
型の演算増幅器の一方の差動入力端子を接続し、前記第
２の出力に前記演算増幅器の他方の差動入力端子を接続
することを特徴とする請求項１記載のサンプルホールド
回路。2. The first output terminal is connected to one differential input terminal of a differential input differential output type operational amplifier, and the second output is connected to the other differential input terminal of the operational amplifier. The sample hold circuit according to claim 1, wherein the sample hold circuit is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13154793A JP3144154B2 (en) | 1993-06-02 | 1993-06-02 | Sample hold circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13154793A JP3144154B2 (en) | 1993-06-02 | 1993-06-02 | Sample hold circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06349295A true JPH06349295A (en) | 1994-12-22 |
| JP3144154B2 JP3144154B2 (en) | 2001-03-12 |
Family
ID=15060634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13154793A Expired - Fee Related JP3144154B2 (en) | 1993-06-02 | 1993-06-02 | Sample hold circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3144154B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015146496A (en) * | 2014-01-31 | 2015-08-13 | アルプス電気株式会社 | signal processing circuit |
-
1993
- 1993-06-02 JP JP13154793A patent/JP3144154B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015146496A (en) * | 2014-01-31 | 2015-08-13 | アルプス電気株式会社 | signal processing circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3144154B2 (en) | 2001-03-12 |
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