JPH06338464A - Substrate for semiconductor device - Google Patents
Substrate for semiconductor deviceInfo
- Publication number
- JPH06338464A JPH06338464A JP12912193A JP12912193A JPH06338464A JP H06338464 A JPH06338464 A JP H06338464A JP 12912193 A JP12912193 A JP 12912193A JP 12912193 A JP12912193 A JP 12912193A JP H06338464 A JPH06338464 A JP H06338464A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- substrate
- silicon single
- semiconductor device
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はシリコン単結晶ウェー
ハ、または、その表面にシリコン単結晶薄膜を成長させ
た半導体装置用基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon single crystal wafer or a semiconductor device substrate having a silicon single crystal thin film grown on the surface thereof.
【０００２】[0002]
【従来の技術及び発明が解決しようとする課題】ＭＯＳ
形のＬＳＩは従来よりシリコン単結晶ウェーハ（以下、
単にシリコンウェーハともいう）を用いて製造されてい
る。このシリコン単結晶ウェーハに対して、最近のデバ
イス構造の微細化に伴ない、ゲート酸化膜として約１０
ｎｍ以下の極めて薄いシリコン酸化膜を形成する必要性
から、表面のミクロな構造（以下、マイクロラフネスと
いう）に関心が持たれている。すなわち、ＭＯＳ形のデ
バイスの性能、信頼性に決定的な役割を果たすゲート酸
化膜の性質がウェーハ表面のマイクロラフネスによって
影響を受けると考えられるようになった。PRIOR ART AND PROBLEM TO BE SOLVED BY THE INVENTION MOS
Type LSI has traditionally been a silicon single crystal wafer (hereinafter,
It is also manufactured using a silicon wafer). With respect to this silicon single crystal wafer, a gate oxide film of about 10 has been formed due to the recent miniaturization of the device structure.
Since it is necessary to form an extremely thin silicon oxide film having a thickness of nm or less, attention is paid to a microstructure of the surface (hereinafter referred to as microroughness). That is, it has been considered that the properties of the gate oxide film, which plays a crucial role in the performance and reliability of the MOS type device, are affected by the microroughness of the wafer surface.
【０００３】しかしながら、シリコンウェーハ表面の原
子的なレベルでの凹凸の評価は困難であり、マイクロラ
フネスの酸化膜の特性に及ぼす影響についても必ずしも
明確になってはおらず、ディープサブミクロンＵＬＳＩ
用シリコンウェーハの表面のマイクロラフネスについて
は規定されていなかった。However, it is difficult to evaluate the unevenness of the surface of the silicon wafer at the atomic level, and the effect of microroughness on the characteristics of the oxide film has not always been clarified. Deep submicron ULSI
The microroughness of the surface of the silicon wafer for use was not specified.
【０００４】ＭＯＳ形のＬＳＩの製造には、主表面の面
方位が（１００）からなるシリコンウェーハが用いられ
ている。通常に用いられているシリコン単結晶ウェーハ
の表面の凹凸を光学干渉法で測定すると、図３に示す表
面構造を有しており、その二乗平均値を求めると約０．
５ｎｍであった。A silicon wafer whose main surface has a plane orientation of (100) is used for manufacturing a MOS type LSI. When the irregularities on the surface of a commonly used silicon single crystal wafer are measured by an optical interference method, they have the surface structure shown in FIG. 3, and the root mean square value thereof is about 0.
It was 5 nm.
【０００５】このシリコンウェーハを用いて膜厚が約１
０ｎｍ以下のゲート酸化膜をもつＭＯＳ形のトランジス
タを製造すると、しばしば、酸化膜の絶縁耐圧が低下す
るというデバイスの初期不良を起こすことが知られてい
る。また、デバイス製造直後の絶縁耐圧は十分に高い
が、この絶縁耐圧が経時的に劣化する現象 (time depen
dent dielectric breakdown)があった。これら絶縁耐圧
の低下あるいは劣化は、ＭＯＳ形デバイスの微細化に伴
い、酸化膜を薄くしなければならない状況の中で深刻な
問題となってきている。Using this silicon wafer, the film thickness is about 1
It is known that when a MOS type transistor having a gate oxide film of 0 nm or less is manufactured, an initial failure of the device often occurs such that the withstand voltage of the oxide film is lowered. In addition, the withstand voltage immediately after device manufacturing is sufficiently high, but this withstand voltage deteriorates over time (time depen
There was a dent dielectric breakdown). The reduction or deterioration of the dielectric strength has become a serious problem in the situation where the oxide film has to be thinned with the miniaturization of MOS type devices.
【０００６】上述した絶縁耐圧の低下あるいは劣化の原
因としては、酸化膜厚の局所的なバラツキ、及びデバイ
ス製造プロセスで発生する微量な金属汚染が考えられて
いる。そこで、製造プロセスのクリーン化等が進められ
てはいるが、抜本的な解決には到っていなかった。As a cause of the above-mentioned decrease or deterioration of the dielectric strength voltage, it is considered that the oxide film thickness locally varies and a trace amount of metal contamination generated in the device manufacturing process. Therefore, although the manufacturing process has been made cleaner, a fundamental solution has not been reached.
【０００７】本発明は上記の問題点を解決するためにな
されたもので、ＵＬＳＩの製造に最適な表面構造をもっ
たシリコン単結晶ウェーハ、または、その表面にシリコ
ン単結晶薄膜を成長させた半導体装置用基板を得ること
を目的とする。The present invention has been made to solve the above problems, and is a silicon single crystal wafer having a surface structure most suitable for the manufacture of ULSI, or a semiconductor having a silicon single crystal thin film grown on the surface thereof. The purpose is to obtain a device substrate.
【０００８】[0008]
【課題を解決するための手段】本発明は、（１００）面
に近い主表面をもつシリコン単結晶ウェーハ、または、
このウェーハに、気相成長法によりシリコン単結晶薄膜
を成長させたものにおいて、最表面の結晶学的ステップ
密度が約１０10個／ｃｍ2 以下（線密度で１０5 個／cm
以下）であることを特徴とする半導体装置用基板であ
る。The present invention is a silicon single crystal wafer having a main surface close to the (100) plane, or
When a silicon single crystal thin film was grown on this wafer by a vapor phase epitaxy method, the crystallographic step density of the outermost surface was about 10 10 pieces / cm 2 or less (10 5 pieces / cm in linear density).
The following) is a substrate for a semiconductor device.
【０００９】[0009]
【作用】極薄の酸化膜を有するＭＯＳ形のデバイスにあ
っては、シリコン単結晶ウェーハ表面のマイクロラフネ
スが耐圧に影響すると考えられたにも拘らず、従来はそ
の定量的な測定法あるいは規定がないために、研磨され
たシリコン単結晶ウェーハをそのまま使用していたこと
が耐圧特性にバラツキを生じる一因であった。In the MOS type device having an ultra-thin oxide film, although it was thought that the microroughness of the surface of the silicon single crystal wafer affected the breakdown voltage, the conventional quantitative measurement method or regulation was used. Since there is no such problem, the fact that the polished silicon single crystal wafer is used as it is is one of the causes of the variation in the withstand voltage characteristics.
【００１０】そこで、発明者は、定量的に規定されてい
なかったシリコン単結晶ウェーハ表面のマイクロラフネ
スを結晶学的ステップ密度で定義し、その絶縁破壊耐圧
への影響を調べ、その結果、（１００）面に近い主表面
をもつシリコン単結晶ウェーハ、または、このウェーハ
に、気相成長法によりシリコン単結晶薄膜を成長させた
ものにおいて、最表面の結晶学的ステップ密度が約１０
10個／ｃｍ2 以下であるとき、酸化膜の耐圧特性及びそ
の長期的信頼性が著しく向上することを見出だした。こ
れにより、ＵＬＳＩの製造に最適な表面構造をもった半
導体装置用基板が得られる。Therefore, the inventor defined the microroughness of the surface of a silicon single crystal wafer, which was not quantitatively defined, by the crystallographic step density, investigated the influence on the dielectric breakdown voltage, and as a result, (100 ), A silicon single crystal wafer having a main surface close to that of a silicon wafer, or a wafer in which a silicon single crystal thin film is grown by a vapor phase growth method, and the crystallographic step density of the outermost surface is about 10
It has been found that the breakdown voltage characteristics of the oxide film and the long-term reliability thereof are remarkably improved when the number is 10 pieces / cm 2 or less. As a result, a semiconductor device substrate having a surface structure most suitable for ULSI manufacturing can be obtained.
【００１１】[0011]
【実施例】以下、本発明の具体的な実施例について、図
面を参照して説明する。通常のチョクラルスキー法で引
上げられたシリコン単結晶基板は、主平面が（１００）
±１°となるようにウェーハ状に加工され、仕上げられ
る。ウェーハ表面は、通常、機械的または化学的な研磨
によって鏡面に仕上げられるが、その表面の微少な凹凸
を原子間力顕微鏡 (Atomic Force Microscope) によっ
て観察すると、高さが約０．３μｍのステップが存在し
た。これはシリコン (Ｓi) 結晶の（１００）表面の２
量体 (dimer)の高さに対応するものである。通常ウェー
ハにおいて、このステップは１０11〜１０12個／ｃｍ2
程度の密度を持って存在し、ウェーハ面内で不規則に分
布している。これは従来の仕上げ方法及び洗浄方法では
表面のマイクロラフネスの制御ができないことを示して
いる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the drawings. The main surface of the silicon single crystal substrate pulled by the ordinary Czochralski method is (100)
It is processed and finished in a wafer shape to be ± 1 °. The wafer surface is usually mirror-finished by mechanical or chemical polishing, but when observing the minute irregularities on the surface with an atomic force microscope, a step with a height of about 0.3 μm can be seen. Were present. This is 2 of (100) surface of silicon (Si) crystal.
It corresponds to the height of the dimer. In a normal wafer, this step is 10 11 to 10 12 pieces / cm 2
It exists with a certain density and is irregularly distributed on the wafer surface. This indicates that the conventional finishing method and cleaning method cannot control the surface microroughness.
【００１２】そこで、鏡面仕上げされているシリコンウ
ェーハ上に、気相化学反応法によりエピタキシャル層を
成長させることを試みた。この場合、気相反応には、例
えば、水素とトリクロルシランの混合ガスを用い、この
ガスを１０００〜１２００℃に加熱したシリコン単結晶
基板上に送り込み、その表面での還元反応によってシリ
コン単結晶膜を形成した。気相成長させたウェーハの表
面構造を原子間力顕微鏡で観察すると、正規の（１０
０）面からのずれ角度、すなわち、オフアングルに応じ
て密度が異なるものの、周期的なステップ構造になって
いることが分かった。Therefore, an attempt was made to grow an epitaxial layer on a mirror-finished silicon wafer by a vapor phase chemical reaction method. In this case, for the gas phase reaction, for example, a mixed gas of hydrogen and trichlorosilane is used, and this gas is fed onto a silicon single crystal substrate heated to 1000 to 1200 ° C., and the silicon single crystal film is subjected to a reduction reaction on the surface thereof. Was formed. When the surface structure of the vapor-grown wafer is observed with an atomic force microscope, the normal (10
It was found that the density is different depending on the angle of deviation from the (0) plane, that is, the off-angle, but has a periodic step structure.
【００１３】図２(a),(b) はこの表面構造を示したもの
で、オフアングルが０．５°のときは、(a) に示すよう
に１×１０11のステップ密度で、オフアングルが０．１
°のときは、(b) に示すように約４×１０10のステップ
密度であった。なお、図示はしないが、オフアングルが
０．０５°のときは約１×１０9 のステップ密度であっ
た。このように、周期的で、かつ、均一なステップ構造
が気相成長で形成される理由は、気相成長が単原子層毎
に成長する横方向成長機構によるものである。[0013] FIG. 2 (a), (b) is an illustration of this surface structure, and when off-angle is 0.5 °, in the step density of 1 × 10 11 (a), the OFF Angle is 0.1
When the angle was °, the step density was about 4 × 10 10 as shown in (b). Although not shown, the step density was about 1 × 10 9 when the off-angle was 0.05 °. As described above, the reason why the periodic and uniform step structure is formed by vapor phase growth is due to the lateral growth mechanism in which vapor phase growth grows for each monoatomic layer.
【００１４】上記のように、オフアングルが種々に異な
るウェーハにそれぞれエピタキシャル層を成長させた多
数のエピタキシャルウェーハを用いて、その上にそれぞ
れ酸化膜を形成すると共に、酸化膜の絶縁破壊耐圧のス
テップ密度への依存性を調べると図１に示す関係があっ
た。この図から明らかなように、ステップ密度が約１０
10個／ｃｍ2 以下では高い絶縁破壊耐圧を示し、これよ
りもステップ密度が高くなる程、絶縁破壊耐圧は低くな
っている。As described above, a large number of epitaxial wafers each having an epitaxial layer grown on wafers having different off-angles are used to form an oxide film on each of the epitaxial wafers, and the dielectric breakdown voltage step of the oxide film is increased. When the dependence on the density was examined, there was the relationship shown in FIG. As is clear from this figure, the step density is about 10
When the number is less than 10 pieces / cm 2 , the dielectric breakdown voltage is high, and the higher the step density is, the lower the dielectric breakdown voltage is.
【００１５】この結果、ステップ密度が約１０10個／ｃ
ｍ2 以下（線密度で１０5 個／cm以下）のシリコン単結
晶基板を使用することが、微細なＭＯＳ形のデバイスの
特性及び信頼性を向上させる上で極めて有効であること
が判明した。As a result, the step density is about 10 10 pieces / c.
It has been found that the use of a silicon single crystal substrate of m 2 or less (10 5 pieces / cm or less in linear density) is extremely effective in improving the characteristics and reliability of a fine MOS type device.
【００１６】ステップは、Ｆe ，Ｃu ，Ｎi 等のデバイ
ス製造プロセス中に混入する微量な金属不純物の吸着サ
イトとなるため、ステップ密度の少ないシリコン単結晶
ウェーハは金属の吸着量が少なくなり、その結果、酸化
膜の耐圧特性が向上せしめられたものと考えることがで
きる。Since the step serves as an adsorption site for a trace amount of metal impurities such as Fe, Cu, Ni mixed in the device manufacturing process, the silicon single crystal wafer having a small step density has a small amount of adsorbed metal, and as a result, It can be considered that the withstand voltage characteristic of the oxide film is improved.
【００１７】一方、シリコン単結晶ウェーハの表面のス
テップ密度を減少させることを目的として、鏡面仕上げ
されているシリコン単結晶ウェーハを超高真空中（１０
-9Ｔｏｒｒ以下）で、約１０００℃の高温アニールを行
なった。かかる高温アニールによっても表面でシリコン
原子の移動が起き、ステップ密度が減少することが分か
った。この方法によって作成したシリコン単結晶ウェー
ハにおいても、ステップ密度が約１０10個／ｃｍ2 以下
のものに対する、酸化膜の絶縁破壊耐圧は上述したと同
様に高いという結果が得られた。On the other hand, in order to reduce the step density on the surface of the silicon single crystal wafer, the mirror-finished silicon single crystal wafer is subjected to ultra high vacuum (10
-9 Torr or less), and high temperature annealing at about 1000 ° C. was performed. It was found that the high-temperature annealing also causes the movement of silicon atoms on the surface and reduces the step density. Also in the silicon single crystal wafer produced by this method, it was found that the dielectric breakdown voltage of the oxide film was as high as that described above for a step density of about 10 10 / cm 2 or less.
【００１８】[0018]
【発明の効果】以上の説明によって明らかなように、本
発明によれば、ＭＯＳ形のデバイスで使用される極薄の
酸化膜の耐圧特性を大幅に向上させることができ、ＵＬ
ＳＩの製造に最適な基板とし得ると共に、デバイスのの
歩留まり、及び長期的な信頼性を高めることができる。As is apparent from the above description, according to the present invention, it is possible to greatly improve the withstand voltage characteristic of an ultrathin oxide film used in a MOS type device.
The substrate can be optimally used for manufacturing SI, and the yield of devices and long-term reliability can be improved.
【図１】本発明の実施例に係るシリコン単結晶ウェーハ
のステップ密度と酸化膜の絶縁破壊耐圧との関係を示し
た線図。FIG. 1 is a diagram showing the relationship between the step density of a silicon single crystal wafer according to an example of the present invention and the dielectric breakdown voltage of an oxide film.
【図２】本発明の実施例に係るシリコンエピタキシャル
単結晶ウェーハの表面構造の説明図。FIG. 2 is an explanatory diagram of a surface structure of a silicon epitaxial single crystal wafer according to an example of the present invention.
【図３】従来のシリコン単結晶基板の表面構造の説明
図。FIG. 3 is an explanatory diagram of a surface structure of a conventional silicon single crystal substrate.
Claims (2)
単結晶ウェーハでなる半導体装置用基板において、最表
面の結晶学的ステップ密度が約１０10個／ｃｍ2 以下で
あることを特徴とする半導体装置用基板。1. A substrate for a semiconductor device comprising a silicon single crystal wafer having a main surface close to a (100) plane, wherein the crystallographic step density of the outermost surface is about 10 10 pieces / cm 2 or less. Substrate for semiconductor device.
単結晶ウェーハに、気相成長法によりシリコン単結晶薄
膜を成長させた半導体装置用基板において、最表面の結
晶学的ステップ密度が約１０10個／ｃｍ2 以下（線密度
で１０5 個／cm以下）であることを特徴とする半導体装
置用基板。2. In a substrate for a semiconductor device in which a silicon single crystal thin film is grown on a silicon single crystal wafer having a main surface close to the (100) plane by a vapor phase epitaxy method, the crystallographic step density of the outermost surface is about A semiconductor device substrate having a density of 10 10 pieces / cm 2 or less (a linear density of 10 5 pieces / cm or less).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12912193A JPH06338464A (en) | 1993-05-31 | 1993-05-31 | Substrate for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12912193A JPH06338464A (en) | 1993-05-31 | 1993-05-31 | Substrate for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06338464A true JPH06338464A (en) | 1994-12-06 |
Family
ID=15001601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12912193A Pending JPH06338464A (en) | 1993-05-31 | 1993-05-31 | Substrate for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06338464A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011125282A1 (en) | 2010-04-01 | 2011-10-13 | 信越半導体株式会社 | Silicon epitaxial wafer and method for producing the same, as well as bonded soi wafer and method for producing the same |
-
1993
- 1993-05-31 JP JP12912193A patent/JPH06338464A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011125282A1 (en) | 2010-04-01 | 2011-10-13 | 信越半導体株式会社 | Silicon epitaxial wafer and method for producing the same, as well as bonded soi wafer and method for producing the same |
| JP2011216780A (en) * | 2010-04-01 | 2011-10-27 | Shin Etsu Handotai Co Ltd | Silicon epitaxial wafer, method for producing the same, method for producing bonded soi wafer, and bonded soi wafer |
| US20120326268A1 (en) * | 2010-04-01 | 2012-12-27 | Shin-Etsu Handotai Co., Ltd. | Silicon epitaxial wafer, method for manufacturing the same, bonded soi wafer and method for manufacturing the same |
| CN102859649A (en) * | 2010-04-01 | 2013-01-02 | 信越半导体股份有限公司 | Silicon Epitaxial Wafer And Method For Producing The Same, As Well As Bonded Soi Wafer And Method For Producing The Same |
| US8823130B2 (en) | 2010-04-01 | 2014-09-02 | Shin-Etsu Handotai Co., Ltd. | Silicon epitaxial wafer, method for manufacturing the same, bonded SOI wafer and method for manufacturing the same |
| CN102859649B (en) * | 2010-04-01 | 2015-06-24 | 信越半导体股份有限公司 | Silicon Epitaxial Wafer And Method For Producing The Same, As Well As Bonded Soi Wafer And Method For Producing The Same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6930026B2 (en) | Method of forming a semiconductor wafer having a crystalline layer thereon containing silicon, germanium and carbon | |
| US8043929B2 (en) | Semiconductor substrate and method for production thereof | |
| TWI382456B (en) | Epitaxial growth of relaxed silicon germanium layers | |
| EP0159252B1 (en) | Process for the production of semiconductor devices by using silicon-on-isolation techniques | |
| US7056789B2 (en) | Production method for semiconductor substrate and production method for field effect transistor and semiconductor substrate and field effect transistor | |
| JP3454033B2 (en) | Silicon wafer and manufacturing method thereof | |
| US6117231A (en) | Method of manufacturing semiconductor silicon single crystal wafer | |
| JP2713310B2 (en) | Method for manufacturing high-strength silicon wafer | |
| JP3081706B2 (en) | Substrate for semiconductor device | |
| WO2022158148A1 (en) | Method for manufacturing epitaxial wafer | |
| JP3344205B2 (en) | Method for manufacturing silicon wafer and silicon wafer | |
| JP4158607B2 (en) | Manufacturing method of semiconductor substrate | |
| JP4120163B2 (en) | Si epitaxial wafer manufacturing method and Si epitaxial wafer | |
| JPH11204534A (en) | Manufacture of silicon epitaxial wafer | |
| JPH06338464A (en) | Substrate for semiconductor device | |
| JPH09266212A (en) | Silicon wafer | |
| JPH0529234A (en) | Epitaxial crowing method | |
| Park et al. | Growth of polycrystalline silicon at low temperature on hydrogenated macrocrystalline silicon (μ c-Si: H) seed layer | |
| JP2004349522A (en) | Manufacturing method of semiconductor substrate | |
| JP3922674B2 (en) | Silicon wafer manufacturing method | |
| JP2774855B2 (en) | Gettering effect enhanced silicon substrate and method of manufacturing the same | |
| JPS6012775B2 (en) | Method for forming a single crystal semiconductor layer on a foreign substrate | |
| JP2001080992A (en) | Silicon wafer and production of the same | |
| JP3238957B2 (en) | Silicon wafer | |
| JPH09199379A (en) | High-quality epitaxial wafer and its manufacturing method |