JPH06334187A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06334187A
JPH06334187A JP5178430A JP17843093A JPH06334187A JP H06334187 A JPH06334187 A JP H06334187A JP 5178430 A JP5178430 A JP 5178430A JP 17843093 A JP17843093 A JP 17843093A JP H06334187 A JPH06334187 A JP H06334187A
Authority
JP
Japan
Prior art keywords
region
type
semiconductor region
semiconductor
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5178430A
Other languages
Japanese (ja)
Other versions
JP3116667B2 (en
Inventor
Masato Otsuki
正人 大月
Katsunori Ueno
勝典 上野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
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Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP05178430A priority Critical patent/JP3116667B2/en
Publication of JPH06334187A publication Critical patent/JPH06334187A/en
Application granted granted Critical
Publication of JP3116667B2 publication Critical patent/JP3116667B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744—Gate-turn-off devices
    • H01L29/745—Gate-turn-off devices with turn-off by field effect
    • H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thyristor Switches And Gates (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To speed up turn-off operation and reduce power loss during the operation by restoring dramatically a potential barrier caused by a pn junction between a P type base region and an n type cathode region when turning off in MCT structure and then setting control MISFET in an off state. CONSTITUTION:This semiconductor device comprises an MCT part 30 and an IGBT part 40 where the MCT part provides a first MOSFET 21 and a second MOSFET 22, which share a gate electrode 19 while the IGBT provides a third MOSFET 23 which can be controlled independently. When turning off, the third FET 23 remains in an ON state while the first FET 21 is turned off and the second FET 22 is turned on. As a result, mainly, hole current flows by way of the second FET 22 while electronic current flows by way of the third FET 23 and separated into an electric current passage per carrier, which forces the electronic current flowing by way of a pn junction to disappear. As a result, a potential barrier produced by this pn junction is dramatically restored. Immediately after the barrier is restored, the second and the third MOSFETs 22 and 23 are turned off.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、パワーデバイスなどに
用いられるｐｎｐｎ構造を有する半導体装置の構成に関
し、特に、２つのゲート電極を有するダブルゲート型半
導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device having a pnpn structure used for a power device or the like, and more particularly to a double gate type semiconductor device having two gate electrodes.

【０００２】[0002]

【従来の技術】パワーエレクトロニクスにおける高性
能，小型化および低コスト化などの課題を解決するため
の最も重要なキーテクノロジーの１つとして、パワーデ
バイスの低損失化が挙げられ、オン電圧が低く、また、
ターンオフ時間が短いデバイスの開発が各方面で活発に
行なわれている。たとえば、バイポーラトランジスタに
ついては、高性能，高耐圧および大電流化が図られ、ま
た、種々の保護機能を内蔵したインテリジェントモジュ
ールも登場している。また、ＩＧＢＴ（伝導度変調型ト
ランジスタ）においては、高速応答を可能としたものも
登場している。これらのパワーデバイスは、バッテリー
により駆動され持ち運びが簡単なように小型化された電
気製品、インバータ装置、また、環境保護の面から採用
が検討されている電気自動車などに適用され、省電力化
の一役を担っている。そして、近年益々増大する電力需
要に対応するために、これらのパワー半導体デバイスに
対してもさらに省電力低損失化が要求されている。2. Description of the Related Art One of the most important key technologies for solving the problems of high performance, miniaturization, and cost reduction in power electronics is to reduce the loss of power devices and to reduce the on-voltage. Also,
Devices with short turn-off times are being actively developed in various fields. For example, with regard to bipolar transistors, high performance, high breakdown voltage and high current have been achieved, and intelligent modules incorporating various protection functions have also appeared. In addition, as IGBTs (conductivity modulation type transistors), those capable of high-speed response have also appeared. These power devices are applied to battery-driven miniaturized electric products that are easy to carry, inverter devices, and electric vehicles that are being considered for environmental protection. Play a role. In order to meet the increasing demand for electric power in recent years, further power saving and low loss are required for these power semiconductor devices.

【０００３】例えば、サイリスタ構造によるオン電圧の
低減、およびＭＯＳゲートデバイスによる高速，低駆動
電力化を目的としたＭＣＴ（ＭＯＳゲート・コントロー
ル・サイリスタ）が開発されている。このＭＣＴは、図
１０，図１１に示すような構造及び等価回路を有するデ
バイスであり、V.A.K.Templeの発表したペーパー（”MO
S controlled thyristors" IEEE International Electr
on Device Meeting Digest 1984 ）などに詳しい。この
ＭＣＴの構造は、アノード電極１が形成されたｐ+ 型の
半導体基板のアノード層２と、この上に形成されたｎ+
型のバッファ層３と、この上に形成されたｎ- 型のベー
ス層４と、このｎ- 型のベース層４の主面側に形成され
たウェル状のｐ型のベース領域５と、このｐ型のベース
領域５の主面側に形成されたウェル状のｎ型のカソード
領域６と、このｎ型のカソード領域６の主面側に形成さ
れたｐ+ 型のドレイン領域７と、このカソード領域６の
周縁部及びｐ型のベース領域５をバックゲート（チャネ
ル領域）としドレイン領域７からｎ- 型のベース層４に
亘ってゲート絶縁膜８を介して形成された単一のゲート
電極９と、ｎ型のカソード領域６及びｐ+ 型のドレイン
領域７の双方に導電接触するカソード電極１０とを有し
ている。ゲート電極９はオン用ＭＯＳＦＥＴ１２とオフ
用ＭＯＳＦＥＴ１４を併有しており、オン用ＭＯＳＦＥ
Ｔ１２は、ｐ型のベース領域５をバックゲート（チャネ
ル領域）とし、カソード領域６をソース領域とすると共
にｎ- 型のベース層４をドレイン領域とするｎチャネル
型の絶縁ゲート型電界効果トランジスタであり、オフ用
ＭＯＳＦＥＴ１４は、ドレイン領域７を有し、カソード
領域６をバックゲート（チャネル領域）とすると共にｐ
型のベース領域５をソース領域とするｐチャネル型の絶
縁ゲート型電界効果トランジスタである。また、ｐ+ 型
のアノード層２，ｎ+ 型のバッファ層３，ｎ- 型のベー
ス層４及びｐ型のベース領域５はｐｎｐ型バイポーラト
ランジスタＱpnpを構成しており、ｎ- 型のベース層
４，ｐ型のベース領域５及びｎ型のカソード領域６はｎ
ｐｎ型バイポーラトランジスタＱnpn を構成している。For example, an MCT (MOS gate control thyristor) has been developed for the purpose of reducing the on-voltage by a thyristor structure and high speed and low driving power by a MOS gate device. This MCT is a device having a structure and an equivalent circuit as shown in FIGS. 10 and 11, and is a paper published by VAK Temple ("MO
S controlled thyristors "IEEE International Electr
on Device Meeting Digest 1984). The structure of this MCT is such that the anode layer 2 of the p + type semiconductor substrate on which the anode electrode 1 is formed and the n + layer formed on the anode layer 2 are formed.
Type buffer layer 3, an n − type base layer 4 formed thereon, a well-shaped p type base region 5 formed on the main surface side of the n − type base layer 4, A well-shaped n-type cathode region 6 formed on the main surface side of the p-type base region 5, ap + -type drain region 7 formed on the main surface side of the n-type cathode region 6, and A single gate electrode formed using the peripheral portion of the cathode region 6 and the p-type base region 5 as a back gate (channel region) and extending from the drain region 7 to the n − -type base layer 4 via the gate insulating film 8. 9 and a cathode electrode 10 in conductive contact with both the n-type cathode region 6 and the p + -type drain region 7. The gate electrode 9 has an ON MOSFET 12 and an OFF MOSFET 14 together, and has an ON MOSFET.
T12 is an n-channel insulated gate field effect transistor having the p-type base region 5 as a back gate (channel region), the cathode region 6 as a source region, and the n − -type base layer 4 as a drain region. The off MOSFET 14 has a drain region 7, uses the cathode region 6 as a back gate (channel region) and p
Is a p-channel type insulated gate field effect transistor whose source region is the base region 5 of the mold. Further, the p + -type anode layer 2, the n + -type buffer layer 3, the n − -type base layer 4 and the p-type base region 5 form a pnp-type bipolar transistor Q pnp , and the n − -type base layer is formed. The layer 4, the p-type base region 5 and the n-type cathode region 6 are n
It constitutes a pn-type bipolar transistor Q npn .

【０００４】先ず、ゲート電極９に高電位を印加する
と、オン用ＭＯＳＦＥＴ１２が導通し、オフ用ＭＯＳＦ
ＥＴ１４は遮断状態のままである。このオン用ＭＯＳＦ
ＥＴ１２の導通によって、カソード電極１０，カソード
領域６，オン用ＭＯＳＦＥＴ１２のチャネル部を介して
ｎ- 型のベース層４へその多数キャリア（電子）が注入
されるので、それに呼応してアノード電極１，アノード
領域２及びバッファ層３を介してｎ- 型のベース層４へ
少数キャリア（正孔）が流入し、ｎ- 型のベース層４の
伝導度が変調される。これによりトランジスタＱpnp が
オンするので、トランジスタＱnpn もオンし、サイリス
タｐｎｐｎがターンオンする。このサイリスタのオン状
態では、図１２（ａ）に示すように、オン用ＭＯＳＦＥ
Ｔ１２を介した電子電流（図示実線矢印）が流れている
と共に、ｎ型カソード領域６とｐ型ベース領域５の接合
を介した正孔電流（図示破線矢印）及び電子電流が流れ
ており、ｎ型カソード領域６とｐ型ベース領域５のｐｎ
接合は順バイアスされている。First, when a high potential is applied to the gate electrode 9, the on-MOSFET 12 becomes conductive and the off-MOSF is turned on.
ET14 remains blocked. This on MOSF
Due to conduction of the ET 12, the majority carriers (electrons) are injected into the n − -type base layer 4 through the cathode electrode 10, the cathode region 6, and the channel portion of the MOSFET 12 for ON, and accordingly, the anode electrode 1, through the anode region 2 and the buffer layer 3 n - -type minority carriers (holes) flow into the base layer 4, n - conductivity type base layer 4 is modulated. This turns on the transistor Q pnp , turning on the transistor Q npn and turning on the thyristor pnpn. In the ON state of this thyristor, as shown in FIG.
An electron current (indicated by a solid arrow in the figure) is flowing through T12, and a hole current (indicated by a dashed arrow in the figure) and an electron current are flowing through a junction between the n-type cathode region 6 and the p-type base region 5, and n Of the p-type cathode region 6 and the p-type base region 5
The junction is forward biased.

【０００５】次に、ゲート電極９に零又は負電位を印加
すると、オン用ＭＯＳＦＥＴ１２が遮断し、今度はオフ
用ＭＯＳＦＥＴ１４が導通する。このオフ用ＭＯＳＦＥ
Ｔ１４の導通によってｐ型のベース領域５の正孔（多数
キャリア）がそのチャネル，ドレイン領域７及びカソー
ド電極１０を介して引き抜かれるので、トランジスタＱ
npn がオフ状態となるため、トランジスタＱpnp もオフ
し、サイリスタｐｎｐｎがターンオフする。このよう
に、ＭＣＴは、ＭＯＳＦＥＴ１２のオンによりデバイス
をオンとするため、応答速度が速く、また、サイリスタ
をオン状態とするため、オン電圧も１Ｖ程度と非常に低
い。なお、ｎ+ 型のバッファ層３はアノード層２からｎ
- 型のベース層４への正孔（少数キャリア）の注入効率
を抑制してターンオフ時間を短縮するために形成されて
いる。Next, when zero or a negative potential is applied to the gate electrode 9, the on MOSFET 12 is cut off and the off MOSFET 14 is turned on this time. This off MOSFET
Due to the conduction of T14, holes (majority carriers) in the p-type base region 5 are extracted through the channel, drain region 7 and cathode electrode 10, so that the transistor Q
Since npn is turned off, the transistor Q pnp is also turned off and the thyristor pnpn is turned off. As described above, the MCT turns on the device by turning on the MOSFET 12, and therefore has a high response speed. Further, since the thyristor is turned on, the on-voltage is very low, about 1V. The n + -type buffer layer 3 is formed from the anode layer 2 to the n-type buffer layer 3.
- is formed in order to reduce the turn-off time by suppressing the injection efficiency of holes (minority carriers) type to the base layer 4.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、ｎ+ 型
のバッファ層３の形成によって、ターンオフ時にｎ- 型
のベース層４への正孔注入を抑制したとしても、これは
アノード電極１からの新たな正孔注入を抑制するもので
あり、デバイス内に蓄積されたキャリアの流れを直接抑
制するものではない。すなわち、サイリスタ動作時にお
いては、ｎ- 型のベース層４からｐ型ベース領域５を介
してｎ型カソード領域６へ正孔が流れ込み、またｎ型カ
ソード領域６からｐ型ベース領域５を介してｎ- 型のベ
ース層４へ電子が流れ込んでおり、ｐ型ベース領域５と
ｎ型カソード領域６のｐｎ接合が順バイアス状態でｐｎ
接合の電位障壁が無くなっているため、図１２（ｂ）に
示すように、ターンオフの初期においてはオフ用ＭＯＳ
ＦＥＴ１４の導通によってｐ型のベース領域５中の正孔
の吐き出しが開始されても、依然としてｐ型ベース領域
５とｎ型カソード領域６のｐｎ接合は正孔電流の電圧降
下で順バイアス状態にあり、その電位障壁がなかなか回
復せず、しばらくその接合を介して電子電流が流れ続け
る。このため、ＭＣＴにおいてはターンオフ時間が長く
なり、電力損失を招くという問題点があった。However, even if the formation of the n + -type buffer layer 3 suppresses the hole injection into the n − -type base layer 4 at the time of turn-off, this is a new phenomenon from the anode electrode 1. It suppresses the hole injection, and does not directly suppress the flow of carriers accumulated in the device. That is, during thyristor operation, holes flow from the n − -type base layer 4 to the n-type cathode region 6 through the p-type base region 5, and from the n-type cathode region 6 through the p-type base region 5. Electrons are flowing into the n − -type base layer 4, and the pn junction between the p-type base region 5 and the n-type cathode region 6 is forward biased to pn.
Since the potential barrier of the junction has disappeared, as shown in FIG.
Even if the discharge of holes in the p-type base region 5 is started by the conduction of the FET 14, the pn junction between the p-type base region 5 and the n-type cathode region 6 is still in the forward bias state due to the voltage drop of the hole current. , The potential barrier does not recover easily, and electron current continues to flow through the junction for a while. Therefore, in the MCT, there is a problem that the turn-off time becomes long and power loss occurs.

【０００７】そこで、本発明の課題は、上記問題点に鑑
み、ターンオフ時においてｐ型のベース領域とｎ型のカ
ソード領域とのｐｎ接合による電位障壁の回復を急速に
行なわせた後にＭＩＳＦＥＴをオフ状態とさせることに
より、ターンオフ動作の高速化を図り、ターンオフ時の
電力損失を低減可能の半導体装置を実現することにあ
る。Therefore, in view of the above problems, an object of the present invention is to turn off the MISFET after rapidly recovering the potential barrier by the pn junction between the p-type base region and the n-type cathode region at turn-off. The purpose of this is to realize a semiconductor device in which the turn-off operation can be speeded up and the power loss at the time of turn-off can be reduced by setting the state.

【０００８】[0008]

【課題を解決するための手段】上記課題を解決するため
に、本発明はＭＣＴの構造とＩＧＢＴの構造を併有する
ハイブリット構造を採用するものであり、ターンオフ時
の電流経路を変化させるため独立開閉可能の第３のＭＩ
ＳＦＥＴを設けたものである。即ち、本発明は、第１導
電型の第１半導体領域，第２導電型の第２半導体領域，
第１導電型の第３半導体領域及び第２導電型の第４半導
体領域とからなるサイリスタ構造と、第２導電型の第４
半導体領域の主面側に形成された第１導電型の第５半導
体領域と、第１導電型の第３半導体領域をバックゲート
（チャネル領域）とし第２導電型の第４半導体領域から
第２導電型の第２半導体領域に対しその多数キャリアを
注入可能の第１のＭＩＳＦＥＴと、第２導電型の第４半
導体領域をバックゲート（チャネル領域）とし第１導電
型の第３半導体領域から第１導電型の第５半導体領域に
対しその多数キャリアを引き抜き可能で第１のＭＩＳＦ
ＥＴのゲート電極を共用する第２のＭＩＳＦＥＴとを備
えた所謂ＭＣＴ構造の半導体装置において、第１導電型
の第３半導体領域の主面側においてそれを残して前記第
２導電型の第４半導体領域とは隔離した部位に形成され
た第２導電型の第６半導体領域と、第１導電型の第３半
導体領域をバックゲート（チャネル領域）とし第２導電
型の第６半導体領域から第２導電型の第２半導体領域に
対しその多数キャリアを注入可能で前記第１のＭＩＳＦ
ＥＴとは独立に開閉可能の第３のＭＩＳＦＥＴとを設け
たことを特徴とする。かかる構造においては、第１導電
型の第３半導体領域，第２導電型の第４半導体領域，第
１導電型の第５半導体領域及び第２導電型の第６半導体
領域の主面すべてに導電接触する電極部を設けても良い
し、また第２導電型の第４半導体領域，第１導電型の第
５半導体領域及び第２導電型の第６半導体領域の主面に
のみ導電接触する電極部を設けても良い。In order to solve the above-mentioned problems, the present invention adopts a hybrid structure having both an MCT structure and an IGBT structure, and has an independent switching for changing a current path at turn-off. Possible third MI
The SFET is provided. That is, the present invention provides a first conductivity type first semiconductor region, a second conductivity type second semiconductor region,
A thyristor structure including a third semiconductor region of the first conductivity type and a fourth semiconductor region of the second conductivity type; and a fourth semiconductor of the second conductivity type
A fifth semiconductor region of the first conductivity type formed on the main surface side of the semiconductor region and a third semiconductor region of the first conductivity type are used as a back gate (channel region) and a fourth semiconductor region of the second conductivity type to a second semiconductor region. A first MISFET capable of injecting majority carriers into the conductive second semiconductor region, and a second conductive fourth semiconductor region serving as a back gate (channel region) from a first conductive third semiconductor region It is possible to extract the majority carriers of the fifth semiconductor region of one conductivity type from the first MISF.
In a semiconductor device having a so-called MCT structure including a second MISFET sharing the gate electrode of ET, the fourth semiconductor of the second conductivity type is left on the main surface side of the third semiconductor region of the first conductivity type. The second conductive type sixth semiconductor region formed in a region separated from the region and the first conductive type third semiconductor region serving as a back gate (channel region) are formed from the second conductive type sixth semiconductor region to the second region. The majority carriers can be injected into the conductive second semiconductor region, and the first MISF can be injected.
It is characterized in that a third MISFET that can be opened and closed independently of ET is provided. In such a structure, the conductivity is applied to all the main surfaces of the third semiconductor region of the first conductivity type, the fourth semiconductor region of the second conductivity type, the fifth semiconductor region of the first conductivity type, and the sixth semiconductor region of the second conductivity type. An electrode portion which comes into contact may be provided, or an electrode which comes into conductive contact only with the main surfaces of the second conductive type fourth semiconductor region, the first conductive type fifth semiconductor region and the second conductive type sixth semiconductor region. Parts may be provided.

【０００９】第３，第４，第５及び第６半導体領域の主
面に導電接触する電極部を設けた場合においては、第３
半導体領域内で、少なくとも当該領域と第６半導体領域
との接合面近傍に第１導電型の高濃度半導体領域を形成
することが望ましい。この高濃度半導体領域は、第４半
導体領域の主面側境界にまで拡がり、第３半導体領域の
深さと同程度又はそれ以上の深さのウェル領域であって
も良いし、また第４半導体領域の主面側境界にまで拡が
り、第３半導体領域よりも浅いウェル領域であっても良
い。In the case where an electrode portion which is in conductive contact is provided on the main surfaces of the third, fourth, fifth and sixth semiconductor regions, the third portion is formed.
It is desirable to form a high-concentration semiconductor region of the first conductivity type in the semiconductor region at least in the vicinity of the junction surface between the region and the sixth semiconductor region. This high-concentration semiconductor region may extend to the boundary of the fourth semiconductor region on the main surface side and may be a well region having a depth equal to or greater than the depth of the third semiconductor region, or the fourth semiconductor region. It may be a well region that extends to the boundary on the main surface side and is shallower than the third semiconductor region.

【００１０】他方、第４，第５及び第６半導体領域の主
面にのみ導電接触する電極部を設けた場合においては、
第３半導体領域内に第１導電型の高濃度埋め込み領域を
形成した構造を採用できる。また第３半導体領域内で、
少なくとも当該領域と第６半導体領域との接合面近傍に
第１導電型の高濃度半導体領域を形成しても良い。この
高濃度半導体領域は、第４半導体領域の主面側境界にま
で拡がり、第３半導体領域の深さと同程度又はそれ以上
の深さのウェル領域であっても良いし、また第４半導体
領域の主面側境界にまで拡がり、第３半導体領域よりも
浅いウェル領域であっても良い。On the other hand, in the case where the electrode portions which are in conductive contact are provided only on the main surfaces of the fourth, fifth and sixth semiconductor regions,
A structure in which a high-concentration buried region of the first conductivity type is formed in the third semiconductor region can be adopted. In the third semiconductor region,
A first conductivity type high-concentration semiconductor region may be formed at least near the junction surface between the region and the sixth semiconductor region. This high-concentration semiconductor region may extend to the boundary of the fourth semiconductor region on the main surface side and may be a well region having a depth equal to or greater than the depth of the third semiconductor region, or the fourth semiconductor region. It may be a well region that extends to the boundary on the main surface side and is shallower than the third semiconductor region.

【００１１】[0011]

【作用】かかる半導体装置においては、ターンオン時は
従来のＭＣＴと同様に動作する。即ち、第１のＭＩＳＦ
ＥＴをオンさせると共に、第３のＭＩＳＦＥＴをオンさ
せると、第２導電型の第２半導体領域にその多数キャリ
アが注入されるので、第１導電型の第１半導体領域，第
２導電型の第２半導体領域及び第１導電型の第３半導体
領域で形成される第２導電型のバイポーラトランジスタ
がオン状態になるので、これにより第２導電型の第２半
導体領域，第１導電型の第３半導体領域及び第２導電型
の第４半導体領域で形成される第１導電型のバイポーラ
トランジスタがオン状態となり、ｐｎｐｎ構造のサイリ
スタがターンオンする。かかるオン状態においては、第
１及び第２のＭＩＳＦＥＴを介した多数キャリアが流れ
ている。また第１導電型の第３半導体領域と第２導電型
の第４半導体領域とのｐｎ接合を介して電流（多数キャ
リアと少数キャリアの電流）が流れており、その接合の
電位障壁は消滅している。When the semiconductor device is turned on, it operates in the same manner as the conventional MCT. That is, the first MISF
When ET is turned on and the third MISFET is turned on, the majority carriers are injected into the second conductivity type second semiconductor region, so that the first conductivity type first semiconductor region and the second conductivity type first semiconductor region are injected. Since the second conductivity type bipolar transistor formed of the second semiconductor region and the first conductivity type third semiconductor region is turned on, the second conductivity type second semiconductor region and the first conductivity type third transistor are thereby turned on. The first conductivity type bipolar transistor formed of the semiconductor region and the second conductivity type fourth semiconductor region is turned on, and the thyristor having the pnpn structure is turned on. In such an ON state, majority carriers are flowing through the first and second MISFETs. Further, a current (current of majority carrier and minority carrier) flows through the pn junction between the third semiconductor region of the first conductivity type and the fourth semiconductor region of the second conductivity type, and the potential barrier of the junction disappears. ing.

【００１２】次に、ターンオフの動作においては、先ず
第３のＭＩＳＦＥＴをオン状態に維持したまま、第１の
ＭＩＳＦＥＴをオフさせると共に、第２のＭＩＳＦＥＴ
をオンさせると、第２のＭＩＳＦＥＴを介して第１導電
型の第３半導体領域から多数キャリア（第２導電型の第
２半導体領域の少数キャリア）が引き抜かれる。この多
数引き抜き動作時においては第３のＭＩＳＦＥＴを介し
て第２導電型の第２半導体領域の多数キャリアが流れた
ままであるので、キャリアごとの電流経路が分離される
ことになる。このため、第１導電型の第３半導体領域と
第２導電型の第４半導体領域とのｐｎ接合を介して流れ
ようとする電流が消滅し、その電位障壁が急速に回復す
る。この直後の第２及び第３のＭＩＳＦＥＴをオフ状態
にすると、既に第１導電型の第３半導体領域と第２導電
型の第４半導体領域とのｐｎ接合に電位障壁が回復して
いるので、それを介した電流は生じない。このため、タ
ーンオフ時間を短縮することができ、電力損失を低減で
きる。Next, in the turn-off operation, the first MISFET is turned off and the second MISFET is turned on while the third MISFET is kept on.
Is turned on, the majority carriers (minority carriers in the second conductivity type second semiconductor region) are extracted from the first conductivity type third semiconductor region through the second MISFET. During this majority extraction operation, the majority carriers in the second conductivity type second semiconductor region are still flowing through the third MISFET, so that the current path for each carrier is separated. Therefore, the current that tends to flow via the pn junction between the first-conductivity-type third semiconductor region and the second-conductivity-type fourth semiconductor region disappears, and the potential barrier thereof is rapidly recovered. Immediately after this, when the second and third MISFETs are turned off, the potential barrier has already been restored in the pn junction between the third semiconductor region of the first conductivity type and the fourth semiconductor region of the second conductivity type. No current flows through it. Therefore, the turn-off time can be shortened and the power loss can be reduced.

【００１３】ここで、第１導電型の第３半導体領域，第
２導電型の第４半導体領域，第１導電型の第５半導体領
域及び第２導電型の第６半導体領域の主面にすべて導電
接触する電極部を設けた場合には、第１導電型の第３半
導体領域内に電極部に接続する寄生抵抗（拡散抵抗）が
存在することになるが、ターンオフ時にはこの拡散抵抗
を介しても電流が流れるので、上記ｐｎ接合に流れよう
とする電流を更に抑制することができる。従って、その
電位障壁の回復も更に急速であるので、ターンオフ時間
のなお一層の短縮化を達成できる。Here, all of the main surfaces of the third semiconductor region of the first conductivity type, the fourth semiconductor region of the second conductivity type, the fifth semiconductor region of the first conductivity type, and the sixth semiconductor region of the second conductivity type are all provided. In the case where the electrode portion in conductive contact is provided, a parasitic resistance (diffusion resistance) connected to the electrode portion exists in the third semiconductor region of the first conductivity type. Since a current also flows, it is possible to further suppress the current that tends to flow to the pn junction. Therefore, the recovery of the potential barrier is more rapid, and the turn-off time can be further shortened.

【００１４】第２導電型の第４半導体領域，第１導電型
の第５半導体領域及び第２導電型の第６半導体領域の主
面にのみ導電接触する電極部を設けた場合には、第２，
第３及び第４半導体領域で構成されるバイポーラトラン
ジスタがオンし易いので、オン電圧を低くできる。In the case where an electrode portion which is conductively contacted only with the main surface of the fourth semiconductor region of the second conductivity type, the fifth semiconductor region of the first conductivity type and the sixth semiconductor region of the second conductivity type is provided, Two
Since the bipolar transistor composed of the third and fourth semiconductor regions is easily turned on, the on voltage can be lowered.

【００１５】ここで、第３，第４，第５及び第６半導体
領域の主面に導電接触する電極部を設けた場合において
は、第３半導体領域内で、少なくとも当該領域と第６半
導体領域との接合面近傍に第１導電型の高濃度半導体領
域を形成することが望ましい。これは、第１導電型の高
濃度半導体領域が存在すると、電極に短絡する第６半導
体領域の接合面近傍の寄生抵抗が低抵抗化されているた
め、ターンオフ時においてその接合が順バイアスされ
ず、寄生トランジスタがオンし難くなる。従って、ラッ
チアップを抑制できるので、可制御ターンオフ電流の大
容量化を図ることができる。この高濃度半導体領域は、
第４半導体領域の主面側境界にまで拡がり、第３半導体
領域の深さと同程度又はそれ以上の深さのウェル領域で
あっても良いし、また第４半導体領域の主面側境界にま
で拡がり、第３半導体領域よりも浅いウェル領域であっ
ても良い。Here, in the case where an electrode portion which is in conductive contact is provided on the main surfaces of the third, fourth, fifth and sixth semiconductor regions, at least the region and the sixth semiconductor region are provided in the third semiconductor region. It is desirable to form a high-concentration semiconductor region of the first conductivity type in the vicinity of the bonding surface with. This is because the presence of the first-conductivity-type high-concentration semiconductor region reduces the parasitic resistance near the junction surface of the sixth semiconductor region short-circuited to the electrode, so that the junction is not forward-biased at turn-off. , It becomes difficult to turn on the parasitic transistor. Therefore, since latch-up can be suppressed, the controllable turn-off current can be increased in capacity. This high-concentration semiconductor region is
The well region may extend to the boundary of the fourth semiconductor region on the main surface side and have a depth that is substantially equal to or greater than the depth of the third semiconductor region, or may extend to the boundary of the fourth semiconductor region on the main surface side. The well region may be wider and shallower than the third semiconductor region.

【００１６】他方、第４，第５及び第６半導体領域の主
面にのみ導電接触する電極部を設けた場合において、第
３半導体領域内に第１導電型の高濃度埋め込み領域を形
成したときには、第２ＭＩＳＦＥＴによるキャリア引き
抜き時の第３半導体領域の電流経路の経路抵抗（拡散抵
抗）が低抵抗であるため、第６半導体領域の接合が順バ
イアスされず、寄生トランジスタがオンし難くなる。従
って、ラッチアップを抑制できるので、可制御ターンオ
フ電流の大容量化を図ることができる。また第３半導体
領域内で、少なくとも当該領域と第６半導体領域との接
合面近傍に第１導電型の高濃度半導体領域を形成しても
良い。かかる場合も、同様に、キャリア引き抜き時の第
３半導体領域の電流経路の経路抵抗（拡散抵抗）は低抵
抗である。この高濃度半導体領域は、第４半導体領域の
主面側境界にまで拡がり、第３半導体領域の深さと同程
度又はそれ以上の深さのウェル領域であっても良いし、
また第４半導体領域の主面側境界にまで拡がり、第３半
導体領域よりも浅いウェル領域であっても良い。On the other hand, in the case where the electrode portions which are in conductive contact are provided only on the main surfaces of the fourth, fifth and sixth semiconductor regions, when the high-concentration buried region of the first conductivity type is formed in the third semiconductor region. Since the path resistance (diffusion resistance) of the current path of the third semiconductor region at the time of extracting carriers by the second MISFET is low, the junction of the sixth semiconductor region is not forward biased and the parasitic transistor is hard to turn on. Therefore, since latch-up can be suppressed, the controllable turn-off current can be increased in capacity. Further, in the third semiconductor region, a high-concentration semiconductor region of the first conductivity type may be formed at least in the vicinity of the junction surface between the region and the sixth semiconductor region. In such a case as well, the path resistance (diffusion resistance) of the current path in the third semiconductor region at the time of carrier extraction is low similarly. The high-concentration semiconductor region may be a well region that extends to the boundary of the fourth semiconductor region on the main surface side and has a depth equal to or greater than the depth of the third semiconductor region.
Further, it may be a well region that extends to the boundary of the main surface side of the fourth semiconductor region and is shallower than the third semiconductor region.

【００１７】[0017]

【実施例】以下に図面を参照して、本発明の実施例を説
明する。Embodiments of the present invention will be described below with reference to the drawings.

【００１８】〔実施例１〕図１は本発明の実施例１に係
る半導体装置の構造を示す断面図である。この半導体装
置の構造は、アノード電極１が導電接触するｐ+ 型の半
導体基板のアノード層２と、この上に形成されたｎ+ 型
のバッファ層３と、この上に形成された伝導度変調層と
してのｎ- 型のベース層４と、このｎ- 型のベース層４
の主面側に形成されたウェル状のｐ型のベース領域５
と、このｐ型のベース領域５の主面側において一方に偏
倚させて形成されたウェル状のｎ型のカソード領域１６
と、ｐ型のベース領域５の主面側において他方に偏倚し
ておりカソード領域１６とは隔離した部位に形成された
ｎ+ 型のソース領域１８と、ｎ型のカソード領域１６の
主面側に形成されたｐ+ 型のドレイン領域１７と、ｐ型
のベース領域５の周縁部の一方側においてｎ型のカソー
ド領域１６及びそのｐ型のベース領域５をバックゲート
（チャネル領域）としドレイン領域１７からｎ- 型のベ
ース層４に亘ってゲート絶縁膜８を介して形成された共
用ゲート型の第１のゲート電極１９と、ｐ型のベース領
域５の周縁部の他方側においてそのｐ型のベース領域５
をバックゲート（チャネル領域）としソース領域１８か
らｎ- 型のベース層４に亘ってゲート絶縁膜８を介して
形成された第２のゲート電極２０と、ｐ+ 型のドレイン
領域１７，ｎ型のカソード領域１６，ｐ型のベース領域
５及びｎ+ 型のソース領域１８のそれぞれに導電接触す
るカソード電極１５とを有している。[Embodiment 1] FIG. 1 is a sectional view showing the structure of a semiconductor device according to Embodiment 1 of the present invention. This semiconductor device has a structure in which an anode layer 2 of a p + type semiconductor substrate with which an anode electrode 1 is in conductive contact, an n + type buffer layer 3 formed on the anode layer 2, and a conductivity modulation layer formed on the anode layer 2. N − type base layer 4 as a layer and this n − type base layer 4
Well-shaped p-type base region 5 formed on the main surface side of the
And a well-shaped n-type cathode region 16 formed so as to be biased to one side on the main surface side of the p-type base region 5.
And an n + -type source region 18 formed in a portion separated from the cathode region 16 on the main surface side of the p-type base region 5 and the main surface side of the n-type cathode region 16. And the p + -type drain region 17 formed on the first side, and the n-type cathode region 16 and the p-type base region 5 on one side of the peripheral edge of the p-type base region 5 as a back gate (channel region) 17 to the n − -type base layer 4 and the common gate-type first gate electrode 19 formed via the gate insulating film 8 and the p-type on the other side of the peripheral portion of the p-type base region 5. Base area 5
As a back gate (channel region), the second gate electrode 20 formed through the gate insulating film 8 from the source region 18 to the n − type base layer 4, the p + type drain region 17, the n type Of the cathode region 16, the p-type base region 5 and the n + -type source region 18 respectively.

【００１９】第１のゲート電極１９は多数キャリア注入
用の第１のＭＯＳＦＥＴ２１と多数キャリア引き抜き用
の第２のＭＯＳＦＥＴ２２とを併有しており、その第１
のＭＯＳＦＥＴ２１は、ｐ型のベース領域５をバックゲ
ート（チャネル領域）とし、カソード領域１６をソース
領域とすると共にｎ- 型のベース層４をドレイン領域と
するｎチャネル型の絶縁ゲート型電界効果トランジスタ
であり、第２のＭＯＳＦＥＴ２２は、ドレイン領域１７
を有し、カソード領域１６をバックゲート（チャネル領
域）とすると共にｐ型のベース領域５をソース領域とす
るｐチャネル型の絶縁ゲート型電界効果トランジスタで
ある。他方、第２のゲート電極２０は第１のゲート電極
１９とは独立にゲート電圧の制御が可能で、多数キャリ
ア注入用の第３のＭＯＳＦＥＴ２３を構成している。こ
の第３のＭＯＳＦＥＴ２３はソース領域１８を有し、ｐ
型のベース領域５をバックゲート（チャネル領域）とす
ると共にｎ- 型のベース層４をドレイン領域とするｎチ
ャネル型の絶縁ゲート型電界効果トランジスタである。The first gate electrode 19 has both a first MOSFET 21 for injecting majority carriers and a second MOSFET 22 for extracting majority carriers.
Of MOSFET 21 is an n-channel insulated gate field effect transistor having a p-type base region 5 as a back gate (channel region), a cathode region 16 as a source region, and an n − -type base layer 4 as a drain region. And the second MOSFET 22 has a drain region 17
And is a p-channel insulated gate field effect transistor having the cathode region 16 as a back gate (channel region) and the p-type base region 5 as a source region. On the other hand, the second gate electrode 20 can control the gate voltage independently of the first gate electrode 19, and constitutes a third MOSFET 23 for injecting majority carriers. The third MOSFET 23 has a source region 18 and p
This is an n-channel insulated gate field effect transistor in which the n - type base layer 4 is used as the back gate (channel region) and the n − -type base layer 4 is used as the drain region.

【００２０】この半導体装置の等価回路は、図２に示す
ように、図１１に示す従来のＭＣＴの等価回路とＩＧＢ
Ｔ（伝導度変調型ＭＯＳＦＥＴ）の等価回路を合わせた
回路構成を有している。即ち、この半導体装置は、ｐ+
型のアノード層２，ｎ+ 型のバッファ層３，ｎ- 型のベ
ース層４及びｐ型のベース領域５で形成されるｐｎｐ型
バイポーラトランジスタＱpnp と、ｎ- 型のベース層
４，ｐ型のベース領域５及びｎ型のカソード領域１６で
構成されるｎｐｎ型バイポーラトランジスタＱnp n とか
らなるｐｎｐｎ構造（サイリスタ構造）を有し、このｐ
ｎｐｎ構造を共用するＭＣＴ部３０とＩＧＢＴ部４０を
併有している。ＭＣＴ部３０は、トランジスタＱpnp ，
Ｑnpn と、トランジスタＱpnp のｎ- 型のベース層４と
ｎ型のカソード領域１６とを導通・遮断するｎチャネル
型の第１のＭＯＳＦＥＴ２１と、トランジスタＱnpn の
ｐ型のベース領域５とｐ+ 型のドレイン領域１７とを導
通・遮断するｐ型の第２のＭＯＳＦＥＴ２２とから構成
され、またＩＧＢＴ部４０は、トランジスタＱpnp ，Ｑ
npn と、トランジスタＱpnp のｎ- 型のベース層４とｎ
+ 型のソース領域１８を導通・遮断するｎ型の第３のＭ
ＯＳＦＥＴ２３とから構成されている。なお、本例にお
いては、カソード電極１５がｎ型のカソード領域１６と
ｎ+ 型のソース領域１８との間のｐ型のベース領域５の
一部にも導電接触された構造であるので、ｐ型のベース
領域５内の拡散抵抗Ｒがカソード電極１５に接続されて
いる。The equivalent circuit of this semiconductor device is, as shown in FIG. 2, an equivalent circuit of the conventional MCT shown in FIG.
It has a circuit configuration in which an equivalent circuit of T (conductivity modulation type MOSFET) is combined. That is, this semiconductor device has p +
-Type anode layer 2, n + -type buffer layer 3, n − -type base layer 4 and p-type base region 5 and a pnp-type bipolar transistor Q pnp , and n − -type base layer 4 and p-type Has a pnpn structure (thyristor structure) composed of an npn-type bipolar transistor Q np n composed of the base region 5 and the n-type cathode region 16.
Both the MCT section 30 and the IGBT section 40 sharing the npn structure are included. The MCT unit 30 includes a transistor Q pnp ,
Q npn , the first n-channel MOSFET 21 for electrically connecting and disconnecting the n − -type base layer 4 and the n-type cathode region 16 of the transistor Q pnp , and the p-type base region 5 and p of the transistor Q npn. The p-type second MOSFET 22 for connecting / disconnecting the + -type drain region 17 is provided, and the IGBT section 40 includes the transistors Q pnp , Q.
npn and the n − -type base layer 4 and n of the transistor Q pnp
The n-type third M that conducts / blocks the + type source region 18
It is composed of the OSFET 23. In this example, since the cathode electrode 15 is also in conductive contact with part of the p-type base region 5 between the n-type cathode region 16 and the n + -type source region 18, p The diffused resistance R in the base region 5 of the mold is connected to the cathode electrode 15.

【００２１】ゲート電極１９とゲート電極２０に高電位
を印加すると、その直下のｐ型のベース領域５の主面側
に反転層が形成され、第１のＭＯＳＦＥＴ２１と第３の
ＭＯＳＦＥＴ２３が共にオンし、ｎ型のカソード領域１
６からｎ- 型のベース層４の一方へ多数キャリア（電
子）が注入されると共に、ｎ+ 型のソース領域１８から
ｎ- 型のベース層４の他方へ多数キャリア（電子）が注
入される。これによりｎ- 型のベース層４の伝導度が変
調され、アノード層２，バッファ層３，ｎ- 型のベース
層４及びｐ型のベース領域５で形成されるトランジスタ
Ｑpnp がオンすると共に、ｎ- 型のベース層４，ｐ型の
ベース領域５及びｎ型のカソード領域１６で形成される
トランジスタＱnpn もオンし、ｐｎｐｎ構造のサイリス
タがターンオンする。このターンオン時の電流経路は、
図３（ａ）に示すように、第１のＭＯＳＦＥＴ２１及び
第３のＭＯＳＦＥＴ２３を介した電子電流（実線矢印）
と、ｐ型のベース領域５とｎ型のカソード領域１６の接
合を介した電子電流及び正孔電流（破線矢印）と、カソ
ード領域１６の拡散抵抗（短絡抵抗）を介した電子電流
及び正孔電流が存在する。When a high potential is applied to the gate electrode 19 and the gate electrode 20, an inversion layer is formed on the main surface side of the p-type base region 5 immediately thereunder, and the first MOSFET 21 and the third MOSFET 23 are both turned on. , N-type cathode region 1
The majority carriers (electrons) are injected from 6 to one of the n − type base layers 4, and the majority carriers (electrons) are injected from the n + type source region 18 to the other of the n − type base layer 4. . Thereby, the conductivity of the n − type base layer 4 is modulated, the transistor Q pnp formed by the anode layer 2, the buffer layer 3, the n − type base layer 4 and the p type base region 5 is turned on, and The transistor Q npn formed by the n − type base layer 4, the p type base region 5, and the n type cathode region 16 is also turned on, and the thyristor of the pnpn structure is turned on. The current path at turn-on is
As shown in FIG. 3A, an electron current (solid arrow) through the first MOSFET 21 and the third MOSFET 23.
, Electron current and hole current (broken line arrow) through the junction of the p-type base region 5 and n-type cathode region 16, and electron current and hole through the diffusion resistance (short-circuit resistance) of the cathode region 16. There is an electric current.

【００２２】次に、本デバイスのターンオフ動作時にお
いては、先ずゲート電極２０の電位を高電位のまま維持
し、ゲート電極１９に零又は負電位を印加すると、ゲー
ト電極１９の直下のｐ型のベース領域５の反転層は消滅
するが、ｎ型のカソード領域１６の表面に反転層が形成
されるため、第３のＭＯＳＦＥＴ２３はオン状態のまま
で、第１のＭＯＳＦＥＴ２１がオフ状態となると共に第
２のＭＯＳＦＥＴ２２がオン状態となる。これにより、
図３（ｂ）に示すように、ｐ型のベース領域５内の多数
キャリア（正孔）は第２のＭＯＳＦＥＴ２２により引き
抜かれる。この多数キャリア引き抜き動作は従来と同様
であるが、第２のＭＯＳＦＥＴ２２による引き抜き動作
時には第３のＭＯＳＦＥＴ２３もオン状態であり、これ
により電子電流がｎ- 型のベース層４からソース領域１
８へ流れており、ＩＧＢＴ動作が行なわれている。そし
て、主たる正孔電流の経路はｐ型のベース領域５の一方
側で、主たる電子電流の経路はｐ型のベース領域５の他
方側であり、ｐ型のベース領域５とｎ型のカソード領域
１６の接合を介した電流密度が非常に希薄になるため、
急速に順バイアス状態が解消され、ｎ型のカソード領域
１６の正孔引き抜き後、直ちにそのｐｎ接合の電位障壁
が回復する。この後直ちに第２のＭＯＳＦＥＴ２２及び
第３のＭＯＳＦＥＴ２３をオフ状態にしても、既に回復
した電位障壁の回復によって、その接合を介して電子電
流は流れないので、ターンオフ時間を短縮することがで
き、電力損失を低減可能である。換言すると、ターンオ
フ時の初期においては第３のＭＯＳＦＥＴ２３を介して
電子電流を流しておき、第２のＭＯＳＦＥＴ２２を介し
て正孔電流を引き抜くことにより、ｐ型のベース領域５
とｎ型のカソード領域１６の接合を介する電子電流を希
薄化して抑制し、その電位障壁を急速に回復させた後、
第２及び第３のＭＯＳＦＥＴ２２，２３をオフ状態とす
るものである。ここで、本例においては、カソード領域
１６とソース領域１８との間は非形成領域としてｐ型の
ベース領域５が残されており、これにカソード電極１５
が導電接触されている。このため、ｐ型のベース領域５
内にカソード電極１５に接続する拡散抵抗（短絡抵抗）
Ｒが存在している。従って、第２のＭＯＳＦＥＴ２２の
オンによる正孔引き抜き動作時においては、電流の一部
がｐ型のベース領域５とｎ型のカソード領域１６の接合
を迂回してこの拡散抵抗Ｒを介して流れるので、その接
合の電位障壁の回復を更に速めている。従って、ターン
オフ速度の高速化に寄与している。ただ、この拡散抵抗
（短絡抵抗）Ｒが存在すると、ターンオン時におけるト
ランジスタＱnpn がオンし難く、オン電圧が若干高くな
る。Next, during the turn-off operation of this device, first, the potential of the gate electrode 20 is maintained at a high potential, and zero or a negative potential is applied to the gate electrode 19, so that the p-type transistor immediately below the gate electrode 19 is formed. Although the inversion layer in the base region 5 disappears, the inversion layer is formed on the surface of the n-type cathode region 16, so that the third MOSFET 23 remains in the on state and the first MOSFET 21 turns off and the first MOSFET 21 turns off. The second MOSFET 22 is turned on. This allows
As shown in FIG. 3B, the majority carriers (holes) in the p-type base region 5 are extracted by the second MOSFET 22. Although this majority carrier extraction operation is the same as the conventional one, the third MOSFET 23 is also in the ON state during the extraction operation by the second MOSFET 22, so that the electron current flows from the n − type base layer 4 to the source region 1.
8 and the IGBT operation is being performed. The main hole current path is on one side of the p-type base region 5 and the main electron current path is on the other side of the p-type base region 5, and the p-type base region 5 and the n-type cathode region 5 are connected. Since the current density through the 16 junctions is very dilute,
The forward bias state is rapidly eliminated, and the potential barrier of the pn junction is immediately restored after the holes are extracted from the n-type cathode region 16. Immediately after this, even if the second MOSFET 22 and the third MOSFET 23 are turned off, since the electric current does not flow through the junction due to the restoration of the potential barrier that has already been restored, the turn-off time can be shortened and the power consumption can be reduced. Loss can be reduced. In other words, in the initial stage of turn-off, an electron current is allowed to flow through the third MOSFET 23, and a hole current is drawn out through the second MOSFET 22, so that the p-type base region 5 is formed.
After diluting and suppressing the electron current through the junction between the n-type cathode region 16 and the n-type cathode region 16 and rapidly restoring the potential barrier,
The second and third MOSFETs 22 and 23 are turned off. Here, in this example, the p-type base region 5 is left as a non-formed region between the cathode region 16 and the source region 18, and the cathode electrode 15 is formed in this region.
Are in conductive contact. Therefore, the p-type base region 5
Diffusion resistance (short-circuit resistance) connected to the cathode electrode 15 inside
R is present. Therefore, during the hole extraction operation by turning on the second MOSFET 22, a part of the current bypasses the junction between the p-type base region 5 and the n-type cathode region 16 and flows through the diffusion resistance R. , The recovery of the potential barrier of the junction is further accelerated. Therefore, it contributes to a higher turn-off speed. However, if the diffused resistance (short-circuit resistance) R exists, the transistor Q npn is difficult to turn on at the time of turn-on, and the on-voltage becomes slightly higher.

【００２３】〔実施例２〕ところで、ベース領域５の拡
散抵抗（短絡抵抗）Ｒを介して流れる電流が大きすぎる
か、又は拡散抵抗Ｒ自体が大きすぎると、ＩＧＢＴ部４
０がラッチアップしてしまう。即ち、ｎ- 型のベース層
４，ｐ型のベース領域５及びｎ型のカソード領域１６は
サイリスタ構造のｎｐｎ型トランジスタＱnpn を構成し
ているが、図２の等価回路に示すように、ベース領域５
とソース領域１８のｐｎ接合はｎ-型のベース層４，ｐ
型のベース領域５及びｎ+ 型のソース領域１８で構成さ
れる寄生ｎｐｎ型トランジスタＱ′npn のベース・エミ
ッタ接合であり、寄生ｎｐｎ型トランジスタＱ′npn は
トランジスタＱnpn に並列接続している。このため、拡
散抵抗Ｒの電圧降下量が大きいと、ベース領域５とソー
ス領域１８のｐｎ接合が順バイアスされ、寄生トランジ
スタＱ′npn がオン状態となり、ＩＧＢＴ部４０がラッ
チアップするおそれがある。このラッチアップが起これ
ば、第３ＭＯＳＦＥＴ２３をオフしてもサイリスタがタ
ーンオフしないことになる。このようにＭＣＴ部３０と
ＩＧＢＴ部４０の併存する構造においては、今度はＩＧ
ＢＴ部４０の寄生トランジスタＱ′npn が軽視できず、
ターンオフ時にラッチアップしてしまう新たな問題が生
じ、可制御ターンオフ電流（電流容量）を大きくするこ
とができなくなる。[Embodiment 2] By the way, if the current flowing through the diffusion resistance (short circuit resistance) R of the base region 5 is too large, or the diffusion resistance R itself is too large, the IGBT section 4 will be described.
0 will latch up. That is, the n − -type base layer 4, the p-type base region 5 and the n-type cathode region 16 form an npn-type transistor Q npn having a thyristor structure, but as shown in the equivalent circuit of FIG. Area 5
And the pn junction between the source region 18 and the n − type base layer 4, p
'Is a npn of the base-emitter junction, a parasitic npn-type transistors Q' parasitic npn-type transistors Q consists of type base region 5 and n + -type source region 18 npn is connected in parallel to the transistor Q npn. Therefore, if the voltage drop amount of the diffusion resistance R is large, the pn junction between the base region 5 and the source region 18 is forward biased, the parasitic transistor Q ′ npn is turned on, and the IGBT unit 40 may latch up. If this latch-up occurs, the thyristor will not turn off even if the third MOSFET 23 is turned off. Thus, in the structure in which the MCT section 30 and the IGBT section 40 coexist, the IG
The parasitic transistor Q ′ npn of the BT unit 40 cannot be neglected,
A new problem of latch-up at turn-off occurs, and the controllable turn-off current (current capacity) cannot be increased.

【００２４】図４は本発明の実施例２に係る半導体装置
の構造を示す断面図である。この実施例２に係る半導体
構造は上記の新たな問題点を解決するものであり、ｐ型
のベース領域５内においてはこれとｎ+ 型のソース領域
１８の接合面近傍部位を含んだ領域にｐ+ 型のウェル２
５が形成されている。この高濃度のウェル２５は深く形
成されている。ここで、例えばｐ型のベース領域５の濃
度は１×１０16〜５×１０17cm-3，深さは２〜２０μｍ
で、ｐ+ 型のウェル２５は１×１０17〜５×１０19cm
-3, 深さは２〜２０μｍに設定される。勿論、ウェル２
５の深さはベース領域５の深さと同程度であっても良い
し、またそれ以上の深さでも良い。この高濃度のウェル
２５における表面側の拡がり部分は、第３のＭＯＳＦＥ
Ｔ２３のチャネル部にかからないよう接合面をカバース
するように形成する。これは接合面の周囲に分布する拡
散抵抗ＲB を低減するためである。また本例においては
カソード電極１５直下のカソード領域１６とソース領域
１８に挟まれた部位も高濃度化されており、全体として
拡散抵抗Ｒの値を小さく設定してある。FIG. 4 is a sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention. The semiconductor structure according to the second embodiment solves the above-mentioned new problem. In the p-type base region 5, the semiconductor structure is formed in a region including a portion near the junction surface between the p-type base region 5 and the n + -type source region 18. p + type well 2
5 is formed. The well 25 of high concentration is deeply formed. Here, for example, the p-type base region 5 has a concentration of 1 × 10 16 to 5 × 10 17 cm −3 and a depth of 2 to 20 μm.
And the p + type well 25 has a size of 1 × 10 17 to 5 × 10 19 cm.
-3, the depth is set to 2 to 20 μm. Of course, well 2
The depth of 5 may be the same as the depth of the base region 5, or may be more than that. The expanded portion of the high-concentration well 25 on the surface side is the third MOSFE.
It is formed so as to cover the joint surface so as not to cover the channel portion of T23. This is to reduce the diffusion resistance R B distributed around the joint surface. Further, in this example, the region sandwiched between the cathode region 16 and the source region 18 immediately below the cathode electrode 15 is also highly concentrated, and the value of the diffusion resistance R is set small as a whole.

【００２５】このような深いｐ+ 型のウェル２５を設け
た構造は、いわばバイポーラトランジスタのグラフトベ
ース（graft base) 構造と同様な構造を発揮する。即
ち、図４に示す拡散抵抗ＲB を含めた抵抗Ｒが低抵抗化
する。従って、サイリスタのターンオフ時においてｐ型
のベース領域５とｎ+ 型のソース領域１８の接合面近傍
部位に瞬間的に増加する電流が流れても、電圧降下量が
大きくならず、その接合が順バイアスされずに済み、寄
生トランジスタＱ′npn が作動しない。これによってラ
ッチアップを防止することができ、可制御ターンオフ電
流を大きくすることが可能となる。The structure provided with such a deep p + type well 25 exhibits, so to speak, a structure similar to the graft base structure of a bipolar transistor. That is, the resistance R including the diffusion resistance R B shown in FIG. 4 is lowered. Therefore, even when an instantaneously increasing current flows in the vicinity of the junction surface between the p-type base region 5 and the n + -type source region 18 when the thyristor is turned off, the amount of voltage drop does not increase, and the junction is normally formed. It does not have to be biased and the parasitic transistor Q'npn does not work. This makes it possible to prevent latch-up and increase the controllable turn-off current.

【００２６】〔実施例３〕図５は本発明の実施例３に係
る半導体装置の構造を示す断面図である。この実施例３
に係る半導体構造も上記の新たな問題を解決するもので
ある。実施例２の構造と異なり、ｐ型のベース領域５よ
りも浅い高濃度のｐ+ 型のウェル２６が形成されてい
る。ｐ+ 型のウェル２６は、ｐ型のベース領域５内にお
いて、これとｎ+ 型のソース領域１８の接合面近傍部位
を含んでいる。ここで、例えばｐ型のベース領域５の濃
度は１×１０16〜５×１０17cm-3，深さは２〜２０μｍ
で、ｐ+ 型のウェル２６は１×１０18〜１×１０20cm
-3, 深さは０．５〜２μｍに設定される。実施例２にお
けるウェル２５は深い拡散により形成されるので、高濃
度化が不十分な場合もあり、またウェル２５とベース５
の境界が傾斜濃度となってしまうので、境界を第３のＭ
ＯＳＦＥＴ２３のチャネル部までギリギリに近接させる
ことは難しい。しかし、本例の浅いｐ+ 型のウェル２６
では、フォトプロセスにより段階濃度の境界を第３のＭ
ＯＳＦＥＴ２３のチャネル部及びカソード領域１６の主
面側境界までギリギリに接近させることが可能で、且つ
高濃度化が容易である。即ち、実施例２の構造に比べ
て、拡散抵抗ＲB を含めた抵抗Ｒの低抵抗化が確実であ
る。本例もまたターンオフ時のラッチアップの抑制を確
実に実現でき、可制御ターンオフ電流を大容量化でき
る。なお、本例の浅いｐ+ 型のウェル２６と実施例２の
深いウェル２５とが併存する構造を採用しても良い。[Third Embodiment] FIG. 5 is a sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention. This Example 3
The semiconductor structure according to the present invention also solves the above new problem. Unlike the structure of the second embodiment, a high concentration p + -type well 26 shallower than the p-type base region 5 is formed. The p + type well 26 includes, in the p type base region 5, a portion in the vicinity of a junction surface between the p + type well region 5 and the n + type source region 18. Here, for example, the p-type base region 5 has a concentration of 1 × 10 16 to 5 × 10 17 cm −3 and a depth of 2 to 20 μm.
And the p + type well 26 has a size of 1 × 10 18 to 1 × 10 20 cm.
-3, the depth is set to 0.5-2 μm. Since the well 25 in the second embodiment is formed by deep diffusion, the high concentration may be insufficient in some cases, and the well 25 and the base 5 may be formed.
Since the boundary of M becomes the gradient density, the boundary of the third M
It is difficult to bring the channel portion of the OSFET 23 close to the end. However, the shallow p + type well 26 of this example is
Then, the boundary of the step density is set to the third M by the photo process.
The channel portion of the OSFET 23 and the boundary of the main surface side of the cathode region 16 can be brought close to each other, and the concentration can be easily increased. That is, the resistance of the resistance R including the diffusion resistance R B can be surely lowered as compared with the structure of the second embodiment. Also in this example, it is possible to surely suppress the latch-up at turn-off and increase the controllable turn-off current. A structure in which the shallow p + type well 26 of this example and the deep well 25 of Example 2 coexist may be adopted.

【００２７】〔実施例４〕図６は本発明の実施例４に係
る半導体装置の構造を示す断面図であり、図７は実施例
４の等価回路図を示す。図６及び図７において、実施例
１に係る図１及び図２に示す部分と同一部分には同一参
照符号を付し、その説明は省略する。[Embodiment 4] FIG. 6 is a sectional view showing the structure of a semiconductor device according to Embodiment 4 of the present invention, and FIG. 7 is an equivalent circuit diagram of Embodiment 4. 6 and 7, the same parts as those shown in FIGS. 1 and 2 according to the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

【００２８】この半導体装置の実施例１のものと異なる
点は、カソード電極１５ａ，１５ｂの構造にある。即
ち、カソード領域１６とソース領域１８との間は非形成
領域としてｐ型のベース領域５が残されているが、これ
にはカソード電極が導電接触していない。カソード電極
は、電極部１５ａを以てドレイン領域１７及びカソード
領域１６に導電接触し、また電極部１５ｂを以てソース
領域１５ｂに導電接触している。従って、ｐ型のベース
領域５内には実施例１のようなカソード電極１５に接続
する拡散抵抗Ｒは存在しない。このため、ターンオフ時
にｐ型のベース領域５内のキャリアが直接カソード電極
に対して流れることはないので、ベース領域５とカソー
ド領域１６との接合による電位障壁の回復速度は実施例
１に比して若干遅くなるものの、ターンオン時にはトラ
ジスタＱnpn がオンし易いので、オン電圧を低くでき
る。勿論、本例においてもターンオフ時の初期に第３の
ＭＯＳＦＥＴ２３を介して電子電流を流しておき、第２
のＭＯＳＦＥＴ２２で正孔を引く抜くことにより、ｐ型
のベース領域５とｎ型のカソード領域１６の接合を介す
る電子電流を希薄化して抑制し、その電位障壁を急速に
回復させてから、第２及び第３のＭＯＳＦＥＴ２２，２
３をオフ状態とするものであるので、従来のＭＣＴに比
してターンオフ時間の短縮化が図れている。The difference from the semiconductor device according to the first embodiment is the structure of the cathode electrodes 15a and 15b. That is, the p-type base region 5 is left as a non-formed region between the cathode region 16 and the source region 18, but the cathode electrode is not in conductive contact therewith. The cathode electrode is in conductive contact with the drain region 17 and the cathode region 16 through the electrode portion 15a, and is in conductive contact with the source region 15b through the electrode portion 15b. Therefore, in the p-type base region 5, there is no diffusion resistance R connected to the cathode electrode 15 as in the first embodiment. For this reason, carriers in the p-type base region 5 do not flow directly to the cathode electrode at the time of turn-off, so that the recovery rate of the potential barrier due to the junction between the base region 5 and the cathode region 16 is higher than that in the first embodiment. However, since the transistor Q npn is easily turned on at the time of turn-on, the on-voltage can be lowered. Of course, also in this example, an electron current is made to flow through the third MOSFET 23 at the initial stage of turn-off, and
By pulling out holes with the MOSFET 22 of, the electric current flowing through the junction between the p-type base region 5 and the n-type cathode region 16 is diluted and suppressed, and the potential barrier is rapidly restored, and then the second And the third MOSFETs 22, 2
Since 3 is turned off, the turn-off time can be shortened as compared with the conventional MCT.

【００２９】〔実施例５〕ところで、実施例４の構造に
おいても、図７の等価回路に示すように、ベース領域５
とソース領域１８のｐｎ接合はｎ- 型のベース層４，ｐ
型のベース領域５及びｎ+ 型のソース領域１８で構成さ
れる寄生ｎｐｎ型トランジスタＱ′npn のベース・エミ
ッタ接合であり、寄生ｎｐｎ型トランジスタＱ′npn は
トランジスタＱnpn に並列接続している。ベース領域５
はカソード電極１５ａ，１５ｂと直接導電接触していな
いため、実施例１〜３の構造におけるような電極に短絡
する拡散抵抗Ｒは存在せず、ターンオフ時にはベース領
域５内の正孔は専ら第２のＭＯＳＦＥＴ２２を介して引
き抜かれるが、その正孔電流が大きすぎる場合や、その
引き抜き経路の寄生ベース抵抗（拡散抵抗）Ｒ′B が大
きすぎると、その電圧降下量が大きくなり、ベース領域
５とソース領域１８のｐｎ接合が順バイアスされ、寄生
トランジスタＱ′npn がオン状態となり、ＩＧＢＴ部４
０がラッチアップするおそれがある。このラッチアップ
が起これば、第３ＭＯＳＦＥＴ２３をオフしてもサイリ
スタがターンオフしないことになる。実施例４において
も、ＩＧＢＴ部４０の寄生トランジスタＱ′npn が軽視
できず、ターンオフ時にラッチアップしてしまう新たな
問題が生じ、可制御ターンオフ電流（電流容量）を大き
くすることができなくなる。[Embodiment 5] By the way, also in the structure of Embodiment 4, as shown in the equivalent circuit of FIG.
And the pn junction between the source region 18 and the n − type base layer 4, p
'Is a npn of the base-emitter junction, a parasitic npn-type transistors Q' parasitic npn-type transistors Q consists of type base region 5 and n + -type source region 18 npn is connected in parallel to the transistor Q npn. Base area 5
Is not in direct conductive contact with the cathode electrodes 15a and 15b, there is no diffusion resistance R that short-circuits the electrodes as in the structures of Examples 1 to 3, and at the time of turn-off, holes in the base region 5 are exclusively second. However, if the hole current is too large, or if the parasitic base resistance (diffusion resistance) R ′ B of the extraction path is too large, the voltage drop amount becomes large, and The pn junction of the source region 18 is forward-biased, the parasitic transistor Q ′ npn is turned on, and the IGBT part 4 is turned on.
0 may latch up. If this latch-up occurs, the thyristor will not turn off even if the third MOSFET 23 is turned off. Also in the fourth embodiment, the parasitic transistor Q ′ npn of the IGBT section 40 cannot be neglected, and a new problem arises in that the parasitic transistor Q ′ npn latches up at turn-off, and the controllable turn-off current (current capacity) cannot be increased.

【００３０】図８は本発明の実施例５に係る半導体装置
の構造を示す断面図である。この実施例５に係る半導体
構造は上記の新たな問題点を解決するものであり、ｐ型
のベース領域５内においてはこれとｎ+ 型のソース領域
１８の接合面近傍部位の直下も含みｐ+ 型の埋め込み領
域２７が形成されている。この高濃度の埋め込み領域２
７はソース領域１８のうち第３のＭＯＳＦＥＴ２３のチ
ャネル部の直下から第２のＭＯＳＦＥＴ２２のチャネル
部の直下にわたり形成することが望ましい。引き抜かれ
る正孔の長い経路をすべて高濃度化し、低抵抗化するた
めである。従って、サイリスタのターンオフ時において
引き抜かれる正孔電流が多くても、寄生ベース抵抗（拡
散抵抗）Ｒ′B による電圧降下量が大きくならず、ｐ型
のベース領域５とｎ+ 型のソース領域１８の接合が順バ
イアスされずに済み、寄生トランジスタＱ′npn が作動
しない。これによってラッチアップを防止することがで
き、可制御ターンオフ電流を大きくすることが可能とな
る。FIG. 8 is a sectional view showing the structure of a semiconductor device according to the fifth embodiment of the present invention. The semiconductor structure according to the fifth embodiment solves the above-mentioned new problem. In the p-type base region 5, the p-type base region 5 and the n + -type source region 18 are also included immediately below the junction plane. A + type embedded region 27 is formed. This high-concentration embedded region 2
It is desirable that 7 is formed in the source region 18 immediately below the channel portion of the third MOSFET 23 to immediately below the channel portion of the second MOSFET 22. This is to increase the concentration of all the long paths of the extracted holes and reduce the resistance. Therefore, even if a large amount of hole current is extracted when the thyristor is turned off, the amount of voltage drop due to the parasitic base resistance (diffusion resistance) R ′ B does not increase, and the p-type base region 5 and the n + -type source region 18 are formed. Is not forward biased and the parasitic transistor Q'npn does not work. This makes it possible to prevent latch-up and increase the controllable turn-off current.

【００３１】〔実施例６〕図９は本発明の実施例６に係
る半導体装置の構造を示す断面図である。この実施例６
に係る半導体構造も上記の新たな問題を解決するもので
ある。実施例５の構造と異なり、ｐ型のベース領域５内
においてはこれとｎ+ 型のソース領域１８の接合面近傍
部位を含んだ領域にｐ+ 型のウェル２８が形成されてい
る。この高濃度のウェル２８は深く形成されている。こ
こで、例えばｐ型のベース領域５の濃度は１×１０16〜
５×１０17cm-3，深さは２〜２０μｍで、ｐ+ 型のウェ
ル２５は１×１０17〜５×１０19cm-3, 深さは２〜２０
μｍに設定される。勿論、ウェル２８の深さはベース領
域５の深さと同程度であっても良いし、またそれ以上の
深さでも良い。また浅い別のｐ+ 型のウェルと併存した
構造でも良い。この高濃度のウェル２８における表面側
の拡がり部分は、第３のＭＯＳＦＥＴ２３のチャネル部
にかからないよう接合面をカバーするように形成する。
これは接合面の周囲に分布する拡散抵抗Ｒ′B を低減す
るためである。サイリスタのターンオフ時において引き
抜かれる正孔電流が多くても、寄生ベース抵抗（拡散抵
抗）Ｒ′B が低抵抗化されているため、その電圧降下量
が大きくならず、ｐ型のベース領域５とｎ+ 型のソース
領域１８の接合が順バイアスされずに済み、寄生トラン
ジスタＱ′npn が作動しない。これによってラッチアッ
プを防止することができ、可制御ターンオフ電流を大き
くすることが可能となる。なお、本例の高濃度のウェル
と実施例５における高濃度の埋め込み領域とが併存した
構造であっても良い。[Sixth Embodiment] FIG. 9 is a sectional view showing the structure of a semiconductor device according to a sixth embodiment of the present invention. This Example 6
The semiconductor structure according to the present invention also solves the above new problem. Unlike the structure of the fifth embodiment, in the p-type base region 5, a p + -type well 28 is formed in a region including the vicinity of the junction surface between this and the n + -type source region 18. The high-concentration well 28 is deeply formed. Here, for example, the concentration of the p-type base region 5 is 1 × 10 16 to
5 × 10 17 cm -3, the depth is 2 to 20 [mu] m, p + -type well 25 is 1 × 10 17 ~5 × 10 19 cm -3, the depth 2-20
It is set to μm. Of course, the depth of the well 28 may be about the same as the depth of the base region 5, or may be more than that. Further, it may have a structure coexisting with another shallow p + type well. The expanded portion of the high-concentration well 28 on the surface side is formed so as to cover the junction surface so as not to cover the channel portion of the third MOSFET 23.
This is to reduce the diffusion resistance R ′ B distributed around the joint surface. Even if a large amount of hole current is extracted when the thyristor is turned off, the parasitic base resistance (diffusion resistance) R ′ B is lowered, so that the voltage drop does not increase, and the p-type base region 5 and The junction of the n + type source region 18 is not forward biased, and the parasitic transistor Q ′ npn does not operate. This makes it possible to prevent latch-up and increase the controllable turn-off current. The high-concentration well of this example and the high-concentration buried region of the fifth embodiment may coexist.

【００３２】[0032]

【発明の効果】以上説明したように、本発明は、従来の
第１及び第２のＭＩＳＦＥＴを備えたＭＣＴ構造におい
て、いわばカソード領域を第４半導体領域と第６半導体
領域とに独立に分離し、第６半導体領域を用いて独立制
御可能の第３のＭＩＳＦＥＴを設けてＩＧＢＴ部を形成
した点に特徴を有するものである。従って、次の効果を
奏する。As described above, according to the present invention, in the conventional MCT structure including the first and second MISFETs, the cathode region is independently divided into the fourth semiconductor region and the sixth semiconductor region. , The sixth semiconductor region is used to provide an independently controllable third MISFET to form an IGBT part. Therefore, the following effects are obtained.

【００３３】 ターンオフの動作においては、先ず第
３のＭＩＳＦＥＴをオン状態に維持したまま、第１のＭ
ＩＳＦＥＴをオフさせると共に、第２のＭＩＳＦＥＴを
オンさせると、第２のＭＩＳＦＥＴを介して第１導電型
の第３半導体領域から多数キャリア（第２導電型の第２
半導体領域の少数キャリア）が引き抜かれる。この多数
引き抜き動作時においては第３のＭＩＳＦＥＴを介して
第２導電型の第２半導体領域の多数キャリアが流れたま
まであるので、キャリアごとの電流経路が分離される。
このため、第１導電型の第３半導体領域と第２導電型の
第４半導体領域とのｐｎ接合を介して流れようとする電
流が消滅し、その電位障壁が急速に回復する。この直後
の第２及び第３のＭＩＳＦＥＴをオフ状態にすると、既
に第１導電型の第３半導体領域と第２導電型の第４半導
体領域とのｐｎ接合に電位障壁が回復しているので、そ
れを介した電流は生じない。このため、ターンオフ時間
を短縮することができ、電力損失を低減できる。In the turn-off operation, first the first M-FET is kept on while the first M-FET is kept on.
When the ISFET is turned off and the second MISFET is turned on, the majority carriers (the second conductivity type second semiconductor layer) are transferred from the third semiconductor region of the first conductivity type through the second MISFET.
Minority carriers in the semiconductor region) are extracted. During this majority extraction operation, the majority carriers in the second conductivity type second semiconductor region still flow through the third MISFET, so that the current path for each carrier is separated.
Therefore, the current that tends to flow via the pn junction between the first-conductivity-type third semiconductor region and the second-conductivity-type fourth semiconductor region disappears, and the potential barrier thereof is rapidly recovered. Immediately after this, when the second and third MISFETs are turned off, the potential barrier has already been restored in the pn junction between the third semiconductor region of the first conductivity type and the fourth semiconductor region of the second conductivity type. No current flows through it. Therefore, the turn-off time can be shortened and the power loss can be reduced.

【００３４】 第１導電型の第３半導体領域，第２導
電型の第４半導体領域，第１導電型の第５半導体領域及
び第２導電型の第６半導体領域の主面にすべて導電接触
する電極部を設けた場合には、第１導電型の第３半導体
領域内に電極部に接続する寄生抵抗（拡散抵抗）が存在
することになるが、ターンオフ時にはこの拡散抵抗を介
しても電流が流れるので、上記ｐｎ接合に流れようとす
る電流を抑制することができる。従って、その電位障壁
の回復も更に急速であるので、ターンオフ時間のなお一
層の短縮化を達成できる。All of the main surfaces of the third semiconductor region of the first conductivity type, the fourth semiconductor region of the second conductivity type, the fifth semiconductor region of the first conductivity type, and the sixth semiconductor region of the second conductivity type are in conductive contact. When the electrode portion is provided, there is a parasitic resistance (diffusion resistance) connected to the electrode portion in the third semiconductor region of the first conductivity type. However, at the time of turn-off, current does not flow through this diffusion resistance. Since it flows, the current that tends to flow to the pn junction can be suppressed. Therefore, the recovery of the potential barrier is more rapid, and the turn-off time can be further shortened.

【００３５】 第４，第５及び第６半導体領域の主面
にのみ導電接触する電極部を設けた場合には、第２，第
３及び第４半導体領域で構成されるバイポーラトランジ
スタがオンし易いので、オン電圧を低くできる。When the electrode portions that are in conductive contact are provided only on the main surfaces of the fourth, fifth and sixth semiconductor regions, the bipolar transistor composed of the second, third and fourth semiconductor regions is easily turned on. Therefore, the on-voltage can be lowered.

【００３６】 第３，第４，第５及び第６半導体領域
の主面に導電接触する電極部を設けた場合において、第
３半導体領域内で、少なくとも当該領域と第６半導体領
域との接合面近傍に第１導電型の高濃度半導体領域が形
成されているときには、電極に短絡する第６半導体領域
の接合面近傍の寄生抵抗が低抵抗化されているため、タ
ーンオフ時におけてその接合が順バイアスされず、寄生
トランジスタがオンし難くなる。従って、ラッチアップ
を抑制できるので、可制御ターンオフ電流の大容量化を
図ることができる。In the case where an electrode portion which is conductively contacted is provided on the main surfaces of the third, fourth, fifth and sixth semiconductor regions, at least the junction surface between the region and the sixth semiconductor region in the third semiconductor region. When the first-conductivity-type high-concentration semiconductor region is formed in the vicinity, the parasitic resistance in the vicinity of the junction surface of the sixth semiconductor region short-circuited to the electrode is reduced. It is not biased and the parasitic transistor is hard to turn on. Therefore, since latch-up can be suppressed, the controllable turn-off current can be increased in capacity.

【００３７】 他方、第４，第５及び第６半導体領域
の主面にのみ導電接触する電極部を設けた場合におい
て、第３半導体領域内に第１導電型の高濃度埋め込み領
域が形成されているときには、第２ＭＩＳＦＥＴによる
キャリア引く抜き時の第３半導体領域の電流経路の経路
抵抗（拡散抵抗）が低抵抗であるため、第６半導体領域
の接合が順バイアスされず、寄生トランジスタがオンし
難くなる。従って、ラッチアップを抑制できるので、可
制御ターンオフ電流の大容量化を図ることができる。ま
た第３半導体領域内で、少なくとも当該領域と第６半導
体領域との接合面近傍に第１導電型の高濃度半導体領域
が形成されているときにも、同様の効果が発揮される。On the other hand, in the case where the electrode portions that are in conductive contact are provided only on the main surfaces of the fourth, fifth and sixth semiconductor regions, the first conductivity type high concentration buried region is formed in the third semiconductor region. When it is present, since the path resistance (diffusion resistance) of the current path of the third semiconductor region at the time of extracting carriers by the second MISFET is low, the junction of the sixth semiconductor region is not forward biased, and the parasitic transistor is hard to turn on. Become. Therefore, since latch-up can be suppressed, the controllable turn-off current can be increased in capacity. The same effect is also exhibited when the first-conductivity-type high-concentration semiconductor region is formed in the third semiconductor region at least in the vicinity of the junction surface between the region and the sixth semiconductor region.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例１に係る半導体装置の構造を示
す断面図である。FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the invention.

【図２】同半導体装置の等価回路を示す回路図である。FIG. 2 is a circuit diagram showing an equivalent circuit of the same semiconductor device.

【図３】（ａ）は同半導体装置のサイリスタ状態におけ
る電流の流れを示す断面図、（ｂ）は同半導体装置のト
ランジスタ状態における電流の流れを示す断面図であ
る。3A is a sectional view showing a current flow in the thyristor state of the semiconductor device, and FIG. 3B is a sectional view showing a current flow in a transistor state of the semiconductor device.

【図４】本発明の実施例２に係る半導体装置の構造を示
す断面図である。FIG. 4 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the invention.

【図５】本発明の実施例３に係る半導体装置の構造を示
す断面図である。FIG. 5 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the invention.

【図６】本発明の実施例４に係る半導体装置の構造を示
す断面図である。FIG. 6 is a sectional view showing a structure of a semiconductor device according to a fourth embodiment of the present invention.

【図７】同半導体装置の等価回路を示す回路図である。FIG. 7 is a circuit diagram showing an equivalent circuit of the same semiconductor device.

【図８】本発明の実施例５に係る半導体装置の構造を示
す断面図である。FIG. 8 is a sectional view showing a structure of a semiconductor device according to a fifth embodiment of the invention.

【図９】本発明の実施例６に係る半導体装置の構造を示
す断面図である。FIG. 9 is a sectional view showing a structure of a semiconductor device according to a sixth embodiment of the present invention.

【図１０】従来のＭＣＴの構造の一例を示す断面図であ
る。FIG. 10 is a sectional view showing an example of a structure of a conventional MCT.

【図１１】図１０に示すＭＣＴの等価回路を示す回路図
である。11 is a circuit diagram showing an equivalent circuit of the MCT shown in FIG.

【図１２】（ａ）は図１０に示すＭＣＴのサイリスタ状
態における電流の流れを示す断面図、（ｂ）は同半導体
装置のトランジスタ状態における電流の流れを示す断面
図である。12A is a sectional view showing a current flow in a thyristor state of the MCT shown in FIG. 10, and FIG. 12B is a sectional view showing a current flow in a transistor state of the semiconductor device.

【符号の説明】 １・・・アノード電極 ２・・・ｐ+ 型のアノード層 ３・・・ｎ+ 型のバッファ層 ４・・・ｎ- 型のベース層 ５・・・ｐ型のベース領域 ８・・・ゲート絶縁膜 １５・・・カソード電極 １５ａ，１５ｂ・・・電極部 １６・・・ｎ型のカソード領域 １７・・・ｐ+ 型のドレイン領域 １８・・・ｎ+ 型のソース領域 １９・・・第１のゲート電極 ２０・・・第２のゲート電極 ２１・・・第１のＭＯＳＦＥＴ ２２・・・第２のＭＯＳＦＥＴ ２３・・・第３のＭＯＳＦＥＴ ２５・・・ｐ+ 型の深いウェル ２６・・・ｐ+ 型の浅いウェル ２７・・・ｐ+ 型の埋め込み領域 ２８・・・ｐ+ 型の深いウェル Ｑpnp ・・・ｐｎｐ型バイポーラトランジスタ Ｑnpn ・・・ｎｐｎ型バイポーラトランジスタ Ｑ′npn ・・寄生ｎｐｎ型バイポーラトランジスタ ３０・・・ＭＣＴ部 ４０・・・ＩＧＢＴ部 Ｒ，ＲB,Ｒ′B ・・・拡散抵抗。[Description of Reference Signs] 1 ... Anode electrode 2 ... P + type anode layer 3 ... N + type buffer layer 4 ... N − type base layer 5 ... P type base region 8 ... Gate insulating film 15 ... Cathode electrode 15a, 15b ... Electrode part 16 ... N type cathode region 17 ... P + type drain region 18 ... N + type source region 19 ... 1st gate electrode 20 ... 2nd gate electrode 21 ... 1st MOSFET 22 ... 2nd MOSFET 23 ... 3rd MOSFET 25 ... p + type Deep well 26 ... p + shallow well 27 ... p + buried region 28 ... p + deep well Q pnp ... pnp bipolar transistor Q npn ... npn bipolar transistor Q 'npn ·· parasitic npn type bipolar tiger Register 30 · · · MCT unit 40 · · · IGBT unit R, R B, R 'B ··· diffusion resistance.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０３Ｋ 17/56 Ｃ 9184−5Ｊ 17/732 9383−5Ｊ Ｈ０３Ｋ 17/73 Ｂ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical indication location H03K 17/56 C 9184-5J 17/732 9383-5J H03K 17/73 B

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】 第１導電型の第１半導体領域，第２導電
型の第２半導体領域，第１導電型の第３半導体領域及び
第２導電型の第４半導体領域とからなるサイリスタ構造
と、第２導電型の第４半導体領域の主面側に形成された
第１導電型の第５半導体領域と、第１導電型の第３半導
体領域をバックゲートとし第２導電型の第４半導体領域
から第２導電型の第２半導体領域に対しその多数キャリ
アを注入可能の第１のＭＩＳＦＥＴと、第２導電型の第
４半導体領域をバックゲートとし第１導電型の第３半導
体領域から第１導電型の第５半導体領域に対しその多数
キャリアを引き抜き可能で第１のＭＩＳＦＥＴのゲート
電極を共用する第２のＭＩＳＦＥＴとを備えた半導体装
置であって、 第１導電型の第３半導体領域の主面側においてそれを残
して前記第２導電型の第４半導体領域とは隔離した部位
に形成された第２導電型の第６半導体領域と、第１導電
型の第３半導体領域をバックゲートとし第２導電型の第
６半導体領域から第２導電型の第２半導体領域に対しそ
の多数キャリアを注入可能で前記第１のＭＩＳＦＥＴと
は独立に開閉可能の第３のＭＩＳＦＥＴとを有すること
を特徴とする半導体装置。1. A thyristor structure comprising a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type and a fourth semiconductor region of a second conductivity type. A fifth semiconductor region of the first conductivity type formed on the main surface side of the fourth semiconductor region of the second conductivity type and a third semiconductor region of the first conductivity type as a back gate, and a fourth semiconductor of the second conductivity type. A first MISFET capable of injecting majority carriers from the region to the second conductivity type second semiconductor region, and a second conductivity type fourth semiconductor region serving as a back gate from the first conductivity type third semiconductor region What is claimed is: 1. A semiconductor device comprising: a first conductivity type fifth semiconductor region; a second MISFET capable of extracting majority carriers thereof and sharing a gate electrode of the first MISFET; and a first conductivity type third semiconductor region. Leaving it on the main surface side of The second conductive type sixth semiconductor region formed in a portion separated from the second conductive type fourth semiconductor region and the first conductive type third semiconductor region as a back gate are used as the second conductive type sixth semiconductor region. A semiconductor device comprising a third MISFET capable of injecting majority carriers from the semiconductor region to the second semiconductor region of the second conductivity type and capable of opening / closing independently of the first MISFET. 【請求項２】 請求項１に記載の半導体装置において、
第１導電型の第３半導体領域，第２導電型の第４半導体
領域，第１導電型の第５半導体領域及び第２導電型の第
６半導体領域の主面にすべて導電接触する電極部を有す
ることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein
Electrode portions that are all in conductive contact with the main surfaces of the third semiconductor region of the first conductivity type, the fourth semiconductor region of the second conductivity type, the fifth semiconductor region of the first conductivity type, and the sixth semiconductor region of the second conductivity type. A semiconductor device having. 【請求項３】 請求項２に記載の半導体装置において、
前記第１導電型の第３半導体領域内で、少なくとも当該
領域と前記第２導電型の第６半導体領域との接合面近傍
に形成された第１導電型の高濃度半導体領域を有するこ
とを特徴とする半導体装置。3. The semiconductor device according to claim 2,
In the third semiconductor region of the first conductivity type, at least a high-concentration semiconductor region of the first conductivity type is formed in the vicinity of a bonding surface between the region and the sixth semiconductor region of the second conductivity type. Semiconductor device. 【請求項４】 請求項３に記載の半導体装置において、
前記第１導電型の高濃度半導体領域は、前記第２導電型
の第４半導体領域の主面側境界にまで拡がり、前記第１
導電型の第３半導体領域の深さと同程度又はそれ以上の
深さのウェル領域であることを特徴とする半導体装置。4. The semiconductor device according to claim 3,
The first-conductivity-type high-concentration semiconductor region extends to the boundary of the second-conductivity-type fourth semiconductor region on the main surface side,
A semiconductor device having a well region having a depth equal to or greater than the depth of a conductive third semiconductor region. 【請求項５】 請求項３又は請求項４に記載の半導体装
置において、前記第１導電型の高濃度半導体領域は、前
記第２導電型の第４半導体領域の主面側境界にまで拡が
り、前記第１導電型の第３半導体領域よりも浅いウェル
領域であることを特徴とする半導体装置。5. The semiconductor device according to claim 3, wherein the first-conductivity-type high-concentration semiconductor region spreads to a boundary of the second-conductivity-type fourth semiconductor region on the main surface side, A semiconductor device, wherein the well region is shallower than the third semiconductor region of the first conductivity type. 【請求項６】 請求項１に記載の半導体装置において、
第２導電型の第４半導体領域，第１導電型の第５半導体
領域及び第２導電型の第６半導体領域の主面にのみ導電
接触する電極部を有することを特徴とする半導体装置。6. The semiconductor device according to claim 1,
A semiconductor device having an electrode portion which is conductively contacted only with the main surfaces of a second conductivity type fourth semiconductor region, a first conductivity type fifth semiconductor region, and a second conductivity type sixth semiconductor region. 【請求項７】 請求項６に記載の半導体装置において、
前記第１導電型の第３半導体領域内に形成された第１導
電型の高濃度埋め込み領域を有することを特徴とする半
導体装置。7. The semiconductor device according to claim 6,
A semiconductor device having a high-concentration buried region of a first conductivity type formed in the third semiconductor region of the first conductivity type. 【請求項８】 請求項６又は請求項７に記載の半導体装
置において、前記第１導電型の第３半導体領域内で、少
なくとも当該領域と前記第２導電型の第６半導体領域と
の接合面近傍に形成された第１導電型の高濃度半導体領
域を有することを特徴とする半導体装置。8. The semiconductor device according to claim 6, wherein a junction surface of at least the region and the sixth semiconductor region of the second conductivity type in the third semiconductor region of the first conductivity type. A semiconductor device having a first-conductivity-type high-concentration semiconductor region formed in the vicinity thereof. 【請求項９】 請求項８に記載の半導体装置において、
前記第１導電型の高濃度半導体領域は、前記第２導電型
の第４半導体領域の主面側境界にまで拡がり、前記第１
導電型の第３半導体領域の深さと同程度又はそれ以上の
深さのウェル領域であることを特徴とする半導体装置。9. The semiconductor device according to claim 8, wherein
The first-conductivity-type high-concentration semiconductor region extends to the boundary of the second-conductivity-type fourth semiconductor region on the main surface side,
A semiconductor device having a well region having a depth equal to or greater than the depth of a conductive third semiconductor region. 【請求項１０】 請求項８又は請求項９に記載の半導体
装置において、前記第１導電型の高濃度半導体領域は、
前記第２導電型の第４半導体領域の主面側境界にまで拡
がり、前記第１導電型の第３半導体領域よりも浅いウェ
ル領域であることを特徴とする半導体装置。10. The semiconductor device according to claim 8, wherein the high-concentration semiconductor region of the first conductivity type is
A semiconductor device, which is a well region that extends to a boundary of a main surface side of a fourth semiconductor region of the second conductivity type and is shallower than a third semiconductor region of the first conductivity type.
JP05178430A 1993-03-23 1993-07-20 Semiconductor device Expired - Fee Related JP3116667B2 (en)

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JP6227993 1993-03-23
JP5-62279 1993-03-23
JP05178430A JP3116667B2 (en) 1993-03-23 1993-07-20 Semiconductor device

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0718893A3 (en) * 1994-11-25 1999-07-14 Fuji Electric Co., Ltd. MOS controlled thyristor having two gates
WO1999056323A1 (en) * 1998-04-27 1999-11-04 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and process for manufacturing the same
DE102005038441A1 (en) * 2005-08-12 2007-02-22 Infineon Technologies Ag Field-effect semiconductor component, has bipolar transistor structure in transistor body with weakly and strongly doped zones

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0718893A3 (en) * 1994-11-25 1999-07-14 Fuji Electric Co., Ltd. MOS controlled thyristor having two gates
WO1999056323A1 (en) * 1998-04-27 1999-11-04 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and process for manufacturing the same
US6472693B1 (en) 1998-04-27 2002-10-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
DE102005038441A1 (en) * 2005-08-12 2007-02-22 Infineon Technologies Ag Field-effect semiconductor component, has bipolar transistor structure in transistor body with weakly and strongly doped zones
DE102005038441B4 (en) * 2005-08-12 2010-08-05 Infineon Technologies Ag Field effect semiconductor device and method for producing the same

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