JPH06324350A - Thin-film field effect transistor array - Google Patents
Thin-film field effect transistor arrayInfo
- Publication number
- JPH06324350A JPH06324350A JP11256893A JP11256893A JPH06324350A JP H06324350 A JPH06324350 A JP H06324350A JP 11256893 A JP11256893 A JP 11256893A JP 11256893 A JP11256893 A JP 11256893A JP H06324350 A JPH06324350 A JP H06324350A
- Authority
- JP
- Japan
- Prior art keywords
- signal line
- electrodes
- electrode
- line
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はマトリクス液晶表示素子
などに用いる薄膜電界効果型トランジスタアレイに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film field effect transistor array used in a matrix liquid crystal display device or the like.
【0002】[0002]
【従来の技術】ガラスなどの絶縁基板上にシリコン薄膜
を用いて薄膜トランジスタ(以下TFTと記す)を構成
する技術は、アクティブマトリクス液晶表示装置(以下
AMLCDと記す)を構成する中心的技術として重要で
ある。2. Description of the Related Art A technique for forming a thin film transistor (hereinafter referred to as TFT) using a silicon thin film on an insulating substrate such as glass is important as a central technique for forming an active matrix liquid crystal display device (hereinafter referred to as AMLCD). is there.
【0003】AMLCDは、一般的に走査線・信号線お
よびその交差点近傍に配した薄膜トランジスタに接続し
た画素電極を設けた構造のTFT基板と、透明電極を全
面に形成した対向基板との間に液晶を挟み込み、制御し
た画素電極と対向電極の間に電圧を印加することにより
液晶中の光の透過状態を制御する。The AMLCD generally has a liquid crystal between a TFT substrate having a structure in which a pixel electrode connected to a scanning line / signal line and a thin film transistor arranged in the vicinity of an intersection thereof is provided and a counter substrate having a transparent electrode formed on the entire surface. A voltage is applied between the pixel electrode and the counter electrode which are sandwiched between them to control the light transmission state in the liquid crystal.
【0004】このとき、同一走査線に接続した薄膜トラ
ンジスタにより制御する画素電極は、同一時刻に書き込
みを行なわせるためにこの書込電圧を供給する信号線は
走査線がオンするタイミングより少し手前で書込電圧に
設定されなければならない。At this time, the pixel electrode controlled by the thin film transistor connected to the same scanning line writes the signal line supplying this writing voltage in order to write at the same time, slightly before the timing when the scanning line is turned on. Must be set to working voltage.
【0005】液晶は直流を印加し続けると一般的に劣化
が起こる。このため、各画素電極の電位は対向電極電位
に対して正負交互に印加される。このとき、正に印加す
る場合と負に印加する場合とでトランジスタ動作が非対
称になるため完全に同一の電位が印加されることはな
い。この正負の切り替えを広い領域で行うと、この非対
称性が認識されフリッカとなり、表示の認識の妨げとな
る。The liquid crystal generally deteriorates when a direct current is continuously applied. For this reason, the potential of each pixel electrode is alternately applied to the potential of the counter electrode. At this time, since the transistor operation becomes asymmetric between the case of applying the positive voltage and the case of applying the negative voltage, the completely same potential is not applied. If this positive / negative switching is performed in a wide area, this asymmetry is recognized and flicker occurs, which hinders the recognition of the display.
【0006】これを防ぐために、隣合う画素電極に正負
逆の電圧を印加することが考えられているが、一般に画
素間のパリティの組合わせにより駆動方式がいくつかに
区分されている。同一信号線により制御する画素電極に
同一パリティで、隣合う信号線により制御する画素電極
に反対パリティで電位を印加する方法はドレインライン
反転法と呼ばれている。これに対して、同一走査線によ
り制御する画素電極に同一パリティで、隣合う走査線で
制御する画素電極に反転パリティで電圧を印加する方法
はゲートライン反転法と呼ばれる。また隣合う画素電極
を逆パリティで駆動する方法を画素反転法と呼ぶ。In order to prevent this, it has been considered to apply positive and negative voltages to adjacent pixel electrodes, but generally, the driving method is divided into several types depending on the combination of the parities between the pixels. A method of applying a potential to pixel electrodes controlled by the same signal line with the same parity and a potential applied to pixel electrodes controlled by adjacent signal lines with the opposite parity is called a drain line inversion method. On the other hand, a method of applying a voltage to pixel electrodes controlled by the same scanning line with the same parity and a pixel electrode controlled with adjacent scanning lines with the reversed parity is called a gate line inversion method. A method of driving adjacent pixel electrodes with reverse parity is called a pixel inversion method.
【0007】通常、信号線に印加する電圧は、1走査期
間中に外部からシリアルで転送される。ドレインライン
反転および画素反転で駆動するためには、高速で正負の
切り替えを行う駆動ICが必要になる。このため、通常
この方法は消費電圧・コストの面から余り用いられな
い。一般的に最も多く用いられているのはゲートライン
反転法である。Normally, the voltage applied to the signal line is serially transferred from the outside during one scanning period. In order to drive by drain line inversion and pixel inversion, a drive IC that switches positive and negative at high speed is required. Therefore, normally, this method is rarely used in terms of voltage consumption and cost. Generally, the gate line inversion method is most often used.
【0008】[0008]
【発明が解決しようとする課題】ゲートライン反転法を
用いる場合、同一走査線で制御する画素電極に同一パリ
ティの電位が供給され、次の走査線で制御する画素電極
には逆パリティの電位が供給される。この時、すべての
信号線は同一時刻で同時に正負が切り替わる。When the gate line inversion method is used, the pixel electrodes controlled by the same scan line are supplied with the same parity potential, and the pixel electrodes controlled by the next scan line are supplied with the opposite parity potential. Supplied. At this time, all the signal lines switch between positive and negative at the same time at the same time.
【0009】通常、スイッチング素子としては、そのプ
ロセスのコストと安定性の面から逆スタガード構造の薄
膜電界効果型トランジスタが選択されることが多い。こ
のTFTの場合、絶縁基板側からゲート電極・ゲート絶
縁膜・島状非晶質シリコン層・ソース/ドレイン電極が
配されている。この構造では通常、ゲート電極に接続す
る走査線が基板側に、ドレイン電極に接続する信号線が
上側に配される。Normally, as the switching element, a thin film field effect transistor having an inverted staggered structure is often selected from the viewpoint of the cost and stability of the process. In this TFT, a gate electrode, a gate insulating film, an island-shaped amorphous silicon layer, and source / drain electrodes are arranged from the insulating substrate side. In this structure, the scanning line connected to the gate electrode is usually arranged on the substrate side, and the signal line connected to the drain electrode is arranged on the upper side.
【0010】しかしながら、信号線が上に配された場
合、信号線はすべての領域で対向電極と容量的に結合す
る。この容量は配線幅を一定とした場合、配線長にほぼ
比例して増加する。対応電極の電位を安定に保つために
は、この容量に十分対応できるような対向電極のコンダ
クタンスが必要になる。しかし、画面サイズが拡大する
と周辺と中央部との距離が拡大し、対向電極のコンダク
タンスも小さくなっていく。However, when the signal line is arranged on the upper side, the signal line is capacitively coupled to the counter electrode in all regions. This capacitance increases almost in proportion to the wiring length when the wiring width is constant. In order to keep the potential of the corresponding electrode stable, it is necessary to have a conductance of the counter electrode that can sufficiently cope with this capacitance. However, as the screen size increases, the distance between the periphery and the central part increases, and the conductance of the counter electrode also decreases.
【0011】このような関係により、対向電極の電位を
一定にできなくなった場合、このふれ量は信号線の電位
の関係では異なってくるため、図4に示すように、ディ
スプレイ上の黒表示部11内にウインドウ白表示部12
を表示した場合、ウインドウ白表示部12の横の部分が
それ以外のところと輝度が異なるいわゆるクロストーク
現象発生部13が現れる〔例えば、1992年、エス・
アイ・ディー・インターナショナル・シンポジウム・ダ
イジェスト・オブ・テクニカル・ペーパーズ(1992
SID INTERNATIONAL SYMPOS
IUM DIGEST OF TECHNICAL P
APERS)第23巻、59〜62頁参照〕。Due to such a relationship, when the electric potential of the counter electrode cannot be made constant, the amount of vibration differs depending on the electric potential of the signal line. Therefore, as shown in FIG. 4, the black display portion on the display is shown. Window white display section 12 in 11
Is displayed, a so-called crosstalk phenomenon generating section 13 whose brightness is different from the other side of the window white display section 12 is displayed [for example, 1992, S.
ID International Symposium Digest of Technical Papers (1992)
SID INTERNATIONAL SYMPOS
IUM DIGEST OF TECHNICAL P
APERS) 23, pp. 59-62].
【0012】これを防ぐために、従来は対向電極のシー
ト抵抗を減ずる方法がとられていた。しかしながら、現
在のところ特性の安定した透明電極で低抵抗な材料は限
られており、これ以上大面積化した場合対向電極の電位
を一定に保つことが困難になる。In order to prevent this, conventionally, a method of reducing the sheet resistance of the counter electrode has been used. However, at present, transparent electrodes having stable characteristics and low resistance materials are limited, and it becomes difficult to keep the potential of the counter electrode constant when the area is further increased.
【0013】本発明の目的は、大面積においてAMLC
Dの表示性能を安定させるために、対向電極と信号線と
の間の結合容量を減じてクロストークを抑止した薄膜電
界効果型トランジスタアレイを提供することにある。An object of the present invention is to provide AMLC over a large area.
In order to stabilize the display performance of D, it is an object of the present invention to provide a thin film field effect transistor array in which the cross-talk is suppressed by reducing the coupling capacitance between the counter electrode and the signal line.
【0014】[0014]
【課題を解決するための手段】本発明の薄膜電界効果型
トランジスタアレイは、絶縁基板上に格子状に配置して
交差させた走査線および信号線と、前記走査線と信号線
の各交点の近傍の前記絶縁基板上に設け且つ前記走査線
に接続するゲート電極と、前記ゲート電極上にゲート絶
縁膜を介して設けた島状の半導体膜と、前記半導体膜上
に設けて前記信号線と接続するソース電極(又はドレイ
ン電極)および画素電極と接続するドレイン電極(又は
ソース電極)とを有する逆スタガード型薄膜電界効果ト
ランジスタアレイにおいて、前記信号線が前記ゲート電
極と同一層に形成され、前記走査線が前記ソース・ドレ
イン電極と同一層に形成されている。A thin film field effect transistor array according to the present invention comprises a scanning line and a signal line which are arranged in a lattice on an insulating substrate and intersect each other, and an intersection of the scanning line and the signal line. A gate electrode provided on the insulating substrate in the vicinity and connected to the scanning line, an island-shaped semiconductor film provided on the gate electrode via a gate insulating film, and the signal line provided on the semiconductor film. In an inverted staggered thin film field effect transistor array having a source electrode (or drain electrode) connected to it and a drain electrode (or source electrode) connected to a pixel electrode, the signal line is formed in the same layer as the gate electrode, Scan lines are formed in the same layer as the source / drain electrodes.
【0015】[0015]
【作用】対向電極の電位を安定化させるためには、同時
に変化する量が最も大きい信号線と対向電極との間の容
量結合を減ずることが必要である。信号線の面積は主と
して、信号線の遅延と接続の信頼性の問題からある値よ
り小さくすることはできない。信号線の面積を一定とし
たままで、結合容量を減ずるためには、信号線と対向電
極との間に電位の安定した電極を設けることが効果的で
ある。In order to stabilize the potential of the counter electrode, it is necessary to reduce the capacitive coupling between the signal line and the counter electrode, which changes the largest at the same time. The area of the signal line cannot be made smaller than a certain value mainly due to the delay of the signal line and the reliability of the connection. In order to reduce the coupling capacitance while keeping the area of the signal line constant, it is effective to provide an electrode having a stable potential between the signal line and the counter electrode.
【0016】信号線を基板側に配し走査線をこの上に配
することにより、信号線・走査線の交差部で信号線が走
査線で覆われることとなり、この分、対向電極と信号線
との容量結合が減ずる効果がある。By arranging the signal line on the substrate side and the scanning line on this, the signal line is covered with the scanning line at the intersection of the signal line and the scanning line. This has the effect of reducing capacitive coupling with.
【0017】この構造を実現するためには、信号線とゲ
ート電極を同一層で形成し、さらに走査線とソース/ド
レイン電極を同一層で形成し、信号線とドレイン電極お
よび走査線とゲート電極とをコンタクトホールを用いて
接続することにより、実現することができる。In order to realize this structure, the signal line and the gate electrode are formed in the same layer, the scanning line and the source / drain electrode are formed in the same layer, and the signal line and the drain electrode and the scanning line and the gate electrode are formed. This can be realized by connecting and using a contact hole.
【0018】[0018]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【0019】図1(a)は本発明の第1の実施例を示す
平面図、図1(b)は図1(a)のA−A′線断面図、
図1(c)は図1(a)のB−B′線断面図である。FIG. 1 (a) is a plan view showing a first embodiment of the present invention, FIG. 1 (b) is a sectional view taken along the line AA 'in FIG. 1 (a),
FIG. 1C is a sectional view taken along the line BB ′ of FIG.
【0020】図1(a)〜(c)に示すように、ガラス
板等の透光性絶縁基板7の上に走査線1と信号線2とを
交差させて格子状に配置し、これら走査線1と信号線2
の各交点近傍の絶縁基板7の上に設けたゲート電極4
と、ゲート電極4上に絶縁膜8を介して設けた島状の非
晶質シリコン膜10と、非晶質シリコン膜10を含む表
面に設けたソース電極9およびドレイン電極3とを有す
るTFTアレイを構成している。ここで、TFTのドレ
イン電極3をゲート電極4と同一層に設けた信号線2に
絶縁膜8に設けたコンタクトホール6を介して接続し、
ゲート電極4をソース電極9およびドレイン電極3と同
一層に設けた走査線1に接続し、ソース電極9を画素電
極5に接続してTFT基板を構成する。As shown in FIGS. 1 (a) to 1 (c), scanning lines 1 and signal lines 2 are arranged in a grid pattern on a translucent insulating substrate 7 such as a glass plate, and these scanning lines are arranged. Line 1 and signal line 2
Of the gate electrode 4 provided on the insulating substrate 7 near each intersection of
And a TFT array having an island-shaped amorphous silicon film 10 provided on the gate electrode 4 with an insulating film 8 interposed therebetween, and a source electrode 9 and a drain electrode 3 provided on the surface including the amorphous silicon film 10. Are configured. Here, the drain electrode 3 of the TFT is connected to the signal line 2 provided in the same layer as the gate electrode 4 through the contact hole 6 provided in the insulating film 8,
The gate electrode 4 is connected to the scanning line 1 provided in the same layer as the source electrode 9 and the drain electrode 3, and the source electrode 9 is connected to the pixel electrode 5 to form a TFT substrate.
【0021】図2(a)〜(c)は本発明の第1の実施
例の製造方法を説明するための工程順に示した平面図で
ある。2 (a) to 2 (c) are plan views showing the order of steps for explaining the manufacturing method of the first embodiment of the present invention.
【0022】まず、図2(a)に示すように、透光性の
絶縁基板の上にスパッタ法でクロム膜を150nmの厚
さに堆積してパターニングし、絶縁基板上に想定した仮
想格子線14上に信号線2と信号線2に沿って配置した
ゲート電極4とのそれぞれを形成する。次に、信号線2
およびゲート電極4を含む表面にゲート絶縁膜となる窒
化シリコン膜を400nmの厚さに堆積した後、厚さ3
50nmのノンドープ非晶質シリコン膜および厚さ50
nmのn型非晶質シリコン膜を順次堆積してパターニン
グし、ゲート電極4の上に島状の非晶質シリコン膜10
を形成する。First, as shown in FIG. 2A, a chromium film having a thickness of 150 nm is deposited on a translucent insulating substrate by a sputtering method and patterned, and an assumed virtual lattice line is formed on the insulating substrate. The signal line 2 and the gate electrode 4 arranged along the signal line 2 are formed on the signal line 14. Next, signal line 2
After depositing a silicon nitride film to be a gate insulating film to a thickness of 400 nm on the surface including the gate electrode 4 and a thickness of 3 nm.
50 nm non-doped amorphous silicon film and thickness 50
nm n-type amorphous silicon film is sequentially deposited and patterned to form an island-shaped amorphous silicon film 10 on the gate electrode 4.
To form.
【0023】次に、図2(b)に示すように、窒化シリ
コン膜を選択的にエッチングして信号線2およびゲート
電極4上にコンタクトホール6を形成した後、コンタク
トホール6を含む表面にクロム膜を堆積してパターニン
グし、コンタクトホール6を介して信号線2に接続する
ドレイン電極3およびソース電極9のそれぞれを形成す
る。次に、全面にアレミニウム膜を堆積してパターニン
グし走査線1のクロム膜と積層させ、2層構造の走査線
を形成する。Next, as shown in FIG. 2B, the silicon nitride film is selectively etched to form contact holes 6 on the signal lines 2 and the gate electrodes 4, and then on the surface including the contact holes 6. A chromium film is deposited and patterned to form each of the drain electrode 3 and the source electrode 9 connected to the signal line 2 through the contact hole 6. Next, an aluminium film is deposited on the entire surface, patterned, and laminated with the chromium film of the scanning line 1 to form a scanning line having a two-layer structure.
【0024】次に、図2(c)に示すように、ソース電
極9およびドレイン電極3をマスクとして非晶質シリコ
ン膜10のチャネル領域上のn型非晶質シリコン膜をプ
ラズマエッチングで除去し、ITO膜によりソース電極
9と接続する画素電極5を選択的に形成した後、プラズ
マCVD法によりパッシベーション膜として窒化シリコ
ン膜を堆積し、TFT基板を構成する。Next, as shown in FIG. 2C, the n-type amorphous silicon film on the channel region of the amorphous silicon film 10 is removed by plasma etching using the source electrode 9 and the drain electrode 3 as a mask. After selectively forming the pixel electrode 5 connected to the source electrode 9 with the ITO film, a silicon nitride film is deposited as a passivation film by the plasma CVD method to form a TFT substrate.
【0025】図3は本発明の第2の実施例を示す平面図
である。FIG. 3 is a plan view showing a second embodiment of the present invention.
【0026】図3に示すように、走査線1と信号線2と
の交差点から隣接するTFTの近傍までの信号線2の上
に走査線1を延在させて形成し、信号線1の上部の大半
を被覆した以外は第1の実施例と同様の構成を有してお
り、信号線2と対向電極との容量結合を更に低く抑える
ことができるという利点がある。As shown in FIG. 3, the scanning line 1 is formed by extending the scanning line 1 on the signal line 2 from the intersection of the scanning line 1 and the signal line 2 to the vicinity of the adjacent TFT. It has the same structure as that of the first embodiment except that most of it is covered, and has an advantage that the capacitive coupling between the signal line 2 and the counter electrode can be further suppressed.
【0027】[0027]
【発明の効果】本発明は、絶縁基板上に設けた信号線の
上に走査線を配置することにより、信号線と走査線との
交差部で信号線が走査線により覆われるため、対向電極
と信号線との容量結合を減ずることができ、クロストー
クを抑止できる。According to the present invention, by arranging the scanning lines on the signal lines provided on the insulating substrate, the signal lines are covered with the scanning lines at the intersections of the signal lines, so that the counter electrode is provided. The capacitive coupling between the signal line and the signal line can be reduced, and crosstalk can be suppressed.
【図1】本発明の第1の実施例を示す平面図およびA−
A′線断面図並びにB−B′線断面図。FIG. 1 is a plan view and A- showing a first embodiment of the present invention.
A sectional view taken along the line A ′ and a sectional view taken along the line BB ′.
【図2】本発明の第1の実施例の製造方法を説明するた
めの工程順に示した平面図。2A to 2D are plan views showing the order of steps for explaining the manufacturing method according to the first embodiment of the present invention.
【図3】本発明の第2の実施例を示す平面図。FIG. 3 is a plan view showing a second embodiment of the present invention.
【図4】従来の薄膜電界効果型トランジスタアレイを使
用した液晶表示装置の課題を説明するための模式図。FIG. 4 is a schematic diagram for explaining a problem of a liquid crystal display device using a conventional thin film field effect transistor array.
1 走査線 2 信号線 3 ドレイン電極 4 ゲート電極 5 画素電極 6 コンタクトホール 7 絶縁基板 8 絶縁膜 9 ソース電極 10 非晶質シリコン膜 11 黒表示部 12 白ウインドウ表示部 13 クロストーク現象発生部 14 仮想格子線 1 Scan Line 2 Signal Line 3 Drain Electrode 4 Gate Electrode 5 Pixel Electrode 6 Contact Hole 7 Insulating Substrate 8 Insulating Film 9 Source Electrode 10 Amorphous Silicon Film 11 Black Display 12 White Window Display 13 Crosstalk Phenomenon 14 Virtual Grid line
Claims (2)
た走査線および信号線と、前記走査線と信号線の各交点
の近傍の前記絶縁基板上に設け且つ前記走査線に接続す
るゲート電極と、前記ゲート電極上にゲート絶縁膜を介
して設けた島状の半導体膜と、前記半導体膜上に設けて
前記信号線と接続するソース電極(又はドレイン電極)
および画素電極と接続するドレイン電極(又はソース電
極)とを有する逆スタガード型薄膜電界効果トランジス
タアレイにおいて、前記信号線が前記ゲート電極と同一
層に形成され、前記走査線が前記ソース・ドレイン電極
と同一層に形成されたことを特徴とする薄膜電界効果型
トランジスタアレイ。1. A scanning line and a signal line which are arranged and crossed in a grid pattern on an insulating substrate, and are provided on the insulating substrate in the vicinity of intersections of the scanning line and the signal line and are connected to the scanning line. A gate electrode, an island-shaped semiconductor film provided on the gate electrode via a gate insulating film, and a source electrode (or drain electrode) provided on the semiconductor film and connected to the signal line
And a drain electrode (or source electrode) connected to the pixel electrode, the signal line is formed in the same layer as the gate electrode, and the scanning line is formed as the source / drain electrode. A thin film field effect transistor array, which is formed in the same layer.
延在して薄膜電界効果トランジスタ近傍以外の信号線上
を被覆して形成された請求項1記載の薄膜電界効果型ト
ランジスタアレイ。2. The thin film field effect transistor array according to claim 1, wherein the scanning line extends from the intersection of the scanning line and the signal line and covers the signal line other than the vicinity of the thin film field effect transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11256893A JP2556252B2 (en) | 1993-05-14 | 1993-05-14 | Thin film field effect transistor array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11256893A JP2556252B2 (en) | 1993-05-14 | 1993-05-14 | Thin film field effect transistor array |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06324350A true JPH06324350A (en) | 1994-11-25 |
JP2556252B2 JP2556252B2 (en) | 1996-11-20 |
Family
ID=14589965
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11256893A Expired - Lifetime JP2556252B2 (en) | 1993-05-14 | 1993-05-14 | Thin film field effect transistor array |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2556252B2 (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09203886A (en) * | 1996-01-25 | 1997-08-05 | Toshiba Corp | Active matrix liquid crystal panel |
JPH10333181A (en) * | 1997-05-30 | 1998-12-18 | Nec Corp | Active matrix type liquid crystal display device and its manufacture |
JPH112844A (en) * | 1997-06-13 | 1999-01-06 | Nec Corp | Liquid crystal display panel and its manufacture |
JP2002014628A (en) * | 2000-04-27 | 2002-01-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacturing method |
JP2002082630A (en) * | 2000-05-12 | 2002-03-22 | Semiconductor Energy Lab Co Ltd | Electro-optic device |
JP2007249211A (en) * | 2006-03-15 | 2007-09-27 | Samsung Electronics Co Ltd | Display device and manufacturing method therefor |
JP2011141552A (en) * | 2000-02-22 | 2011-07-21 | Semiconductor Energy Lab Co Ltd | Display device |
JP2011197681A (en) * | 2000-04-27 | 2011-10-06 | Semiconductor Energy Lab Co Ltd | El display |
US8188948B2 (en) | 2007-11-09 | 2012-05-29 | Samsung Electronics Co., Ltd. | Organic light emitting diode display and method for manufacturing the same |
US9281343B2 (en) | 2012-02-07 | 2016-03-08 | Samsung Display Co., Ltd. | Thin film transistor display panel and method of manufacturing the same |
WO2016195000A1 (en) * | 2015-06-04 | 2016-12-08 | シャープ株式会社 | Photosensor substrate |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW478014B (en) | 1999-08-31 | 2002-03-01 | Semiconductor Energy Lab | Semiconductor device and method of manufacturing thereof |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0451120A (en) * | 1990-06-19 | 1992-02-19 | Nec Corp | Liquid crystal display element array driven by thin-film electric field effect type transistor |
-
1993
- 1993-05-14 JP JP11256893A patent/JP2556252B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0451120A (en) * | 1990-06-19 | 1992-02-19 | Nec Corp | Liquid crystal display element array driven by thin-film electric field effect type transistor |
Cited By (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09203886A (en) * | 1996-01-25 | 1997-08-05 | Toshiba Corp | Active matrix liquid crystal panel |
JPH10333181A (en) * | 1997-05-30 | 1998-12-18 | Nec Corp | Active matrix type liquid crystal display device and its manufacture |
JPH112844A (en) * | 1997-06-13 | 1999-01-06 | Nec Corp | Liquid crystal display panel and its manufacture |
JP2012185504A (en) * | 2000-02-22 | 2012-09-27 | Semiconductor Energy Lab Co Ltd | Display device and electronic apparatus |
JP2019197232A (en) * | 2000-02-22 | 2019-11-14 | 株式会社半導体エネルギー研究所 | Liquid crystal display device |
US9869907B2 (en) | 2000-02-22 | 2018-01-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP2011141552A (en) * | 2000-02-22 | 2011-07-21 | Semiconductor Energy Lab Co Ltd | Display device |
US9318610B2 (en) | 2000-02-22 | 2016-04-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP2013101352A (en) * | 2000-02-22 | 2013-05-23 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device, display module and electronic apparatus |
US9419026B2 (en) | 2000-04-27 | 2016-08-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
JP2012073625A (en) * | 2000-04-27 | 2012-04-12 | Semiconductor Energy Lab Co Ltd | El display device |
JP2012103727A (en) * | 2000-04-27 | 2012-05-31 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
JP2012133376A (en) * | 2000-04-27 | 2012-07-12 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
US8178880B2 (en) | 2000-04-27 | 2012-05-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
JP2002014628A (en) * | 2000-04-27 | 2002-01-18 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacturing method |
JP2012234207A (en) * | 2000-04-27 | 2012-11-29 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device and electronic device |
JP2017049592A (en) * | 2000-04-27 | 2017-03-09 | 株式会社半導体エネルギー研究所 | Display |
JP2015046629A (en) * | 2000-04-27 | 2015-03-12 | 株式会社半導体エネルギー研究所 | Semiconductor device |
US9099361B2 (en) | 2000-04-27 | 2015-08-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
US9780124B2 (en) | 2000-04-27 | 2017-10-03 | Semiconductor Energy Laboratory Co., Ltd. | Display device including pixel comprising first transistor second transistor and light-emitting element |
JP2011197681A (en) * | 2000-04-27 | 2011-10-06 | Semiconductor Energy Lab Co Ltd | El display |
JP2002082630A (en) * | 2000-05-12 | 2002-03-22 | Semiconductor Energy Lab Co Ltd | Electro-optic device |
JP2007249211A (en) * | 2006-03-15 | 2007-09-27 | Samsung Electronics Co Ltd | Display device and manufacturing method therefor |
US8305311B2 (en) | 2007-11-09 | 2012-11-06 | Samsung Display Co., Ltd. | Organic light emitting diode display and method for manufacturing the same |
US8188948B2 (en) | 2007-11-09 | 2012-05-29 | Samsung Electronics Co., Ltd. | Organic light emitting diode display and method for manufacturing the same |
US9281343B2 (en) | 2012-02-07 | 2016-03-08 | Samsung Display Co., Ltd. | Thin film transistor display panel and method of manufacturing the same |
WO2016195000A1 (en) * | 2015-06-04 | 2016-12-08 | シャープ株式会社 | Photosensor substrate |
US10276611B2 (en) | 2015-06-04 | 2019-04-30 | Sharp Kabushiki Kaisha | Photosensor substrate |
Also Published As
Publication number | Publication date |
---|---|
JP2556252B2 (en) | 1996-11-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2776376B2 (en) | Active matrix liquid crystal display panel | |
JP2616160B2 (en) | Thin film field effect transistor element array | |
US7626646B2 (en) | Substrate for display device and display device equipped therewith | |
JP4241238B2 (en) | Liquid crystal display | |
KR19980027501A (en) | Liquid crystal display device and manufacturing method | |
JPH0814669B2 (en) | Matrix type display device | |
JPH1010548A (en) | Active matrix substrate and its production | |
KR960011495A (en) | Thin film transistor type liquid crystal display device and manufacturing method thereof | |
JP3226836B2 (en) | Liquid crystal display device and manufacturing method thereof | |
JP2556252B2 (en) | Thin film field effect transistor array | |
JPH02830A (en) | Thin film transistor and liquid crystal display device formed by using said transistor | |
JP2735070B2 (en) | Active matrix liquid crystal display panel | |
JPH05142570A (en) | Active matrix substrate | |
JPH0728089A (en) | Liquid crystal display panel | |
KR20020009144A (en) | liquid crystal display device | |
JP3145931B2 (en) | Thin film transistor | |
JPH11177094A (en) | Semiconductor thin film transistor and semiconductor thin film transistor array substrate including semiconductor thin film transistor | |
KR100281861B1 (en) | Sequential staggered type thin film transistor | |
JPH09127556A (en) | Display device and its drive method | |
JPH10293324A (en) | Liquid crystal display element | |
JP3049022B2 (en) | Liquid crystal display | |
JP4297574B2 (en) | Liquid crystal display | |
JPS62247569A (en) | Semiconductor device | |
JP4468626B2 (en) | Display device substrate and display device including the same | |
JP2947299B2 (en) | Matrix display device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19960716 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080905 Year of fee payment: 12 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080905 Year of fee payment: 12 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090905 Year of fee payment: 13 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090905 Year of fee payment: 13 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100905 Year of fee payment: 14 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110905 Year of fee payment: 15 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120905 Year of fee payment: 16 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130905 Year of fee payment: 17 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130905 Year of fee payment: 17 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130905 Year of fee payment: 17 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
EXPY | Cancellation because of completion of term |