JPH0629471A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0629471A JPH0629471A JP4179518A JP17951892A JPH0629471A JP H0629471 A JPH0629471 A JP H0629471A JP 4179518 A JP4179518 A JP 4179518A JP 17951892 A JP17951892 A JP 17951892A JP H0629471 A JPH0629471 A JP H0629471A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- electrode
- insulating film
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
保護抵抗を有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a protective resistance.
【０００２】[0002]
【従来の技術】半導体装置では、入出力端子に印加され
た静電気により、ゲート酸化膜や層間絶縁膜の絶縁破壊
を生じ、動作不良に至ることがあり、この対策として、
入力端子に保護抵抗，ダイオードを接続して設け、静電
気による破壊耐量を向上させる方法が採用されている。2. Description of the Related Art In a semiconductor device, static electricity applied to an input / output terminal may cause dielectric breakdown of a gate oxide film or an interlayer insulating film, resulting in malfunction.
A protection resistor and a diode are connected to the input terminal to provide resistance to destruction by static electricity.
【０００３】図５は保護抵抗とダイオードを用いた入力
保護回路の一例を示す回路図である。FIG. 5 is a circuit diagram showing an example of an input protection circuit using a protection resistor and a diode.
【０００４】図５に示すように、内部トランジスタ１３
のゲートを保護する目的で外部リード端子９と直列に多
結晶シリコン膜による保護抵抗１０を設け、さらに、電
源（Ｖcc）ライン及びグランドラインに対し各１個の保
護ダイオード１１，１２を介して接続している。As shown in FIG. 5, the internal transistor 13
A protection resistor 10 made of a polycrystalline silicon film is provided in series with the external lead terminal 9 for the purpose of protecting the gate of the device, and is connected to the power supply (Vcc) line and the ground line through one protection diode 11 and 12 respectively. is doing.
【０００５】この入力保護回路は、ＭＩＬ規格，ＥＩＡ
Ｊ規格といったコンデンサー放電による静電気印加試験
に対しては、有効な破壊耐量向上策となるが、近年注目
される様になってきたモールド樹脂封止型半導体装置の
モールド樹脂自体に生ずる帯電による静電気破壊現象に
対しては、必ずしも有効とは言えないことがある。This input protection circuit is based on the MIL standard, EIA.
Although it is an effective measure to improve the breakdown resistance against the static electricity applied test by the capacitor discharge such as J standard, the electrostatic breakdown due to the electrification generated in the mold resin itself of the mold resin-encapsulated semiconductor device has been attracting attention in recent years. It may not always be effective for the phenomenon.
【０００６】図３は従来の半導体装置の一例を示す半導
体チップの断面図である。FIG. 3 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor device.
【０００７】図３に示すように、シリコン基板１の上に
設けたフィールド酸化膜２の上に保護抵抗として多結晶
シリコン膜３を選択的に形成し、多結晶シリコン膜３を
含む表面に層間絶縁膜４を堆積してコンタクト孔７を形
成する。次に、コンタクト孔７を含む表面にアルミニウ
ム膜を堆積してパターニングし、コンタクト孔７の多結
晶シリコン膜３と接続する電極５を形成する。次に、電
極５にボンディング線６を接続する。As shown in FIG. 3, a polycrystalline silicon film 3 is selectively formed as a protective resistance on a field oxide film 2 provided on a silicon substrate 1, and an interlayer is formed on the surface including the polycrystalline silicon film 3. The insulating film 4 is deposited to form the contact hole 7. Next, an aluminum film is deposited on the surface including the contact holes 7 and patterned to form an electrode 5 connected to the polycrystalline silicon film 3 in the contact hole 7. Next, the bonding wire 6 is connected to the electrode 5.
【０００８】[0008]
【発明が解決しようとする課題】この従来の半導体装置
では、図４に示すように、モールド樹脂１５の表面部分
が正に帯電した場合、この半導体装置の外部リード端子
が接地されると半導体装置内部の容量に対し電圧が加わ
る。半導体装置内部の容量としては帯電したモールド樹
脂１４の表面部分を１つの電極とし、アイランド１５と
の間に存在する容量（パッケージ容量：ＣPKG ）及びシ
リコン基板１と、入力端子アルミ電極５との間に存在す
る容量（酸化膜容量：ＣOX）が問題となる。In this conventional semiconductor device, as shown in FIG. 4, when the surface portion of the mold resin 15 is positively charged, the semiconductor device is grounded if the external lead terminals are grounded. A voltage is applied to the internal capacitance. As the internal capacitance of the semiconductor device, the surface portion of the charged mold resin 14 is used as one electrode, and the capacitance (package capacitance: CPKG ) existing between the electrode 15 and the island 15 and the silicon substrate 1 and the input terminal aluminum electrode 5 are provided. The capacity (oxide film capacity: C OX ) existing between them poses a problem.
【０００９】外部リード端子が接地されると、モールド
樹脂１４の表面部分の帯電電圧に応じた電圧が、前記パ
ッケージ容量と、酸化膜容量に分担されて印加される。
このとき酸化膜容量に加わる電圧がフィールド熱酸化膜
２の絶縁耐圧を越えると絶縁破壊を生じる。そのときの
破壊箇所としては、図３中に×印で示す部分（電界強度
の高くなる多結晶シリコン膜の端部）がほとんどであ
る。このモールド樹脂帯電モードの静電気破壊では、電
圧の立上りが非常に急峻であるため、入力保護抵抗であ
る多結晶シリコン膜３以降はＣＲ部分定数回路と見なさ
れ、追従できず十分な効果を発揮できないためと考えら
れる。入力保護抵抗値を下げることで、保護回路の効果
を上げることは可能となるが、他のコンデンサー放電に
よる静電気印加試験（ＭＩＬ規格，ＥＩＡＪ規格）での
耐量確保が困難となるという問題がある。When the external lead terminal is grounded, a voltage corresponding to the charging voltage of the surface portion of the mold resin 14 is applied by being shared by the package capacitance and the oxide film capacitance.
At this time, if the voltage applied to the oxide film capacitance exceeds the breakdown voltage of the field thermal oxide film 2, dielectric breakdown occurs. Most of the destruction points at that time are the portions indicated by x in FIG. 3 (the end portions of the polycrystalline silicon film where the electric field strength is high). In this electrostatic breakdown of the mold resin charging mode, since the voltage rises very sharply, the polycrystalline silicon film 3 and the input protection resistors are regarded as a CR partial constant circuit and cannot follow up and cannot exert a sufficient effect. It is thought to be because. Although it is possible to improve the effect of the protection circuit by lowering the input protection resistance value, there is a problem that it becomes difficult to secure the withstand capacity in the static electricity application test (MIL standard, EIAJ standard) by other capacitor discharge.
【００１０】このモードの不良は半導体装置の外部リー
ド端子が接地した場合以外でも、接地されていない抵抗
の低い導体例えば金属に接した際にも生ずる。This mode failure occurs not only when the external lead terminal of the semiconductor device is grounded but also when it is contacted with a conductor having a low resistance, such as a metal, which is not grounded.
【００１１】[0011]
【課題を解決するための手段】本発明の半導体装置は入
力端子とボンディング線で接続される金属電極下層の絶
縁膜膜厚を部分的に薄くするか又は金属電極に接続され
た抵抗体膜を金属電極下層まで拡大・延長して設けた上
で金属電極と電気的に接続する構造を備えている。In a semiconductor device of the present invention, a film thickness of an insulating film under a metal electrode connected to an input terminal by a bonding wire is partially reduced or a resistor film connected to the metal electrode is formed. The structure is such that it is extended and extended to the lower layer of the metal electrode and then electrically connected to the metal electrode.
【００１２】[0012]
【実施例】次に、本発明について、図面を参照して説明
する。Next, the present invention will be described with reference to the drawings.
【００１３】図１は本発明の第１の実施例を示す半導体
チップの断面図である。FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.
【００１４】図１に示すように、シリコン基板１の表面
を熱酸化してフィールド酸化膜２を形成する。次に、フ
ィールド酸化膜２の上に多結晶シリコン膜３を堆積した
後フォトリソグラフィ技術を用いてパターニングし、保
護抵抗を形成する。次に、多結晶シリコン膜３を含む表
面に層間絶縁膜４としてリンガラス膜等を堆積し、フォ
トリソグラフィ技術により多結晶シリコン膜３上のコン
タクト孔７及びボンディング領域部の窓８を設ける。次
に、コンタクト孔７及び窓８を含む表面にアルミニウム
膜をスパッタ法などにより堆積し、フォトリソグラフィ
技術によりパターニングして電極５を形成し、電極５に
ボンディング線６をボンディングして接続する。As shown in FIG. 1, the surface of the silicon substrate 1 is thermally oxidized to form a field oxide film 2. Then, a polycrystalline silicon film 3 is deposited on the field oxide film 2 and then patterned by using a photolithography technique to form a protective resistor. Next, a phosphorus glass film or the like is deposited as an interlayer insulating film 4 on the surface including the polycrystalline silicon film 3, and a contact hole 7 on the polycrystalline silicon film 3 and a window 8 in the bonding region portion are provided by the photolithography technique. Next, an aluminum film is deposited on the surface including the contact hole 7 and the window 8 by a sputtering method or the like, patterned by a photolithography technique to form an electrode 5, and a bonding wire 6 is bonded to the electrode 5 for connection.
【００１５】この実施例では、ボンディング領域部分の
層間絶縁膜７の一部に窓８を設けることでシリコン基板
１と電極５との間に存在する酸化膜容量（ＣOX）１６を
増大させている。In this embodiment, the window 8 is provided in a part of the interlayer insulating film 7 in the bonding region to increase the oxide film capacitance (C OX ) 16 existing between the silicon substrate 1 and the electrode 5. There is.
【００１６】例として、ボンディングパッド部のアルミ
電極寸法が８０μｍ×８０μｍ，層間絶縁膜厚０．５μ
ｍ，フィールド酸化膜厚０．６μｍの半導体装置では従
来構造と比較して酸化膜容量ＣOXの増加は約６０％とな
る。As an example, the aluminum electrode size of the bonding pad portion is 80 μm × 80 μm, the interlayer insulating film thickness is 0.5 μm.
In a semiconductor device having a m and field oxide film thickness of 0.6 μm, the oxide film capacitance C OX is increased by about 60% as compared with the conventional structure.
【００１７】図２は本発明の第２の実施例を示す半導体
チップの断面図である。FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.
【００１８】図２に示すように、第１の実施例と同様
に、シリコン基板１上にフィールド酸化膜２を形成し、
次に、多結晶シリコン膜３を堆積する。この多結晶シリ
コン膜３をフォトリソグラフィ技術により、パターニン
グする際保護抵抗部と連続してボンディング領域に多結
晶シリコン膜３を残しておく。次に、多結晶シリコン膜
３を含む表面に設けた層間絶縁膜４のパターニング時に
ボンディング領域の窓と共通のコンタクト孔７ａを設け
る。As shown in FIG. 2, as in the first embodiment, a field oxide film 2 is formed on a silicon substrate 1,
Next, the polycrystalline silicon film 3 is deposited. When this polycrystalline silicon film 3 is patterned by the photolithography technique, the polycrystalline silicon film 3 is left in the bonding region continuously with the protective resistance portion. Next, when patterning the interlayer insulating film 4 provided on the surface including the polycrystalline silicon film 3, a contact hole 7a common to the window of the bonding region is provided.
【００１９】この第２の実施例における酸化膜容量ＣOX
の増加は第１の実施例と同じ条件下で、従来構造と比較
して約２倍を得ることができる。Oxide film capacitance C OX in the second embodiment
Under the same conditions as in the first embodiment, it is possible to obtain about twice as much as the conventional structure.
【００２０】一方、本発明の構造を用いる場合、金属電
極ボンディング領域の下層を利用するため、チップ面積
拡大等のデメリットは生じない。On the other hand, when the structure of the present invention is used, since the lower layer of the metal electrode bonding region is used, there is no demerit such as an increase in chip area.
【００２１】[0021]
【発明の効果】以上説明したように本発明は、ボンディ
ング領域部分の酸化膜容量を増加させることにより、モ
ールド樹脂帯電モードの静電気破壊耐量を向上すること
ができる。具体的には、シリコン基板と、多結晶シリコ
ン膜間に加わる電圧が次式で表わされることから電圧の
低下効果と同時に電圧立上りの時定数が大きくなるため
に設けられた保護抵抗、ダイオードによる効果が得られ
るためである。As described above, the present invention can improve the electrostatic breakdown resistance in the mold resin charging mode by increasing the oxide film capacitance in the bonding region. Specifically, since the voltage applied between the silicon substrate and the polycrystalline silicon film is expressed by the following equation, the effect of the protective resistance and the diode provided because the time constant of the voltage rise becomes large at the same time as the voltage decreasing effect increases. Is obtained.
【００２２】 [0022]
【００２３】第２の実施例に述べた構造をパッケージ容
量数ｐＦ程度の半導体装置に適用する検討を行ったとこ
ろ表１の結果を得た。When the structure described in the second embodiment was applied to a semiconductor device having a package capacitance of several pF, the results shown in Table 1 were obtained.
【００２４】[0024]
【表１】 [Table 1]
【図１】本発明の第１の実施例を示す半導体チップの断
面図。FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す半導体チップの断
面図。FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.
【図３】従来の半導体装置の一例を示す断面図。FIG. 3 is a sectional view showing an example of a conventional semiconductor device.
【図４】従来の半導体装置の静電破壊現象を説明するた
めの半導体チップの断面図。FIG. 4 is a sectional view of a semiconductor chip for explaining an electrostatic breakdown phenomenon of a conventional semiconductor device.
【図５】入力保護回路の一例を示す回路図。FIG. 5 is a circuit diagram showing an example of an input protection circuit.
１ シリコン基板 ２ フィールド酸化膜 ３ 多結晶シリコン膜 ４ 層間絶縁膜 ５ 電極 ６ ボンディング線 ７，７ａ コンタクト孔 ８ 窓 ９ 外部リード端子 １０ 保護抵抗 １１，１２ 保護ダイオード １３ 内部回路トランジスタ １４ モールド樹脂 １５ アイランド １６ 酸化膜容量（ＣOX） １７ パッケージ容量（ＣPKG ）1 Silicon Substrate 2 Field Oxide Film 3 Polycrystalline Silicon Film 4 Interlayer Insulation Film 5 Electrode 6 Bonding Wire 7, 7a Contact Hole 8 Window 9 External Lead Terminal 10 Protection Resistor 11, 12 Protection Diode 13 Internal Circuit Transistor 14 Mold Resin 15 Island 16 Oxide film capacity (C OX ) 17 Package capacity (C PKG )
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/784 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 29/784
Claims (1)
と、前記フィールド絶縁膜上に設けた抵抗体膜と、前記
抵抗体膜を含む表面に設けた層間絶縁膜と、前記抵抗体
膜上の前記層間絶縁膜に設けたコンタクト孔と、前記抵
抗体膜以外の領域の前記層間絶縁膜に設けた窓と、前記
コンタクト孔及び窓を含む表面に設けて前記抵抗体膜と
接続し且つ入力端子と電気的に接続した金属電極とを備
えたことを特徴とする半導体装置。1. A field insulating film provided on a semiconductor substrate, a resistor film provided on the field insulating film, an interlayer insulating film provided on a surface including the resistor film, and a resistor film on the resistor film. A contact hole provided in the interlayer insulating film, a window provided in the interlayer insulating film in a region other than the resistor film, a surface provided with the contact hole and the window, connected to the resistor film, and an input terminal. And a metal electrode electrically connected to the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4179518A JP2914015B2 (en) | 1992-07-07 | 1992-07-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4179518A JP2914015B2 (en) | 1992-07-07 | 1992-07-07 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0629471A true JPH0629471A (en) | 1994-02-04 |
| JP2914015B2 JP2914015B2 (en) | 1999-06-28 |
Family
ID=16067188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4179518A Expired - Fee Related JP2914015B2 (en) | 1992-07-07 | 1992-07-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2914015B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5696406A (en) * | 1993-10-29 | 1997-12-09 | Nec Corportion | Semiconductor device and method for fabricating the same |
| JP2007134588A (en) * | 2005-11-11 | 2007-05-31 | Sanken Electric Co Ltd | Semiconductor device |
| JP2007250760A (en) * | 2006-03-15 | 2007-09-27 | Nec Electronics Corp | Semiconductor device |
| US7622792B2 (en) | 2005-12-08 | 2009-11-24 | Panasonic Corporation | Semiconductor device and method of manufacturing the same |
-
1992
- 1992-07-07 JP JP4179518A patent/JP2914015B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5696406A (en) * | 1993-10-29 | 1997-12-09 | Nec Corportion | Semiconductor device and method for fabricating the same |
| JP2007134588A (en) * | 2005-11-11 | 2007-05-31 | Sanken Electric Co Ltd | Semiconductor device |
| US7622792B2 (en) | 2005-12-08 | 2009-11-24 | Panasonic Corporation | Semiconductor device and method of manufacturing the same |
| JP2007250760A (en) * | 2006-03-15 | 2007-09-27 | Nec Electronics Corp | Semiconductor device |
| US8283753B2 (en) | 2006-03-15 | 2012-10-09 | Renesas Electronics Corporation | Semiconductor device |
| US8575721B2 (en) | 2006-03-15 | 2013-11-05 | Renesas Electronics Corporation | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2914015B2 (en) | 1999-06-28 |
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