JPH0629134A - Thin-film transformer for high-frequency switching power supply - Google Patents
Thin-film transformer for high-frequency switching power supplyInfo
- Publication number
- JPH0629134A JPH0629134A JP4180181A JP18018192A JPH0629134A JP H0629134 A JPH0629134 A JP H0629134A JP 4180181 A JP4180181 A JP 4180181A JP 18018192 A JP18018192 A JP 18018192A JP H0629134 A JPH0629134 A JP H0629134A
- Authority
- JP
- Japan
- Prior art keywords
- thin
- substrate
- film transformer
- transformer
- thin film
- Prior art date
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- Semiconductor Integrated Circuits (AREA)
- Dc-Dc Converters (AREA)
- Coils Or Transformers For Communication (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、コンバータやスイッチ
ング電源等に好適で、導電性パターンにより小形に構成
された高周波特性に優れる高周波スイッチング電源用薄
膜トランスに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transformer for a high frequency switching power source, which is suitable for a converter, a switching power source and the like, and which has a small size by a conductive pattern and has excellent high frequency characteristics.
【０００２】[0002]
【従来の技術】近年、電子機器構成部品の小形化・軽量
化の要請は厳しく、高品質な電力が得られるスイッチン
グ電源等においても小形化は必須の課題であり、スイッ
チング周波数の高周波化により、トランス，コンデンサ
等の部品を小さくすることで小形化が進められてきた。
半導体部品やコンデンサ部品では、ＬＳＩや積層セラミ
ックコンデンサに代表されるように、早くから薄膜技術
が用いられ、構成部品小形化の要請に十分応えてきた。
一方、トランス等の磁性部品はこれまでに最も小形化し
にくく、また高周波化に伴う損失増加を抑えることが難
しいため、電源の小形化を妨げる第一の原因であった。
このため、現在、高周波スイッチング電源の体積は、磁
性部品の体積によって決定されると言っても過言ではな
い。そこで近年、高周波化に対応すべく薄膜形成技術を
用いた薄膜トランスの研究が進められ、スイッチング周
波数をＭＨｚ帯域まで高めた小形電源の開発が強く望ま
れるようになった。2. Description of the Related Art In recent years, demands for downsizing and weight reduction of electronic equipment components are strict, and downsizing is an essential issue even in switching power supplies and the like that can obtain high-quality power. Miniaturization has been promoted by making parts such as transformers and capacitors smaller.
In semiconductor components and capacitor components, thin film technology has been used for a long time, as represented by LSI and multilayer ceramic capacitors, and has sufficiently met the demand for miniaturization of component parts.
On the other hand, magnetic parts such as transformers have been the most difficult to miniaturize until now, and it has been difficult to suppress an increase in loss due to higher frequencies, which is the first cause of hindering miniaturization of power supplies.
Therefore, it is no exaggeration to say that the volume of the high-frequency switching power supply is currently determined by the volume of the magnetic component. Therefore, in recent years, research on a thin film transformer using a thin film forming technique has been advanced in order to cope with higher frequencies, and development of a small power source in which a switching frequency is increased to a MHz band has been strongly desired.
【０００３】図３に従来の薄膜形成技術で作製された薄
膜トランス（例えば、Ｔ．ＹＡＣＨＩ，Ｍ．ＭＩＮＯ，
Ａ．ＴＡＧＯ，ａｎｄ Ｋ．ＹＡＮＡＧＩＳＡＷＡ，
“ＡＮＥＷ ＰＬＡＮＡＲ ＭＩＣＲＯＴＲＡＮＳＦＯ
ＲＭＥＲ ＦＯＲ ＵＳＥＩＮ ＭＩＣＲＯ−ＳＷＩＴ
ＣＨＩＮＧ−ＣＯＮＶＥＲＴＥＲＳ”，ＩＥＥＥＰＥＳ
Ｃ Ｒｅｃ．，ｐｐ．２０−２６，Ｊｕｎ．，１９９
１．）の構造模式図を示す。図中、１は基板、２は絶縁
層、３は磁性層、４は１次巻線、５は２次巻線を示して
いる。3A and 3B show a thin film transformer manufactured by a conventional thin film forming technique (for example, T.YACHI, M.MINO,
A. TAGO, and K.K. YANAGISAWA,
"ANEW PLANAR MICROTRANSFO
RMER FOR USEIN MICRO-SWIT
CHING-CONVERTERS ", IEEEPES
C Rec. , Pp. 20-26, Jun. , 199
1. ) Shows a schematic structure diagram. In the figure, 1 is a substrate, 2 is an insulating layer, 3 is a magnetic layer, 4 is a primary winding, and 5 is a secondary winding.
【０００４】従来、この種の薄膜トランス・インダクタ
の作製は、以下のように行われていた。すなわち、表面
が絶縁性であるガラスやフェライト，またはＳｉ基板に
ＳｉＯ2を堆積した基板１上に、下部導体層をスパッタ
等の薄膜形成手法で成膜し、これをパターニングして帯
状の下部導体を形成し、この上に絶縁層２をフォトレジ
スト，ＳｉＯ2，ＳｉＯ，Ａｌ2Ｏ3，ポリイミド樹脂等
で形成し、これを平坦化したのちパーマロイ，ＣｏＺｒ
Ｒｅ等の磁性膜層をスパッタ等で形成し、パターンニン
グして長方形形状の磁性層３としたのち、この上にふた
たび絶縁層２を形成し、さらに本絶縁層２にスルーホー
ルを形成し、上部導体層形成後、パターンニングで帯状
の上部導体を形成して作製される。これら上部導体と下
部導体とは前記スルーホールを通して接続され、磁性層
３を取り巻くように１次巻線４，２次巻線５が構成さ
れ、トランスが作製される。Conventionally, the fabrication of this type of thin film transformer / inductor has been performed as follows. That is, a lower conductor layer is formed by a thin film forming method such as sputtering on a substrate 1 having an insulating surface such as glass or ferrite, or a Si substrate on which SiO 2 is deposited, and is patterned to form a strip-shaped lower conductor. Is formed, and the insulating layer 2 is formed on it with photoresist, SiO 2 , SiO, Al 2 O 3 , polyimide resin, etc., and after flattened, permalloy, CoZr
After forming a magnetic film layer of Re or the like by sputtering or the like and patterning to form a rectangular magnetic layer 3, an insulating layer 2 is formed again on the rectangular magnetic layer 3, and a through hole is formed in the main insulating layer 2. After forming the upper conductor layer, a strip-shaped upper conductor is formed by patterning. The upper conductor and the lower conductor are connected to each other through the through hole, and the primary winding 4 and the secondary winding 5 are formed so as to surround the magnetic layer 3 to manufacture a transformer.
【０００５】こうして作製された薄膜トランスやインダ
クタは、チップとして切断されて、別の基板上に回路チ
ップと同様に実装され、使用されている。特にスイッチ
ング電源の変換効率向上のために、ＭＯＳＦＥＴを整流
素子として使用する同期整流回路においては、ＭＯＳＦ
ＥＴチップに並べて薄膜トランスチップを実装し、互い
の端子をワイヤボンディングおよび基板上に形成した印
刷配線によって接続して使用されている。The thin film transformer and inductor thus produced are cut into chips and mounted on another substrate in the same manner as circuit chips and used. In particular, in order to improve the conversion efficiency of the switching power supply, in a synchronous rectification circuit that uses a MOSFET as a rectification element, a MOSF
The thin film transformer chips are mounted side by side on the ET chip, and the terminals are used by being connected by wire bonding and printed wiring formed on the substrate.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記従
来技術による薄膜トランスの実装方法では、上記したよ
うに相互の接続にリード線あるいはボンディングワイヤ
等を使用するため、本来の小形化・薄形化の効果が十分
ではなかった。また、ワイヤ類を引き回すために、不要
な容量分やインダクタンス分が発生し高周波での特性を
損なう要因となっていた。However, in the method of mounting a thin film transformer according to the above-mentioned prior art, since lead wires or bonding wires are used for mutual connection as described above, it is possible to reduce the size and thickness of the original device. The effect was not enough. In addition, since the wires are laid around, unnecessary capacitance and inductance are generated, which is a factor that impairs the characteristics at high frequencies.
【０００７】本発明は、上記問題点を解決するためにな
されたものであり、その目的は、使用するに際し小形・
薄形化を実現し、さらに高周波特性を向上させる高周波
スイッチング電源用薄膜トランスを提供することにあ
る。The present invention has been made in order to solve the above-mentioned problems, and its purpose is to reduce the size and
An object of the present invention is to provide a thin film transformer for a high frequency switching power supply which realizes a thin structure and further improves high frequency characteristics.
【０００８】[0008]
【課題を解決するための手段】本発明の高周波スイッチ
ング電源用薄膜トランスは、同期整流用素子としてＭＯ
ＳＦＥＴを作り込んだ基板上に絶縁層を介して薄膜トラ
ンスを作製し、表面配線，スルーホールを介して、上記
ＭＯＳＦＥＴと薄膜トランス相互の接続を行う構成によ
って、素子の小形化・薄形化と配線の最短化による高周
波特性の向上および順方向電圧降下の低減による高効率
化を達成するものである。A thin film transformer for a high frequency switching power supply according to the present invention is an MO device as a synchronous rectification element.
A thin film transformer is formed on an SFET-embedded substrate through an insulating layer, and the MOSFET and the thin film transformer are connected to each other through surface wiring and through holes. It is intended to improve the high frequency characteristics by shortening the wiring and to improve the efficiency by reducing the forward voltage drop.
【０００９】[0009]
【作用】本発明の高周波スイッチング電源用薄膜トラン
スは、基板としてＳｉ，Ｇｅ等の半導体基板を使用し、
半導体プロセス技術により基板に同期整流素子などとし
てＭＯＳＦＥＴを作り付け、絶縁層を介したのち、薄膜
形成技術を用いてトランスを作製する。そして、この薄
膜トランスの接続端とＭＯＳＦＥＴ相互の接続には、通
常の基板上の表面配線のほか絶縁層を通るスルーホール
等の接続手段を用いて行うことにより、同期整流用素子
などとトランスからなる構成を大幅に小形・薄形化する
と同時に、配線の最短化により、抵抗・容量を低減し、
高周波特性を改善する。さらに、基板に作り付けたＭＯ
ＳＦＥＴを整流ダイオードの代替として使用することに
より、順方向電圧（ＶF）を低く設定できるようにし、
電源の出力損のうち、最も大きな割合を持つ整流回路で
の損失を低減させ、特に低電圧出力電源に好適に適用可
能にする。The thin film transformer for a high frequency switching power supply of the present invention uses a semiconductor substrate such as Si or Ge as a substrate,
A MOSFET is built in the substrate as a synchronous rectifying element by a semiconductor process technology, and an insulating layer is interposed therebetween, and then a thin film forming technology is used to manufacture a transformer. The connection ends of the thin film transformer and the MOSFETs are connected to each other by using a connecting means such as a through hole passing through an insulating layer in addition to the normal surface wiring on the substrate so that the synchronous rectifying element and the transformer can be connected to each other. The configuration will be significantly smaller and thinner, and at the same time the resistance and capacitance will be reduced by shortening the wiring.
Improve high frequency characteristics. Furthermore, MO built into the substrate
The use of SFET as an alternative to the rectifier diode, to be set low forward voltage (V F),
The loss in the rectifier circuit, which has the largest proportion of the output loss of the power supply, is reduced, and it is particularly applicable to the low voltage output power supply.
【００１０】[0010]
【実施例】以下、本発明の実施例を、図面を参照して詳
細に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【００１１】図１（ａ），（ｂ），（ｃ）は、本発明の
一実施例の構成を示す平面図とその平面図中のＸ−Ｘ′
およびＹ−Ｙ′間の断面部分拡大図である。本実施例で
は、基板１０としてｎ-エピタキシャル層を持つｐ形Ｓ
ｉ基板を用い、２個のＭＯＳＦＥＴ：Ａ1，Ａ2を半導体
プロセスにより作り込んだ後、ＰＳＧ等による保護膜を
形成して絶縁層１２ａとし、その上に薄膜トランス１１
を薄膜形成技術により作製している。なお、半導体の基
板１０をｎ形Ｓｉ基板やＧｅ基板としても良い。また、
半導体の基板１０中に作製するＭＯＳＦＥＴは１個だけ
作製した場合も基本的には変わらない。1 (a), 1 (b) and 1 (c) are plan views showing the structure of an embodiment of the present invention and XX 'in the plan views.
FIG. 3 is an enlarged view of a partial cross section between YY ′ and YY ′. In this embodiment, a p-type S having an n − epitaxial layer as the substrate 10 is used.
After using the i substrate to fabricate two MOSFETs: A 1 and A 2 by a semiconductor process, a protective film such as PSG is formed as an insulating layer 12a, and the thin film transformer 11 is formed thereon.
Is manufactured by a thin film forming technique. The semiconductor substrate 10 may be an n-type Si substrate or a Ge substrate. Also,
Even if only one MOSFET is formed in the semiconductor substrate 10, it basically does not change.
【００１２】続いて、ＭＯＳＦＥＴ付き薄膜トランス形
成例を作製工程順に説明する。図１（ｂ）中に破線で示
したＭＯＳＦＥＴ：Ａ1，Ａ2はドレインを共通として作
製されており、表面にはＰＳＧ等の絶縁層１２ａをＣＶ
Ｄ法等で堆積している。初めにバイアススパッタリング
等によりＳｉＯ2等の絶縁層１２ｂを形成し、平坦化処
理を行う。その上にＣｏＺｒＲｅ，ＣｏＦｅＳｉＢ等の
磁性膜をスパッタリング法等で堆積し、イオンビームエ
ッチング法等でパターンニングして下部磁性層１４を作
製する（図１（ｃ））。その後、再び上記と同様にＳｉ
Ｏ2等を堆積し、平坦化処理を行い絶縁層１２ｃとす
る。その後、ＭＯＳＦＥＴ：Ａ1，Ａ2のソース電極１３
ａ′，１３ｅ′，ゲート電極１３ｂ′，１３ｄ′，ドレ
イン電極１３ｃ′（共通）上に絶縁層１２ａ，１２ｂ，
１２ｃを貫通するスルーホールをイオンビームエッチン
グ等により形成する（図１（ｂ））。引き続いて絶縁層
１２ｃ上にＣｕ等の導体層を電子ビーム蒸着法等で成膜
し、前記のスルーホールの内部を充填すると共に、導体
層をパターンニングして帯状の下部導体１５ａおよびＭ
ＯＳＦＥＴの各電極端子１３ａ″，１３ｂ，１３ｃ″，
１３ｄ，１３ｅ″を形成する。この時、ＭＯＳＦＥＴの
ゲート電極端子１３ｂ，１３ｄと薄膜トランス１１のゲ
ート駆動用巻線端子１３ｆ，１３ｇをＣｕ等の導体層で
形成した配線パタン１５ｂ，１５ｃによってそれぞれ接
続する。Next, an example of forming a thin film transformer with a MOSFET will be described in the order of manufacturing steps. The MOSFETs A 1 and A 2 shown by broken lines in FIG. 1B are manufactured with a common drain, and an insulating layer 12a such as PSG is provided on the surface of the CV.
It is deposited by the D method or the like. First, an insulating layer 12b such as SiO 2 is formed by bias sputtering or the like, and a flattening process is performed. A magnetic film of CoZrRe, CoFeSiB or the like is deposited thereon by a sputtering method or the like and patterned by an ion beam etching method or the like to form the lower magnetic layer 14 (FIG. 1C). Then, again as above, Si
O 2 or the like is deposited and flattened to form an insulating layer 12c. Then, the source electrodes 13 of the MOSFETs A 1 and A 2
a ', 13e', gate electrodes 13b ', 13d', drain electrode 13c '(common), insulating layers 12a, 12b,
A through hole penetrating 12c is formed by ion beam etching or the like (FIG. 1B). Subsequently, a conductor layer of Cu or the like is formed on the insulating layer 12c by an electron beam evaporation method or the like to fill the inside of the through hole, and the conductor layer is patterned to form strip-shaped lower conductors 15a and M.
Each electrode terminal 13a ", 13b, 13c" of the OSFET,
13d, 13e "are formed. At this time, the gate electrode terminals 13b, 13d of the MOSFET and the gate driving winding terminals 13f, 13g of the thin film transformer 11 are connected by wiring patterns 15b, 15c formed of a conductor layer such as Cu, respectively. To do.
【００１３】次に、絶縁層１２ｄを形成した後、中間磁
性膜をスパッタリング法等により成膜し、パターンニン
グして中心磁性層１６とする。さらに、この上に絶縁層
１２ｅを形成し、平坦化を行う。その後、１３ａ″，１
３ｃ″，１３ｅ″の電極端子上に絶縁層１２ｄ，１２ｅ
を貫通するスルーホールと上下導体層（下部導体１５ａ
と次に形成する上部導体１７ａ等）を接続するためのス
ルーホールとをイオンビームエッチング等により形成す
る。引き続いて絶縁層１２ｅ上にＣｕ等の導体層を電子
ビーム蒸着法等で成膜し、前記スルーホールの内部を充
填するとともに、導体層をパターンニングして上部導体
１７ａおよびＭＯＳＦＥＴの電極端子１３ａ，１３ｃ，
１３ｅを形成する。この時、トランスの１次側外部端子
１７ｂ，１７ｃ、２次側端子１７ｄ，１７ｅ、外部接続
端子１７ｆ，１７ｇ、さらに配線パタン１７ｈ〜１７ｋ
（図１（ａ））をパターンニングして作製し、トランス
の２次側端子１７ｄ，１７ｅとＭＯＳＦＥＴ：Ａ1の電
極端子１３ａ，１３ｅ、ＭＯＳＦＥＴ：Ａ2の電極端子
１３ｃ，１３ｅと外部端子１７ｆ，１７ｇとをそれぞれ
接続する。そして、さらに絶縁層１２ｆを形成し、平坦
化を行った後、上部磁性膜を成膜し、パターンニングし
て上部磁性層１８とする。最後に、絶縁層１２ｇを形成
したのち、端子１７ｂ，１７ｃ，１７ｆ，１７ｇ部にス
ルーホールを開けて外部端子とし、完成する。Next, after forming the insulating layer 12d, an intermediate magnetic film is formed by a sputtering method or the like and patterned to form the central magnetic layer 16. Further, an insulating layer 12e is formed on this and flattening is performed. Then 13a ", 1
Insulating layers 12d and 12e on the electrode terminals of 3c "and 13e"
Through hole and upper and lower conductor layers (lower conductor 15a
And a through hole for connecting the upper conductor 17a and the like to be formed next) are formed by ion beam etching or the like. Subsequently, a conductor layer of Cu or the like is formed on the insulating layer 12e by an electron beam evaporation method or the like to fill the inside of the through hole, and the conductor layer is patterned to form the upper conductor 17a and the electrode terminal 13a of the MOSFET. 13c,
13e is formed. At this time, primary side external terminals 17b and 17c of the transformer, secondary side terminals 17d and 17e, external connection terminals 17f and 17g, and wiring patterns 17h to 17k.
(FIG. 1 (a)) is patterned to prepare, transformer secondary terminals 17d, 17e and MOSFET: A 1 of the electrode terminals 13a, 13e, MOSFET: A 2 of the electrode terminals 13c, 13e and the external terminal 17f , 17 g, respectively. Then, the insulating layer 12f is further formed and planarized, and then an upper magnetic film is formed and patterned to form the upper magnetic layer 18. Finally, after forming the insulating layer 12g, through holes are formed in the terminals 17b, 17c, 17f and 17g to form external terminals, which is completed.
【００１４】図２は、この実施例に適用する１石フォワ
ード形コンバータの回路図を示す。図中、１１は薄膜ト
ランス、Ｌ1は平滑インダクタ、１９は直流電源、２０
はパルス発生器（Ｐ．Ｇ）、Ｔｒ1はスイッチング素
子、Ａ1，Ａ2はＭＯＳＦＥＴ、Ｃ1，Ｃ2はコンデンサ、
Ｒ1は抵抗、ＲLは負荷である。このコンバータの構成に
おいて、薄膜トランス１１の一次巻き線側には直流電源
１９とスイッチング素子Ｔｒ1が直列に接続され、直流
電源１９に並列にコンデンサＣ1が接続されている。こ
の構成により、主トランスの薄膜トランス１１で昇圧も
しくは降圧された電力が、ＭＯＳＦＥＴ：Ａ1，Ａ2の回
路で整流され、平滑インダクタＬ1，コンデンサＣ2で平
滑されて、負荷ＲLに供給され得るようになっている。FIG. 2 shows a circuit diagram of a one-stone forward type converter applied to this embodiment. In the figure, 11 is a thin film transformer, L 1 is a smoothing inductor, 19 is a DC power supply, and 20
Is a pulse generator (PG), Tr 1 is a switching element, A 1 and A 2 are MOSFETs, C 1 and C 2 are capacitors,
R 1 is a resistance and R L is a load. In the configuration of this converter, a DC power supply 19 and a switching element Tr 1 are connected in series on the primary winding side of the thin film transformer 11, and a capacitor C 1 is connected in parallel to the DC power supply 19. With this configuration, the power boosted or stepped down by the thin film transformer 11 of the main transformer is rectified by the circuit of MOSFETs: A 1 and A 2 , smoothed by the smoothing inductor L 1 and the capacitor C 2 , and supplied to the load RL . It can be done.
【００１５】上記実施例は、図２中の破線で示した部分
ＺをＳｉ基板上に作製したものである。すなわち図１に
おいて、薄膜トランス１１，ＭＯＳＦＥＴ：Ａ1，Ａ
2は、絶縁層を通るスルーホールと配線層を通して上記
に示したように相互に接続され、外部配線用端子１７
ｂ，１７ｃ，１７ｆ，１７ｇを基板１０表面に作製して
いる。図１（ａ）中のＭＯＳＦＥＴの電極端子１３ａ〜
１３ｅ、トランス１次側端子１７ｂ，１７ｃ、およびト
ランス２次側端子１３ｆ，１７ｄ，１７ｅ，１３ｇは、
図２の回路図中の接続点（１３ａ）〜（１３ｅ）、（１
７ｂ），（１７ｃ），（１７ｆ），（１７ｇ）、および
（１３ｆ），（１７ｄ），（１７ｅ），（１３ｇ）にそ
れぞれ対応しており、周辺素子類と接続される。ただ
し、図１（ａ）中の配線パタン１５ｂと１７ｈ，１５ｃ
と１７ｉは、絶縁層を介して交差しており、互いに接触
していない。In the above embodiment, the portion Z shown by the broken line in FIG. 2 is formed on the Si substrate. That is, in FIG. 1, a thin film transformer 11, MOSFETs: A 1 , A
2 are connected to each other through the through hole passing through the insulating layer and the wiring layer as described above, and are connected to the external wiring terminal 17
b, 17c, 17f and 17g are formed on the surface of the substrate 10. The electrode terminals 13a to 13a of the MOSFET in FIG.
13e, the transformer primary side terminals 17b and 17c, and the transformer secondary side terminals 13f, 17d, 17e and 13g,
Connection points (13a) to (13e), (1 in the circuit diagram of FIG.
7b), (17c), (17f), (17g), and (13f), (17d), (17e), (13g), respectively, and are connected to peripheral elements. However, the wiring patterns 15b and 17h and 15c in FIG.
And 17i intersect with each other through the insulating layer and are not in contact with each other.
【００１６】以上のように構成した実施例を試作し、動
作試験を行った結果、従来の実装方法による動作可能な
周波数以上の高周波域においても正常に動作することが
確認できた。一方、Ｓｉ基板１０中にＭＯＳＦＥＴ：Ａ
1，Ａ2を作り込むことにより、個別部品を実装した従来
の実装方法に比べて、体積・重量を大幅に低減すること
ができた。また、配線の余分な引き回しを低減したこと
により、回路動作も安定し、従来のダイオードによる整
流を行った場合に比べ、順方向電圧（ＶF）が低下し、
電源効率も上昇した。As a result of making a prototype of the embodiment configured as described above and performing an operation test, it has been confirmed that the embodiment normally operates even in a high frequency range above the operable frequency by the conventional mounting method. On the other hand, in the Si substrate 10, the MOSFET: A
By incorporating 1 and A 2 , the volume and weight could be significantly reduced compared to the conventional mounting method in which individual parts were mounted. Also, by reducing the excess wire routing, also stable circuit operation, compared with the case of performing rectification by conventional diode, the forward voltage (V F) is reduced,
Power efficiency has also increased.
【００１７】なお、上記実施例では、薄膜トランスをＳ
ｉ基板に作り付けたＭＯＳＦＥＴの真上部分からはずれ
た場所に作製しているが、薄膜トランスをＭＯＳＦＥＴ
の真上に作製し、スルーホール等を用いて接続できるこ
とは自明である。また、上記実施例では、Ｓｉ基板にＭ
ＯＳＦＥＴのみを作り込んだ例を示したが、必要に応じ
てスイッチング素子，抵抗，コンデンサ類を作り込むこ
とも可能であり、これらと薄膜トランス・インダクタを
接続できることは言うまでもない。このように本発明
は、その主旨に沿って種々に応用され、種々に実施態様
を取り得るものである。In the above embodiment, the thin film transformer is S
The thin film transformer is made in a place off the part directly above the MOSFET built in the i substrate.
It is self-evident that it can be made right above and can be connected using a through hole or the like. In addition, in the above-mentioned embodiment, M is formed on the Si substrate.
Although the example in which only the OSFET is formed is shown, it is needless to say that a switching element, a resistor, and a capacitor can be formed as necessary, and these can be connected to the thin film transformer / inductor. As described above, the present invention can be variously applied and variously embodied in accordance with its gist.
【００１８】[0018]
【発明の効果】以上の説明で明らかなように、本発明の
高周波用薄膜トランスによれば、これまでの個別部品実
装の場合に比べ、大幅な小形・軽量化が実現できる。ま
た、同時に配線の余分な引き回しの低減および整流素子
の順方向電圧ＶFの低減効果により、一層の高周波化と
回路効率の向上が達成できる。As is apparent from the above description, according to the high frequency thin film transformer of the present invention, it is possible to realize a significant reduction in size and weight as compared with the conventional mounting of individual components. At the same time, due to the effect of reducing the extra wiring of the wiring and the effect of reducing the forward voltage V F of the rectifying element, it is possible to further increase the frequency and improve the circuit efficiency.
【図１】本発明の一実施例の平面図および断面部分拡大
図FIG. 1 is a plan view and a partially enlarged sectional view of an embodiment of the present invention.
【図２】上記実施例に適用した１石フォワード形コンバ
ータの回路図FIG. 2 is a circuit diagram of a one-stone forward converter applied to the above embodiment.
【図３】従来の技術を示す構造模式図FIG. 3 is a structural schematic diagram showing a conventional technique.
１０…基板 １１…薄膜トランス １２ａ，１２ｂ，１２ｃ，１２ｄ，１２ｅ，１２ｆ，１
２ｇ…絶縁層 １３ａ′…ＭＯＳＦＥＴ：Ａ1のソース電極 １３ｂ′…ＭＯＳＦＥＴ：Ａ1のゲート電極 １３ｃ′…ＭＯＳＦＥＴ：Ａ1，Ａ2のドレイン電極（共
通） １３ｄ′…ＭＯＳＦＥＴ：Ａ2のゲート電極 １３ｅ′…ＭＯＳＦＥＴ：Ａ2のソース電極 １３ａ，１３ｂ，１３ｃ，１３ｄ，１３ｅ…ＭＯＳＦＥ
Ｔの電極端子 １４…下部磁性層 １５ａ…下部導体 １５ｂ，１５ｃ…配線パタン １６…中心部磁性層 １７ａ…上部導体 １７ｂ，１７ｃ，１７ｄ，１７ｅ，１７ｆ，１７ｇ，１
７ｈ，１７ｉ，１７ｊ，１７ｋ…配線パタン・端子 １８…上部磁性層10 ... Substrate 11 ... Thin film transformer 12a, 12b, 12c, 12d, 12e, 12f, 1
2 g ... insulating layer 13a '... MOSFET: A 1 of the source electrode 13b' ... MOSFET: the gate electrode 13c of A 1 '... MOSFET: A 1 , the drain of the A 2 electrode (common) 13d' ... MOSFET: the gate of the A 2 electrode 13e '... MOSFET: the source electrode 13a of the a 2, 13b, 13c, 13d , 13e ... MOSFE
T electrode terminal 14 ... Lower magnetic layer 15a ... Lower conductor 15b, 15c ... Wiring pattern 16 ... Central magnetic layer 17a ... Upper conductor 17b, 17c, 17d, 17e, 17f, 17g, 1
7h, 17i, 17j, 17k ... Wiring pattern / terminal 18 ... Upper magnetic layer
Claims (1)
成した半導体基板上に絶縁層を介して形成され、前記絶
縁層を通る接続手段を介して前記ＭＯＳＦＥＴの少なく
とも１つに２次巻線が接続されていることを特徴とする
高周波スイッチング電源用薄膜トランス。1. A secondary winding is formed on a semiconductor substrate on which at least one MOSFET is formed, via an insulating layer, and a secondary winding is connected to at least one of the MOSFETs via a connecting means passing through the insulating layer. A thin film transformer for high frequency switching power supplies.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4180181A JPH0629134A (en) | 1992-07-08 | 1992-07-08 | Thin-film transformer for high-frequency switching power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4180181A JPH0629134A (en) | 1992-07-08 | 1992-07-08 | Thin-film transformer for high-frequency switching power supply |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0629134A true JPH0629134A (en) | 1994-02-04 |
Family
ID=16078807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4180181A Pending JPH0629134A (en) | 1992-07-08 | 1992-07-08 | Thin-film transformer for high-frequency switching power supply |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0629134A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998056101A1 (en) * | 1997-06-03 | 1998-12-10 | Lightech Electronics Industries Ltd. | Low voltage illumination system |
| EP1376694A3 (en) * | 2002-04-17 | 2006-08-23 | Sanyo Electric Co., Ltd. | Semiconductor switching circuit device |
| US20150200050A1 (en) * | 2014-01-16 | 2015-07-16 | Fujitsu Limited | Inductor apparatus and inductor apparatus manufacturing method |
-
1992
- 1992-07-08 JP JP4180181A patent/JPH0629134A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998056101A1 (en) * | 1997-06-03 | 1998-12-10 | Lightech Electronics Industries Ltd. | Low voltage illumination system |
| EP1376694A3 (en) * | 2002-04-17 | 2006-08-23 | Sanyo Electric Co., Ltd. | Semiconductor switching circuit device |
| US20150200050A1 (en) * | 2014-01-16 | 2015-07-16 | Fujitsu Limited | Inductor apparatus and inductor apparatus manufacturing method |
| US9837208B2 (en) * | 2014-01-16 | 2017-12-05 | Fujitsu Limited | Inductor apparatus and inductor apparatus manufacturing method |
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