JPH06291342A - Photovoltaic device - Google Patents
Photovoltaic deviceInfo
- Publication number
- JPH06291342A JPH06291342A JP5105001A JP10500193A JPH06291342A JP H06291342 A JPH06291342 A JP H06291342A JP 5105001 A JP5105001 A JP 5105001A JP 10500193 A JP10500193 A JP 10500193A JP H06291342 A JPH06291342 A JP H06291342A
- Authority
- JP
- Japan
- Prior art keywords
- amorphous silicon
- interface
- intrinsic amorphous
- semiconductor
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/546—Polycrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
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- Photovoltaic Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、太陽電池や光センサ等
の光起電力装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to photovoltaic devices such as solar cells and photosensors.
【０００２】[0002]
【従来の技術】一般に、光起電力装置は、発電層として
用いられる半導体の種類により、単結晶系、多結晶系、
非晶質系に分類される。2. Description of the Related Art Generally, a photovoltaic device has a single crystal system, a polycrystalline system, or
It is classified as an amorphous system.
【０００３】この中で、ここ数年、活発な研究開発がな
されたのが、非晶質系からなる光起電力装置である。そ
の理由として、従来の単結晶系のものと比較して、非晶
質系は大面積の形成が容易であり、かつその製造工程に
要するエネルギーが小さくてすむことなどから低コスト
が期待できたためである。[0003] Of these, the ones that have been actively researched and developed in the last few years are photovoltaic devices made of an amorphous system. The reason is that compared with the conventional single crystal system, the amorphous system is easy to form a large area, and the energy required for the manufacturing process can be small, so that the low cost can be expected. Is.
【０００４】しかし、これまで多くの研究成果を得たに
もかかわらず、その性能面では単結晶系の光起電力装置
には及んでいない。However, in spite of the fact that many research results have been obtained so far, in terms of performance, it does not reach the single crystal type photovoltaic device.
【０００５】そこで、近年、光起電力装置の開発の新た
な試みとして、非晶質半導体と結晶系半導体（単結晶半
導体，多結晶半導体）とを組み合わせて半導体接合を形
成させることにより、それぞれの物性が持つ長所を活か
すことで、より高い光電変換効率を得る研究が進められ
ている。Therefore, in recent years, as a new attempt to develop a photovoltaic device, a semiconductor junction is formed by combining an amorphous semiconductor and a crystalline semiconductor (single crystal semiconductor, polycrystalline semiconductor) to form a semiconductor junction. Research is being conducted to obtain higher photoelectric conversion efficiency by making the most of the advantages of physical properties.
【０００６】しかし、通常、前記の各半導体を単に接触
させるだけでは、良好な半導体接合を形成することはで
きない。例えば、図５（ｂ）に示すように、ｎ型の単結
晶半導体１１とｐ型の非晶質半導体１２とを直接接触さ
せ、ｐｎ接合（ヘテロｐｎ接合）を形成したとしても、
同図（ａ）のバンドプロファイルに示すように、ホール
に対する高い障壁が形成されるため、光起電力装置とし
て十分な光電変換効率を得ることはできない。However, normally, it is not possible to form a good semiconductor junction simply by bringing the above semiconductors into contact with each other. For example, as shown in FIG. 5B, even if the n-type single crystal semiconductor 11 and the p-type amorphous semiconductor 12 are directly contacted with each other to form a pn junction (hetero pn junction),
As shown in the band profile of FIG. 10A, a high barrier against holes is formed, so that it is not possible to obtain sufficient photoelectric conversion efficiency as a photovoltaic device.
【０００７】これは、光照射により発生した半導体中の
光生成キャリアの多くが前記ｐｎ接合界面での再結合に
より失われてしまい、前記光生成キャリアを外部に取り
出せないためである。This is because most of the photo-generated carriers in the semiconductor generated by light irradiation are lost by recombination at the pn junction interface, and the photo-generated carriers cannot be taken out to the outside.
【０００８】かかる再結合の原因は、前記非晶質半導体
の局在準位によると考えられる。即ち、非晶質半導体で
は、一般に導電型決定不純物をドーピングすることによ
り、その膜質は著しく劣化する。この影響はバンドギャ
ップ内の局在準位の増加として現れる。そして、この局
在準位は、ｐｎ接合界面に界面準位を生成するように働
きかけ、結果として前記光キャリアを再結合させること
になる。The cause of such recombination is considered to be the localized level of the amorphous semiconductor. That is, in the case of an amorphous semiconductor, the film quality of an amorphous semiconductor is significantly deteriorated by doping with a conductivity type determining impurity. This effect appears as an increase in localized levels in the band gap. Then, this localized level acts to generate an interface level at the pn junction interface, and as a result, the photocarriers are recombined.
【０００９】そこで、本願出願人は、図６（ｂ）に示す
ように、前記のｐｎ接合を薄膜の真性非晶質半導体膜１
３を介在させて行う構造（以下、ＨＩＴ構造という。）
を有した光起電力装置を提案した（特開平４−１９９７
５０号公報参照）。これにより、ｐｎ接合界面での膜質
が良好なものとなり、界面準位密度が低下し、光生成キ
ャリアの再結合を抑制することが可能となった。即ち、
同図（ａ）に示すように、ホールに対する障壁が幾分低
くなり、従来よりも高い光電変換効率を得ることができ
た。Therefore, the applicant of the present application, as shown in FIG. 6 (b), uses the above-mentioned pn junction as a thin intrinsic amorphous semiconductor film 1.
Structure with 3 intervening (hereinafter referred to as HIT structure)
Has proposed a photovoltaic device having a light emitting diode (Japanese Patent Laid-Open No. 4-1997).
No. 50). As a result, the film quality at the pn junction interface was improved, the interface state density was lowered, and recombination of photogenerated carriers could be suppressed. That is,
As shown in FIG. 6A, the barrier against holes was somewhat lowered, and higher photoelectric conversion efficiency than before could be obtained.
【００１０】[0010]
【発明が解決しようとする課題】しかしながら、前記の
ＨＩＴ構造は、ｎ型の単結晶半導体膜１１に真性非晶質
半導体膜１３を接触するものであり、これが良質な膜で
あるとしても、単結晶半導体膜１１との間で異種物質界
面を形成するものであるから、この異種物質界面におい
て分子ネットワークが連続的に繋がり難いという問題は
依然として残される。即ち、未結合手（ダングリングボ
ンド）や格子歪みに起因する局在準位ができるため、界
面準位を十分に低減することはできない。加えて、ホー
ルに対する障壁が低くなったとは言え、未だ残ってい
る。However, in the above HIT structure, the intrinsic amorphous semiconductor film 13 is brought into contact with the n-type single crystal semiconductor film 11, and even if this is a good quality film, Since a heterogeneous material interface is formed with the crystalline semiconductor film 11, there remains a problem that it is difficult to continuously connect a molecular network at the heterogeneous material interface. In other words, localized states due to dangling bonds or lattice distortions are formed, so that the interface states cannot be sufficiently reduced. In addition, although the barrier to holes has dropped, it still remains.
【００１１】本発明は、上記の事情に鑑み、異種物質界
面における分子ネットワークが連続的に繋がり易くなる
ようにして界面準位を低減し、光電変換効率を向上させ
得る光起電力装置を提供することを目的とする。In view of the above circumstances, the present invention provides a photovoltaic device capable of reducing the interface state and facilitating photoelectric conversion efficiency by facilitating continuous connection of molecular networks at interfaces of different substances. The purpose is to
【００１２】[0012]
【課題を解決するための手段】本発明の光起電力装置
は、上記の課題を解決するために、互いに逆導電型の関
係を有する非晶質半導体と結晶系半導体との間に薄膜の
真性非晶質半導体を介在させた光起電力装置において、
前記の真性非晶質半導体は、フッ素を含有し、前記の非
晶質半導体との界面側では結晶系半導体との界面側にお
けるよりもフッ素含有量が少なくされていることを特徴
としている。In order to solve the above-mentioned problems, the photovoltaic device of the present invention has an intrinsic thin film formed between an amorphous semiconductor and a crystalline semiconductor having a relationship of opposite conductivity types to each other. In a photovoltaic device including an amorphous semiconductor,
The intrinsic amorphous semiconductor contains fluorine, and the content of fluorine on the interface side with the amorphous semiconductor is smaller than that on the interface side with the crystalline semiconductor.
【００１３】[0013]
【作用】上記の構成によれば、前記の真性非晶質半導体
がフッ素を含有することによりその分子ネットワークは
結晶系に近いものとなり、結晶系半導体と真性非晶質半
導体との界面における分子ネットワークの繋がりは連続
的なものに近づく。即ち、従来は上記の界面にだけかか
っていた格子歪みがならされるため、界面準位密度が低
減する。加えて、前記真性非晶質半導体の裏面側でのバ
ンドギャップＥｇが結晶系半導体のＥｇに近づくため、
光電変換効率が向上する。一方、フッ素の含有量は、非
晶質半導体との界面側で少なくされているので、非晶質
半導体側（光入射側）でのバンドギャップは結晶系半導
体側（裏面側）でのバンドギャップよりも大きくなり、
当該真性非晶質半導体にフッ素が均一に含まれている場
合と比較して高い電圧を得ることが可能となる。According to the above structure, since the intrinsic amorphous semiconductor contains fluorine, its molecular network becomes close to that of a crystalline system, and the molecular network at the interface between the crystalline semiconductor and the intrinsic amorphous semiconductor. The connection is close to continuous. That is, since the lattice strain that has hitherto been applied only to the interface is smoothed, the interface state density is reduced. In addition, the bandgap Eg on the back surface side of the intrinsic amorphous semiconductor approaches the Eg of the crystalline semiconductor,
The photoelectric conversion efficiency is improved. On the other hand, since the content of fluorine is small on the interface side with the amorphous semiconductor, the band gap on the amorphous semiconductor side (light incident side) is the band gap on the crystalline semiconductor side (back side). Bigger than
A higher voltage can be obtained as compared with the case where fluorine is uniformly contained in the intrinsic amorphous semiconductor.
【００１４】[0014]
【実施例】以下、本発明をその実施例を示す図に基づい
て説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments.
【００１５】図１は、本発明の光起電力装置の断面図お
よびこれに対応付けたバンドプロファイルを示した概念
図である。FIG. 1 is a conceptual diagram showing a cross-sectional view of a photovoltaic device of the present invention and a band profile associated therewith.
【００１６】同図（ｂ）において、１はｎ型単結晶シリ
コン基板、２は真性非晶質シリコン膜、３は前記ｎ型単
結晶シリコン基板１と逆導電型となるｐ型非晶質シリコ
ン膜、４はｎ型単結晶シリコン基板１とコンタクトする
アルミニウムなどからなる電極、５はＩＴＯ（Ｉｎｄｉ
ｕｍ Ｔｉｎ Ｏｘｉｄｅ）膜や酸化スズ等からなる透
明電極膜である。In FIG. 1B, 1 is an n-type single crystal silicon substrate, 2 is an intrinsic amorphous silicon film, and 3 is a p-type amorphous silicon having a conductivity type opposite to that of the n-type single crystal silicon substrate 1. Films, 4 are electrodes made of aluminum or the like in contact with the n-type single crystal silicon substrate 1, and 5 are ITO (Indi).
um Tin Oxide) film and a transparent electrode film made of tin oxide or the like.
【００１７】前記の真性非晶質シリコン膜２は、水素
（Ｈ）およびフッ素（Ｆ）を含んでおり、このフッ素
（Ｆ）量は前記のｎ型単結晶シリコン基板１との界面側
（裏面側）で多くなっている。即ち、真性非晶質シリコ
ン膜２中のＦ量（ＣF ），Ｈ量（ＣH ）において、光入
射側のＣF ／ＣH ＜上記界面側（裏面側）のＣF ／
ＣH 、の関係を充たすようにしてある。また、本実施例
では、Ｆ量（ＣF ）は、上記界面側（裏面側）で対Ｓｉ
比０．１％程度としている。The intrinsic amorphous silicon film 2 contains hydrogen (H) and fluorine (F), and the amount of this fluorine (F) is at the interface side (back surface) with the n-type single crystal silicon substrate 1. Side) is increasing. Ie, F amount of intrinsic amorphous silicon film 2 (C F), H amount in (C H), the light incident side C F / C H <the interface side (back side) C F /
It is as satisfy the C H, the relationship. Further, in the present embodiment, the amount of F (C F ) is measured with respect to Si on the interface side (back side).
The ratio is about 0.1%.
【００１８】このように、上記界面側（裏面側）にフッ
素（Ｆ）を含むことにより、この界面側では真性非晶質
シリコン膜２は結晶系に近い構造を持つに至り、異種物
質界面を形成するものではあるが、分子ネットワークが
連続的に繋がり易くなる。従って、格子歪みの発生が低
減され、局在準位ができ難くなり、界面準位密度が低減
する。加えて、上記真性非晶質シリコン膜２の裏面側で
のバンドギャップＥｇが、結晶シリコン１のＥｇに近づ
くため、同図（ａ）に示しているように、ホールに対す
る障壁が従来のＨＩＴ構造のものより低くなり、光電変
換効率が向上する。一方、ｐ型非晶質シリコン膜３との
界面側（光入射側）においては、フッ素量は少ない或い
はフッ素は存在しないので、高い電圧が得られるように
なっている。即ち、前述した、光入射側のＣF ／ＣH ＜
裏面側のＣF ／ＣH 、の関係を充たすため、光入射側の
Ｅg ＞裏面側のＥg 、の関係が生じ、真性非晶質シリコ
ン膜２に均一にフッ素（Ｆ）を含めたものよりも、高い
電圧が得られることになる。As described above, by including fluorine (F) on the interface side (back surface side), the intrinsic amorphous silicon film 2 has a structure close to a crystal system on this interface side, and the interface between different substances is formed. Although formed, it becomes easy to continuously connect molecular networks. Therefore, the occurrence of lattice strain is reduced, it becomes difficult to form localized states, and the interface state density is reduced. In addition, since the bandgap Eg on the back surface side of the intrinsic amorphous silicon film 2 approaches the Eg of the crystalline silicon 1, as shown in FIG. And the photoelectric conversion efficiency is improved. On the other hand, on the interface side (light incident side) with the p-type amorphous silicon film 3, the amount of fluorine is small or fluorine does not exist, so that a high voltage can be obtained. That is, as described above, C F / C H on the light incident side
For filling the back side of the C F / C H, the relationship, E g> of the back side E g of the light incident side, the relationship resulting, uniformly including fluorine (F) in the intrinsic amorphous silicon film 2 A higher voltage will be obtained than the ones.
【００１９】本実施例の光起電力装置の形成方法として
は、まず、ｎ型単結晶シリコン基板１上にプラズマＣＶ
Ｄ法により真性非晶質シリコン膜２を成膜する。このプ
ラズマＣＶＤによる膜形成は、基板温度２００℃、ＲＦ
パワー１０Ｗ、反応室内圧力０．１Ｔｏｒｒの条件下で
行った。また、反応室内に供給するガスとしては、Ｓｉ
Ｆ4 ，ＳｉＨ4 ，Ｈ2 を用い、Ｈ2 の流量は１００ｓｃ
ｃｍに、ＳｉＨ4 の流量は１ｓｃｃｍに各々設定した。
一方、ＳｉＦ4 については、図２に示すように、真性非
晶質シリコン膜２の成膜開始時は、流量を１０ｓｃｃｍ
とし、次第に少なくして、必要膜厚が得られるころに流
量が０となるように流量制御している。これにより、ｎ
型単結晶シリコン基板１との界面側でフッ素（Ｆ）を多
く含み次第にフッ素（Ｆ）量が少なくされた真性非晶質
シリコン２が形成される。このように、ｎ型単結晶シリ
コン基板１との界面側でフッ素（Ｆ）を多く含むことに
より、この界面側では、下地となる単結晶に倣った構造
（エピタキシャル結晶構造に近似した構造或いは微結晶
構造）が得られ易くなる。また、上述のようにフッ素
（Ｆ）量を一定の勾配で徐々に少なくすることにより、
真性非晶質シリコン２においてグレーデッドなバンドプ
ロファイルが得られる。As a method of forming the photovoltaic device of this embodiment, first, plasma CV is formed on the n-type single crystal silicon substrate 1.
The intrinsic amorphous silicon film 2 is formed by the D method. The film formation by this plasma CVD is performed at a substrate temperature of 200 ° C. and RF
It was conducted under the conditions of a power of 10 W and a reaction chamber pressure of 0.1 Torr. The gas supplied into the reaction chamber is Si
F 4 , SiH 4 , and H 2 are used, and the flow rate of H 2 is 100 sc
cm, and the flow rate of SiH 4 was set to 1 sccm.
On the other hand, for SiF 4 , as shown in FIG. 2, the flow rate is 10 sccm at the start of the formation of the intrinsic amorphous silicon film 2.
The flow rate is controlled so that the flow rate becomes zero when the required film thickness is obtained. This gives n
Intrinsic amorphous silicon 2 containing a large amount of fluorine (F) and having a gradually reduced amount of fluorine (F) is formed on the interface side with the mold single crystal silicon substrate 1. As described above, since a large amount of fluorine (F) is contained on the interface side with the n-type single crystal silicon substrate 1, the interface side has a structure (a structure similar to an epitaxial crystal structure or a fine structure similar to the epitaxial crystal structure). A crystal structure) is easily obtained. Further, by gradually reducing the amount of fluorine (F) at a constant gradient as described above,
A graded band profile is obtained in the intrinsic amorphous silicon 2.
【００２０】次に、同じくプラズマＣＶＤ法により、真
性非晶質シリコン膜２上にｐ型非晶質シリコン膜３を堆
積する。このプラズマＣＶＤ法による膜形成は、基板温
度２００℃、ＲＦパワー１０Ｗ、反応室内圧力０．１Ｔ
ｏｒｒの条件下で行った。また、反応室内に供給するガ
スとしては、ＳｉＨ4 とＢ2 Ｈ6 を用い、ＳｉＨ4 の流
量は５ｓｃｃｍに設定し、Ｂ2 Ｈ6 のＳｉＨ4 に対する
流量比は５％に設定した。Next, the p-type amorphous silicon film 3 is deposited on the intrinsic amorphous silicon film 2 by the plasma CVD method. The film formation by this plasma CVD method is performed at a substrate temperature of 200 ° C., an RF power of 10 W, and a reaction chamber pressure of 0.1 T.
It was performed under the conditions of orr. SiH 4 and B 2 H 6 were used as the gas supplied into the reaction chamber, the flow rate of SiH 4 was set to 5 sccm, and the flow rate ratio of B 2 H 6 to SiH 4 was set to 5%.
【００２１】次に、光入射側となるｐ型非晶質シリコン
膜３上には透明導電膜５を形成し、ｎ型単結晶シリコン
基板１の裏面には金属電極４を形成する。Next, a transparent conductive film 5 is formed on the p-type amorphous silicon film 3 on the light incident side, and a metal electrode 4 is formed on the back surface of the n-type single crystal silicon substrate 1.
【００２２】これにより、本発明の光起電力装置が得ら
れる。As a result, the photovoltaic device of the present invention can be obtained.
【００２３】図３は、前述したプラズマＣＶＤ法により
真性非晶質シリコン膜２を成膜する工程において、成膜
開始時のＳｉＦ4 ／ＳｉＨ4 流量比を、０％、５％、１
０％としたときの、その各々の条件下で得られた真性非
晶質シリコン膜２を用いた光起電力装置の光電変換効率
を示したグラフである。ここで、ＳｉＦ4 ／ＳｉＨ4流
量比が０の場合とは、真性非晶質シリコン膜２がフッ素
（Ｆ）を含んでいない従来のＨＩＴ構造に相当する。こ
のグラフから明らかなように、本発明の光起電力装置の
光電変換効率は、従来のＨＩＴ構造の光起電力装置に比
べ高くなっていることが分かる。FIG. 3 shows that in the step of forming the intrinsic amorphous silicon film 2 by the above-mentioned plasma CVD method, the SiF 4 / SiH 4 flow rate ratio at the start of film formation is 0%, 5%, 1
6 is a graph showing the photoelectric conversion efficiency of a photovoltaic device using the intrinsic amorphous silicon film 2 obtained under each of the conditions when 0% is set. Here, the case where the SiF 4 / SiH 4 flow rate ratio is 0 corresponds to the conventional HIT structure in which the intrinsic amorphous silicon film 2 does not contain fluorine (F). As is clear from this graph, it is understood that the photovoltaic conversion efficiency of the photovoltaic device of the present invention is higher than that of the conventional HIT structure photovoltaic device.
【００２４】図４は、従来のＨＩＴ構造を有する光起電
力装置と、本発明の構造を有する光起電力装置とにおけ
る、各々の真性非晶質シリコン膜２の膜厚を変化させた
ときの光電変換効率の変化を示したグラフである。この
グラフから分かるように、共に真性非晶質シリコン膜２
の膜厚が数Å〜２５０Åの間においてヘテロｐｎ接合構
造のものより高い変換効率を示すが、その効率の高さ
は、本発明の構造を有する光起電力装置の方が高くなっ
ている。また、本発明の構造では、真性非晶質シリコン
膜２の膜厚が約３０Åのところで光電変換効率のピーク
を迎え、真性非晶質シリコン膜２の最適膜厚は従来のＨ
ＩＴ構造のものよりも薄くなっている。FIG. 4 shows a case where the thickness of each intrinsic amorphous silicon film 2 is changed in the conventional photovoltaic device having the HIT structure and the photovoltaic device having the structure of the present invention. 6 is a graph showing a change in photoelectric conversion efficiency. As can be seen from this graph, both the intrinsic amorphous silicon film 2
Shows a higher conversion efficiency than that of the hetero pn junction structure when the film thickness is between several Å and 250 Å, but the efficiency is higher in the photovoltaic device having the structure of the present invention. In the structure of the present invention, the peak of photoelectric conversion efficiency is reached when the film thickness of the intrinsic amorphous silicon film 2 is about 30 Å, and the optimum film thickness of the intrinsic amorphous silicon film 2 is the same as that of the conventional H film.
It is thinner than the IT structure.
【００２５】なお、真性非晶質シリコン膜２の膜厚が２
５０Åを越えると光電変換効率が低下するのは、従来の
ＨＩＴ構造においてもいえるものであるが、これは、真
性非晶質シリコン膜２が、界面準位の低減を主な機能と
し、当該膜２自体の層中で発生する光キャリアはほとん
ど変化効率に寄与せず、むしろ、変換効率の低下を引き
起こすためと考えられる。The thickness of the intrinsic amorphous silicon film 2 is 2
The fact that the photoelectric conversion efficiency decreases when the thickness exceeds 50 Å can be said also in the conventional HIT structure. This is because the intrinsic amorphous silicon film 2 has a main function of reducing the interface state, and It is considered that the photocarriers generated in the layer of 2 itself hardly contribute to the change efficiency, but rather cause the decrease of the conversion efficiency.
【００２６】また、本発明で採用する真性非晶質シリコ
ン膜の膜厚の下限値としては、通常のプラズマＣＶＤ装
置やスパッタ装置あるいは、常圧ＣＶＤ装置などによる
形成で制御可能な数Åまでとされるが、その膜厚の制御
容易性からすれば、２０Å以上が好適である。Further, the lower limit of the film thickness of the intrinsic amorphous silicon film used in the present invention is up to a few Å which can be controlled by a normal plasma CVD apparatus, a sputtering apparatus or a normal pressure CVD apparatus. However, from the viewpoint of easiness of controlling the film thickness, 20 Å or more is preferable.
【００２７】更に、ここでいう真性非晶質シリコンと
は、例えば、前記のプラズマＣＶＤ法によって形成され
たものであれば、導電型決定不純物としてのドーピング
ガスを全く添加することなく形成された真性非晶質シリ
コンを含むことは勿論であるが、それ以外に微量のドー
ピングガスを添加して形成することにより、実質的に真
性型に制御された非晶質シリコンをも含むものである。Further, the intrinsic amorphous silicon referred to here is, for example, an intrinsic amorphous silicon formed by the plasma CVD method described above without adding any doping gas as a conductivity type determining impurity. It includes, of course, amorphous silicon, but it also includes amorphous silicon that is substantially controlled to be an intrinsic type by forming a small amount of doping gas.
【００２８】非晶質シリコンなどの非晶質半導体では、
一般に不純物をなんら添加することなく形成した場合で
も、僅かではあるが導電性を顕すことがあるためで、例
えば、非晶質シリコンの場合、僅かなｎ型を示す。本発
明は、真性非晶質半導体として、このような実質的に真
性な非晶質半導体をも使用しうるものである。In an amorphous semiconductor such as amorphous silicon,
In general, even if the film is formed without adding any impurities, it may show a slight conductivity, but for example, amorphous silicon shows a slight n-type. The present invention can also use such a substantially intrinsic amorphous semiconductor as the intrinsic amorphous semiconductor.
【００２９】また、本実施例では、結晶系半導体として
単結晶半導体を例示したが、これに限らず多結晶半導体
を用いてもよいものである。この場合においても、真性
非晶質半導体との間で異種物質界面を形成するが、前述
したように、分子ネットワークが連続的に繋がり易くな
るとともにバンドプロファイルがスムーズに繋がりやす
くなるので、光電変換効率の向上が図れる。また、この
ように結晶系半導体として多結晶シリコン膜を用いる場
合は、真性非晶質シリコン膜２の膜厚としては３５０Å
以下が好適となる。In this embodiment, a single crystal semiconductor is exemplified as the crystalline semiconductor, but the present invention is not limited to this, and a polycrystalline semiconductor may be used. Even in this case, a heterogeneous substance interface is formed with the intrinsic amorphous semiconductor, but as described above, since it is easy to continuously connect the molecular networks and the band profile is easily connected, the photoelectric conversion efficiency is improved. Can be improved. When a polycrystalline silicon film is used as the crystalline semiconductor as described above, the intrinsic amorphous silicon film 2 has a film thickness of 350Å.
The following are suitable.
【００３０】更に、ドープ膜である非晶質半導体と結晶
系半導体とは互いに逆導電型の関係を有すればよいもの
であり、本実施例とは逆に、結晶系半導体をｐ型とし、
非晶質半導体をｎ型とするようにしてもよい。Further, it is sufficient that the amorphous semiconductor which is the doped film and the crystalline semiconductor have a relationship of opposite conductivity type to each other. Contrary to the present embodiment, the crystalline semiconductor is p-type,
The amorphous semiconductor may be n-type.
【００３１】また、本実施例では、Ｆ量は、上記界面側
（裏面側）で対Ｓｉ比０．１％程度としたが、これに限
るものではない。ただし、Ｆ量の対Ｓｉ比は、１％を越
えないのが望ましいと考えられる。Further, in this embodiment, the amount of F is set to about 0.1% of the ratio of Si on the interface side (back side), but the present invention is not limited to this. However, it is considered preferable that the ratio of F content to Si does not exceed 1%.
【００３２】また、本実施例では、真性非晶質シリコン
膜２のプラズマＣＶＤ法による形成で、ＳｉＦ4 の流量
を制御することとしたが、ＳｉＦ4 の流量を均一にし、
膜全体にフッ素を均一に含む真性非晶質シリコン膜２を
成膜した後、この真性非晶質シリコン膜２の光入射側に
含まれているフッ素を水素と交換するＨ2 プラズマ処理
を行うようにしてもよいものである。その他、ＳｉＦ4
を供給しないプラズマＣＶＤ法とＦ2 プラズマ処理とを
組み合わせることにより、フッ素含有量に変化を持たせ
るようにしてもよい。In this embodiment, the flow rate of SiF 4 is controlled by forming the intrinsic amorphous silicon film 2 by the plasma CVD method, but the flow rate of SiF 4 is made uniform.
After forming the intrinsic amorphous silicon film 2 that uniformly contains fluorine on the entire film, H 2 plasma processing is performed to exchange fluorine contained in the light incident side of the intrinsic amorphous silicon film 2 with hydrogen. You can do it. Others, SiF 4
It is also possible to change the fluorine content by combining the plasma CVD method in which no oxygen is supplied with the F 2 plasma treatment.
【００３３】[0033]
【発明の効果】以上のように、本発明によれば、真性非
晶質半導体がフッ素を含有することによりその分子ネッ
トワークは結晶系に近いものとなり、結晶系半導体と真
性非晶質半導体との界面における分子ネットワークの繋
がりは連続的なものに近づく。即ち、従来は上記の界面
にだけかかっていた格子歪みがならされるため、界面準
位密度が低減する。加えて、上記非晶質半導体の裏面側
でのバンドギャップＥｇが結晶系半導体のＥｇに近づく
ため、光電変換効率が向上する。一方、フッ素の含有量
は、非晶質半導体との界面側で少なくされているので、
当該真性非晶質半導体にフッ素が均一に含まれている場
合と比較して高い電圧を得ることが可能となる。As described above, according to the present invention, since the intrinsic amorphous semiconductor contains fluorine, its molecular network becomes close to that of a crystalline system, and the crystalline semiconductor and the intrinsic amorphous semiconductor are separated from each other. The connection of molecular networks at the interface approaches a continuous one. That is, since the lattice strain that has hitherto been applied only to the interface is smoothed, the interface state density is reduced. In addition, since the bandgap Eg on the back surface side of the amorphous semiconductor approaches the Eg of the crystalline semiconductor, the photoelectric conversion efficiency is improved. On the other hand, since the content of fluorine is reduced on the interface side with the amorphous semiconductor,
A higher voltage can be obtained as compared with the case where fluorine is uniformly contained in the intrinsic amorphous semiconductor.
【図１】同図（ａ）は本発明の光起電力装置のバンドプ
ロファイルを示したグラフであり、同図（ｂ）は断面構
造図である。FIG. 1 (a) is a graph showing a band profile of a photovoltaic device of the present invention, and FIG. 1 (b) is a sectional structural view.
【図２】本発明の真性非晶質シリコン膜の成膜するとき
の、経過時間に対する各供給ガスの流量変化を示すグラ
フである。FIG. 2 is a graph showing changes in flow rate of each supply gas with respect to elapsed time when forming an intrinsic amorphous silicon film of the present invention.
【図３】本発明の真性非晶質シリコン膜成膜開始時のＳ
ｉＦ4 ／ＳｉＨ4 流量比を異ならせ、その各々の条件下
で得られた真性非晶質シリコン膜を用いた光起電力装置
の変換効率を示したグラフである。[FIG. 3] S at the start of film formation of the intrinsic amorphous silicon film of the present invention
6 is a graph showing conversion efficiency of photovoltaic devices using intrinsic amorphous silicon films obtained under different conditions of iF 4 / SiH 4 flow rate ratios.
【図４】本発明の光起電力装置と従来のＨＩＴ構造を有
する光起電力装置とにおける、各々の真性非晶質半導体
の膜厚を変化させたときの光電変換効率の変化を示した
グラフである。FIG. 4 is a graph showing a change in photoelectric conversion efficiency when the film thickness of each intrinsic amorphous semiconductor is changed in the photovoltaic device of the present invention and the conventional photovoltaic device having a HIT structure. Is.
【図５】従来のｐｎヘテロ接合を有する光起電力装置の
断面構造およびバンドプロファイルを示す模式図であ
る。FIG. 5 is a schematic diagram showing a cross-sectional structure and a band profile of a conventional photovoltaic device having a pn heterojunction.
【図６】従来のＨＩＴ構造を有する光起電力装置の断面
構造およびバンドプロファイルを示す模式図である。FIG. 6 is a schematic diagram showing a cross-sectional structure and a band profile of a conventional photovoltaic device having a HIT structure.
１ ｎ型単結晶シリコン膜 ２ 真性非晶質シリコン膜 ３ ｐ型非晶質シリコン膜 ４ 電極 ５ 透明電極膜 1 n-type single crystal silicon film 2 intrinsic amorphous silicon film 3 p-type amorphous silicon film 4 electrode 5 transparent electrode film
Claims (1)
導体と結晶系半導体との間に薄膜の真性非晶質半導体を
介在させた光起電力装置において、前記の真性非晶質半
導体は、フッ素を含有し、前記の非晶質半導体との界面
側では結晶系半導体との界面側におけるよりもフッ素含
有量が少なくされていることを特徴とする光起電力装
置。1. A photovoltaic device in which a thin intrinsic amorphous semiconductor is interposed between an amorphous semiconductor and a crystalline semiconductor having mutually opposite conductivity types, wherein the intrinsic amorphous semiconductor is A photovoltaic device comprising fluorine, wherein the content of fluorine on the interface side with the amorphous semiconductor is smaller than that on the interface side with the crystalline semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10500193A JP3197673B2 (en) | 1993-04-06 | 1993-04-06 | Photovoltaic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10500193A JP3197673B2 (en) | 1993-04-06 | 1993-04-06 | Photovoltaic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06291342A true JPH06291342A (en) | 1994-10-18 |
| JP3197673B2 JP3197673B2 (en) | 2001-08-13 |
Family
ID=14395853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10500193A Expired - Lifetime JP3197673B2 (en) | 1993-04-06 | 1993-04-06 | Photovoltaic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3197673B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7030413B2 (en) | 2000-09-05 | 2006-04-18 | Sanyo Electric Co., Ltd. | Photovoltaic device with intrinsic amorphous film at junction, having varied optical band gap through thickness thereof |
| JP2012253335A (en) * | 2011-05-11 | 2012-12-20 | Semiconductor Energy Lab Co Ltd | Photoelectric conversion device and method of manufacturing the same |
| WO2013128628A1 (en) * | 2012-03-02 | 2013-09-06 | 三洋電機株式会社 | Photovoltaic device |
| WO2014155833A1 (en) * | 2013-03-28 | 2014-10-02 | 三洋電機株式会社 | Solar battery |
-
1993
- 1993-04-06 JP JP10500193A patent/JP3197673B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7030413B2 (en) | 2000-09-05 | 2006-04-18 | Sanyo Electric Co., Ltd. | Photovoltaic device with intrinsic amorphous film at junction, having varied optical band gap through thickness thereof |
| JP2012253335A (en) * | 2011-05-11 | 2012-12-20 | Semiconductor Energy Lab Co Ltd | Photoelectric conversion device and method of manufacturing the same |
| WO2013128628A1 (en) * | 2012-03-02 | 2013-09-06 | 三洋電機株式会社 | Photovoltaic device |
| JPWO2013128628A1 (en) * | 2012-03-02 | 2015-07-30 | パナソニックＩｐマネジメント株式会社 | Photovoltaic device |
| US9705022B2 (en) | 2012-03-02 | 2017-07-11 | Panasonic Intellectual Property Management Co., Ltd. | Photovoltaic device |
| WO2014155833A1 (en) * | 2013-03-28 | 2014-10-02 | 三洋電機株式会社 | Solar battery |
| JPWO2014155833A1 (en) * | 2013-03-28 | 2017-02-16 | パナソニックＩｐマネジメント株式会社 | Solar cell |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3197673B2 (en) | 2001-08-13 |
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