JPH06283623A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH06283623A JPH06283623A JP5068657A JP6865793A JPH06283623A JP H06283623 A JPH06283623 A JP H06283623A JP 5068657 A JP5068657 A JP 5068657A JP 6865793 A JP6865793 A JP 6865793A JP H06283623 A JPH06283623 A JP H06283623A
- Authority
- JP
- Japan
- Prior art keywords
- plating layer
- layer
- semiconductor package
- ceramic substrate
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップを搭載す
るためのセラミック基板上に導体パターンを設けてなる
半導体パッケージに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package in which a conductor pattern is provided on a ceramic substrate for mounting a semiconductor chip.
【０００２】[0002]
【従来の技術】従来から、半導体チップを搭載するため
のセラミック基板上に、ワイヤーボンディング用やシー
ルリング接合用の導体パターンを設けてなる半導体パッ
ケージは種々のものが知られている。図２は従来から知
られている半導体パッケージの一例の構成を示す図であ
る。図２に示す例において、１１はセラミック基板、１
２は外部との電気的接続をとるためのピン、１３はセラ
ミック基板１１のキャビティ１４内に設けられた例えば
Ｓｉからなる半導体チップ１５を搭載するのに使用され
るダイパターン、１６は半導体チップ１５とのワイヤー
ボンディングに使用されるセラミック基板１１を介して
ピン１２と電気的に接続されているワイヤーボンディン
グパターン、１７は図示しない封止用キャップを接合す
るためのシールパターンである。2. Description of the Related Art Conventionally, various types of semiconductor packages have been known in which a conductor pattern for wire bonding or seal ring bonding is provided on a ceramic substrate for mounting a semiconductor chip. FIG. 2 is a diagram showing an example of the configuration of a conventionally known semiconductor package. In the example shown in FIG. 2, 11 is a ceramic substrate, 1
Reference numeral 2 is a pin for making an electrical connection to the outside, 13 is a die pattern used for mounting a semiconductor chip 15 made of, for example, Si, which is provided in the cavity 14 of the ceramic substrate 11, and 16 is a semiconductor chip 15 The wire bonding pattern 17 is electrically connected to the pin 12 through the ceramic substrate 11 used for wire bonding with, and 17 is a seal pattern for bonding a sealing cap (not shown).
【０００３】上述した従来の半導体パッケージの構成の
うち、ダイパターン１３、ワイヤーボンディングパター
ン１６およびシールパターン１７の導体パターンの材料
としては、電気的特性の良好なＡｕを使用することが好
ましいが、全体をＡｕだけで構成するとコストが高くな
る問題があった。この問題を解決するため、例えば図３
に示す導体パターンの膜構成が特公昭６０−１３０７８
号公報において開示されている。Of the above-mentioned conventional semiconductor package constructions, it is preferable to use Au, which has good electrical characteristics, as the material for the conductor patterns of the die pattern 13, the wire bonding pattern 16 and the seal pattern 17, but the whole structure is preferable. However, there is a problem in that the cost increases if the is composed of only Au. In order to solve this problem, for example, FIG.
The film structure of the conductor pattern shown in FIG.
Japanese Patent Publication No.
【０００４】図３に示す導体パターンは、セラミック基
板１１上に設けたＷまたはＭｏからなるメタライズ層２
１と、このメタライズ層２１の上に設けたＮｉ−Ｃｏ合
金からなるＮｉめっき層２２と、このＮｉめっき層２２
の上に設けたＡｕめっき層２３とからなる構成を有して
おり、Ａｕの良好な電気的特性を保ちつつ高価なＡｕの
使用量を減少することができる。The conductor pattern shown in FIG. 3 has a metallized layer 2 made of W or Mo provided on a ceramic substrate 11.
1, a Ni plating layer 22 made of a Ni—Co alloy provided on the metallized layer 21, and the Ni plating layer 22.
The Au plating layer 23 is provided on the top surface of the Au plating layer 23, and the amount of expensive Au used can be reduced while maintaining good electrical characteristics of Au.
【０００５】[0005]
【発明が解決しようとする課題】近年になって、半導体
チップ１５のセラミック基板１１に設けたキャビティ１
４内への固定を、上述したＡｕを使用したダイパターン
１３を使用せずに、Ａｇガラスを使用して半導体チップ
１５を直接キャビティ１４内へ固定することが行われて
いる。図４はこのような半導体パッケージの一例の構成
を示す図であり、２４がダイパターンの代わりに使用さ
れるＡｇガラス接着層、２５が樹脂によるダイコート層
である。In recent years, the cavity 1 provided in the ceramic substrate 11 of the semiconductor chip 15 has been improved.
The semiconductor chip 15 is directly fixed in the cavity 14 by using Ag glass without fixing the die pattern 13 using Au described above. FIG. 4 is a diagram showing a configuration of an example of such a semiconductor package, in which 24 is an Ag glass adhesive layer used in place of the die pattern, and 25 is a resin die coat layer.
【０００６】このようなＡｇガラスを使用して半導体チ
ップを固定した半導体パッケージを製造するには、まず
キャビティ１４内にＡｇガラス接着層２４を介して半導
体チップ１５をセットし、乾燥空気中で４５０℃×２０
分の熱処理を行いチップ付けをして、ワイヤーボンディ
ングを行った後、樹脂を窒素雰囲気中で４５０℃×６０
分の熱処理することによりダイコート層２５を設け、さ
らにキャップシールを行う必要があった。In order to manufacture a semiconductor package in which a semiconductor chip is fixed using such Ag glass, first, the semiconductor chip 15 is set in the cavity 14 via the Ag glass adhesive layer 24, and then 450 in dry air. ℃ × 20
After heat treatment for minutes, chips are attached, and wire bonding is performed. Then, the resin is heated in a nitrogen atmosphere at 450 ° C. × 60.
It was necessary to form the die coat layer 25 by performing heat treatment for a minute, and further perform cap sealing.
【０００７】そのため、従来のダイパターン１３による
半導体チップの固定の場合と比較して、導体パターンが
高温に曝され、ワイヤーボンディングパターン１６およ
びシールパターン１７等の導体パターンの表面のＡｕめ
っき層が酸化により変色し、ボンディング性やシール性
が劣化する問題があった。この問題を解決するため、従
来２μｍであったＡｕめっき層２３の厚さを３．５μｍ
にすることが考えられるが、高価なＡｕを多量に使用し
なければならないため、コストが上昇してしまう問題が
あった。Therefore, as compared with the case of fixing the semiconductor chip by the conventional die pattern 13, the conductor pattern is exposed to high temperature, and the Au plating layer on the surface of the conductor pattern such as the wire bonding pattern 16 and the seal pattern 17 is oxidized. However, there is a problem in that the color changes due to the above, and the bonding property and sealing property deteriorate. In order to solve this problem, the thickness of the Au plating layer 23, which was 2 μm in the past, is 3.5 μm.
However, there is a problem in that the cost increases because a large amount of expensive Au must be used.
【０００８】本発明の目的は上述した課題を解消して、
Ａｕめっき層の厚さを厚くすることなく高温での熱処理
にも耐える導体パターンを有する半導体パッケージを提
供しようとするものである。The object of the present invention is to solve the above problems,
An object of the present invention is to provide a semiconductor package having a conductor pattern that can withstand heat treatment at high temperature without increasing the thickness of the Au plating layer.
【０００９】[0009]
【課題を解決するための手段】本発明の半導体パッケー
ジは、セラミック基板上に設けた導体パターンの膜構成
が、前記セラミック基板上に設けたＷまたはＭｏからな
るメタライズ層と、このメタライズ層上に設けたＮｉ−
Ｗ合金からなるＮｉめっき層と、このＮｉめっき層上に
設けたＡｕめっき層とからなることを特徴とするもので
ある。In the semiconductor package of the present invention, the film structure of the conductor pattern provided on the ceramic substrate has a metallized layer made of W or Mo provided on the ceramic substrate, and a metallized layer formed on the metallized layer. Ni-provided
It is characterized by comprising a Ni plating layer made of a W alloy and an Au plating layer provided on the Ni plating layer.
【００１０】また、本発明の半導体パッケージは、セラ
ミック基板上に設けた導体パターンの膜構成が、前記セ
ラミック基板上に設けたＷまたはＭｏからなるメタライ
ズ層と、このメタライズ層上に設けたＮｉ−Ｐｄ合金か
らなるＮｉめっき層と、このＮｉめっき層上に設けたＡ
ｕめっき層とからなることを特徴とするものである。Further, in the semiconductor package of the present invention, the film structure of the conductor pattern provided on the ceramic substrate is a metallized layer made of W or Mo provided on the ceramic substrate, and a Ni-layer provided on the metallized layer. Ni plating layer made of Pd alloy and A provided on this Ni plating layer
It is characterized by comprising a u plating layer.
【００１１】[0011]
【作用】上述した構成において、セラミック基板と接す
るＷまたはＭｏからなるメタライズ層と最上層のＡｕめ
っき層との間に設けたＮｉ−Ｗ合金またはＮｉ−Ｐｄ合
金からなるＮｉめっき層が、ＮｉめっきのＡｕめっき表
層への熱拡散を防止して、Ａｕめっき層の変色を防止
し、Ａｕめっき層の厚さを厚くすることなく高温での熱
処理にも耐えることができる。In the above structure, the Ni plating layer made of Ni-W alloy or Ni-Pd alloy provided between the metallization layer made of W or Mo and the uppermost Au plating layer in contact with the ceramic substrate is the Ni plating layer. It is possible to prevent heat diffusion to the Au plating surface layer, prevent discoloration of the Au plating layer, and withstand heat treatment at high temperature without increasing the thickness of the Au plating layer.
【００１２】[0012]
【実施例】図１は本発明の半導体パッケージにおける導
体パターンの膜構成の一例を示す図であり、図４に示す
半導体パッケージのワイヤバンディングパターン１６お
よびシールパターン１７を図１に示す膜構成とした以外
は、本発明の半導体パッケージの構成は図４に示す例と
同様である。図１に示す例において、本発明の半導体パ
ッケージにおける導体パターンは、セラミック基板１上
に設けたＷまたはＭｏからなるメタライズ層２と、この
メタライズ層２の上に設けたＮｉ−Ｗ合金またはＮｉ−
Ｐｄ合金からなるＮｉめっき層３と、このＮｉめっき層
３の上に設けたＡｕめっき層４とからなる構成を有して
いる。1 is a view showing an example of a film structure of a conductor pattern in a semiconductor package of the present invention, and the wire banding pattern 16 and the seal pattern 17 of the semiconductor package shown in FIG. 4 have the film structure shown in FIG. Other than that, the configuration of the semiconductor package of the present invention is the same as the example shown in FIG. In the example shown in FIG. 1, the conductor pattern in the semiconductor package of the present invention has a metallized layer 2 made of W or Mo provided on the ceramic substrate 1 and a Ni-W alloy or Ni-made provided on the metallized layer 2.
The Ni plating layer 3 is made of a Pd alloy, and the Au plating layer 4 is provided on the Ni plating layer 3.
【００１３】上述した本発明の膜構成では、Ｎｉめっき
層３中のＷまたはＰｄがＮｉめっき層３中のＮｉのＡｕ
めっき層２中への熱拡散を防止するため、これらの組成
がＮｉめっき層３中に存在すれば本発明を達成できる
が、Ｎｉ−Ｗ合金の場合は、Ｗ：５〜９０ｗｔ％、Ｎｉ
の合金：残部の組成が好ましく、Ｗ：１０〜７０ｗｔ
％、Ｎｉの合金：残部の組成が更に好ましく、Ｎｉ−Ｐ
ｄ合金の場合は、Ｐｄ：４０〜９０ｗｔ％、Ｎｉの合
金：残部の組成が好ましく、Ｐｄ：６０〜８０ｗｔ％、
Ｎｉ：の合金残部の組成が更に好ましい。残部の組成に
はＦｅ，Ｃｏ等の不純物元素等を含むＮｉの合金を含
む。In the above-mentioned film structure of the present invention, W or Pd in the Ni plating layer 3 is Au of Ni in the Ni plating layer 3.
The present invention can be achieved if these compositions are present in the Ni plating layer 3 in order to prevent thermal diffusion into the plating layer 2, but in the case of Ni-W alloy, W: 5 to 90 wt%, Ni
Alloy: the balance is preferably composition, W: 10 to 70 wt
%, Ni alloy: The balance composition is more preferable, and Ni-P
In the case of the d alloy, the composition of Pd: 40 to 90 wt% and Ni alloy: balance is preferable, and Pd: 60 to 80 wt%,
The composition of the balance of Ni: alloy is more preferable. The composition of the balance includes a Ni alloy containing an impurity element such as Fe and Co.
【００１４】ここで、Ｎｉ−Ｗ合金の場合にＷ：５〜９
０ｗｔ％が好ましいのは、Ｗが５ｗｔ％未満であると耐
熱性が不良でＮｉのＡｕ中への拡散防止効果が小となる
場合があるとともに、Ｗが９０ｗｔ％を超えると耐食性
が劣化するためである。また、Ｎｉ−Ｐｄ合金の場合に
Ｐｄ：４０〜９０ｗｔ％が好ましいのは、Ｐｄが４０ｗ
ｔ％未満であると耐熱性が不良でＮｉのＡｕ中への拡散
防止効果が小となる場合があるとともに、Ｐｄが９０ｗ
ｔ％を超えるとＰｄが高価なためやはりコスト増となる
ためである。In the case of Ni-W alloy, W: 5-9
0 wt% is preferable because if W is less than 5 wt%, the heat resistance may be poor and the effect of preventing Ni from diffusing into Au may be small, and if W exceeds 90 wt%, corrosion resistance may deteriorate. Is. Further, in the case of Ni-Pd alloy, Pd: 40 to 90 wt% is preferable because Pd is 40 w.
If it is less than t%, the heat resistance may be poor and the effect of preventing Ni from diffusing into Au may be small, and the Pd may be 90 w.
This is because if t% is exceeded, Pd is expensive and the cost also increases.
【００１５】以下、実際の例について説明する。 実施例１ 半導体パッケージの耐熱性を評価するため、図４に示す
構造の２５６ピンピングリッドアレイタイプのアルミナ
セラミック基板からなる半導体パッケージを準備した。
ワイヤーボンディングパターンおよびシールパターンの
導体パターンの構成は、セラミック基板上にタングステ
ンメタライズ層を施し、このタングステンメタライズ層
上に以下の表１に示す組成の本発明例および比較例のＮ
ｉめっき層を２．０μm 施し、水素雰囲気中で熱処理し
た。次に、熱処理後のＮｉめっき層上に表１に示す厚さ
のＡｕめっき層を施して半導体パッケージを得た。An actual example will be described below. Example 1 In order to evaluate the heat resistance of the semiconductor package, a semiconductor package made of a 256-pin pin grid array type alumina ceramic substrate having the structure shown in FIG. 4 was prepared.
The conductor patterns of the wire bonding pattern and the seal pattern were formed by forming a tungsten metallization layer on a ceramic substrate, and forming the tungsten metallization layer on the tungsten metallization layer with N of the present invention example and the comparative example having the compositions shown in Table 1 below.
An i-plated layer was applied to a thickness of 2.0 μm and heat-treated in a hydrogen atmosphere. Next, an Au plating layer having a thickness shown in Table 1 was applied on the Ni plating layer after the heat treatment to obtain a semiconductor package.
【００１６】その後、得られた半導体パッケージに対し
て耐熱性を評価した。耐熱性の評価は、得られた半導体
パッケージに対し、第１ステップとして乾燥空気中で４
５０℃×２０分の熱処理を行い、第２ステップとして窒
素雰囲気中で４５０℃×６０分の熱処理を行い、その後
Ａｕめっき層表面のＮｉ拡散量（ｗｔ％）をＸ線マイク
ロアナライザー（ＸＭＡ）にて分析して求めた。結果を
表１に示す。Thereafter, the heat resistance of the obtained semiconductor package was evaluated. The heat resistance was evaluated in dry air as a first step for the obtained semiconductor package.
Heat treatment is performed at 50 ° C. for 20 minutes, and as the second step, heat treatment is performed at 450 ° C. for 60 minutes in a nitrogen atmosphere, and then the Ni diffusion amount (wt%) on the surface of the Au plating layer is measured by an X-ray microanalyzer (XMA). I analyzed and asked. The results are shown in Table 1.
【００１７】[0017]
【表１】 [Table 1]
【００１８】表１の結果から、本発明例のＷを含むＮｉ
めっき層を使用したものは、比較例のＷを含まないＮｉ
めっき層を使用したものと比較して、ワイヤーボンディ
ングパターンおよびシールパターンの両者とも耐熱性が
良好で、高温の熱処理にも耐えることがわかった。ま
た、本発明例のなかでも、Ｗを５〜９０ｗｔ％含むＮｉ
めっき層がそれ以外のＷ量のＮｉめっき層と比べて、耐
熱性がさらに良好であることがわかった。From the results of Table 1, Ni containing W of the present invention example
The one using the plated layer is a Ni containing no W of the comparative example.
It was found that both the wire bonding pattern and the seal pattern had better heat resistance than the one using the plated layer and could withstand high temperature heat treatment. In addition, among the examples of the present invention, Ni containing 5 to 90 wt% of W is used.
It was found that the plating layer had better heat resistance than the Ni plating layers having other W amounts.
【００１９】実施例２ Ｎｉめっき層としてＮｉ−Ｐｄ合金を使用した以外は実
施例１と同様にして半導体パッケージを作製し、得られ
た半導体パッケージに対して実施例１と同様にして耐熱
性を評価した。結果を表２に示す。Example 2 A semiconductor package was produced in the same manner as in Example 1 except that a Ni-Pd alloy was used as the Ni plating layer, and the obtained semiconductor package was subjected to heat resistance in the same manner as in Example 1. evaluated. The results are shown in Table 2.
【００２０】[0020]
【表２】 [Table 2]
【００２１】表２の結果からも、本発明例のＰｄを含む
Ｎｉめっき層を使用したものは、ワイヤーボンディング
パターンおよびシールパターンの両者とも耐熱性が良好
で、高温の熱処理にも耐えることがわかった。また、本
発明例のなかでも、Ｐｄを４０〜９０ｗｔ％含むＮｉめ
っき層がそれ以外のＰｄ量のＮｉめっき層と比べて、耐
熱性がさらに良好であることがわかった。The results in Table 2 also show that the one using the Ni plating layer containing Pd of the present invention has good heat resistance in both the wire bonding pattern and the seal pattern and can withstand high temperature heat treatment. It was In addition, it was found that among the examples of the present invention, the Ni plating layer containing 40 to 90 wt% of Pd had further better heat resistance than the Ni plating layer having the other amount of Pd.
【００２２】[0022]
【発明の効果】以上の説明から明らかなように、本発明
によれば、セラミック基板と接するＷまたはＭｏからな
るメタライズ層と最上層のＡｕめっき層との間にＮｉ−
Ｗ合金またはＮｉ−Ｐｄ合金からなるＮｉめっき層を設
けたため、ＮｉめっきのＡｕめっき表層への熱拡散を防
止して、Ａｕめっき層の変色を防止し、Ａｕめっき層の
厚さを厚くすることなく高温での熱処理にも耐えること
ができる。As is apparent from the above description, according to the present invention, a Ni- layer is formed between the metallized layer of W or Mo that is in contact with the ceramic substrate and the uppermost Au plated layer.
Since the Ni plating layer made of W alloy or Ni-Pd alloy is provided, it is possible to prevent thermal diffusion of the Ni plating to the Au plating surface layer, prevent discoloration of the Au plating layer, and increase the thickness of the Au plating layer. It can also withstand high temperature heat treatment.
【図１】本発明の半導体パッケージにおける導体パター
ンの膜構造の一例の構成を示す図である。FIG. 1 is a diagram showing a configuration of an example of a film structure of a conductor pattern in a semiconductor package of the present invention.
【図２】従来の半導体パッケージの一例の構成を示す図
である。FIG. 2 is a diagram showing a configuration of an example of a conventional semiconductor package.
【図３】従来の半導体パッケージにおける導体パターン
の膜構造の一例の構成を示す図である。FIG. 3 is a diagram showing a configuration of an example of a film structure of a conductor pattern in a conventional semiconductor package.
【図４】従来の半導体パッケージの他の例の構成を示す
図である。FIG. 4 is a diagram showing a configuration of another example of a conventional semiconductor package.
１ セラミック基板 ２ メタライズ層 ３ Ｎｉめっき層 ４ Ａｕめっき層 1 Ceramic Substrate 2 Metallization Layer 3 Ni Plating Layer 4 Au Plating Layer
Claims (2)
の膜構成が、前記セラミック基板上に設けたＷまたはＭ
ｏからなるメタライズ層と、このメタライズ層上に設け
たＮｉ−Ｗ合金からなるＮｉめっき層と、このＮｉめっ
き層上に設けたＡｕめっき層とからなることを特徴とす
る半導体パッケージ。1. A film structure of a conductor pattern provided on a ceramic substrate is W or M provided on the ceramic substrate.
A semiconductor package comprising a metallized layer made of o, a Ni plated layer made of a Ni-W alloy provided on the metallized layer, and an Au plated layer provided on the Ni plated layer.
の膜構成が、前記セラミック基板上に設けたＷまたはＭ
ｏからなるメタライズ層と、このメタライズ層上に設け
たＮｉ−Ｐｄ合金からなるＮｉめっき層と、このＮｉめ
っき層上に設けたＡｕめっき層とからなることを特徴と
する半導体パッケージ。2. The film structure of a conductor pattern provided on a ceramic substrate is W or M provided on the ceramic substrate.
A semiconductor package comprising a metallized layer made of o, a Ni plated layer made of a Ni-Pd alloy provided on the metallized layer, and an Au plated layer provided on the Ni plated layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5068657A JPH06283623A (en) | 1993-03-26 | 1993-03-26 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5068657A JPH06283623A (en) | 1993-03-26 | 1993-03-26 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06283623A true JPH06283623A (en) | 1994-10-07 |
Family
ID=13379998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5068657A Pending JPH06283623A (en) | 1993-03-26 | 1993-03-26 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06283623A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0878472A (en) * | 1994-09-05 | 1996-03-22 | Hitachi Cable Ltd | Semiconductor device and base body therefor |
| US6486551B1 (en) | 1998-01-28 | 2002-11-26 | Ngk Spark Plug Co., Ltd. | Wired board and method of producing the same |
| US7781849B2 (en) * | 2008-01-29 | 2010-08-24 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
| CN102197155A (en) * | 2009-04-17 | 2011-09-21 | 吉坤日矿日石金属株式会社 | Barrier film for semiconductor wiring, sintered sputtering target, and method of manufacturing sputtering targets |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56167339A (en) * | 1980-05-26 | 1981-12-23 | Takehiko Yasuda | Electronic parts equipped with gold conductive layer |
-
1993
- 1993-03-26 JP JP5068657A patent/JPH06283623A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56167339A (en) * | 1980-05-26 | 1981-12-23 | Takehiko Yasuda | Electronic parts equipped with gold conductive layer |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0878472A (en) * | 1994-09-05 | 1996-03-22 | Hitachi Cable Ltd | Semiconductor device and base body therefor |
| US6486551B1 (en) | 1998-01-28 | 2002-11-26 | Ngk Spark Plug Co., Ltd. | Wired board and method of producing the same |
| US7781849B2 (en) * | 2008-01-29 | 2010-08-24 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
| CN102197155A (en) * | 2009-04-17 | 2011-09-21 | 吉坤日矿日石金属株式会社 | Barrier film for semiconductor wiring, sintered sputtering target, and method of manufacturing sputtering targets |
| US9051645B2 (en) | 2009-04-17 | 2015-06-09 | Jx Nippon Mining & Metals Corporation | Barrier film for semiconductor wiring, sintered compact sputtering target and method of producing the sputtering target |
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