JPH06282596A - Parallel circuit simulation system - Google Patents
Parallel circuit simulation systemInfo
- Publication number
- JPH06282596A JPH06282596A JP4044710A JP4471092A JPH06282596A JP H06282596 A JPH06282596 A JP H06282596A JP 4044710 A JP4044710 A JP 4044710A JP 4471092 A JP4471092 A JP 4471092A JP H06282596 A JPH06282596 A JP H06282596A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- parallel
- row
- network equation
- processors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は並列回路シミュレーショ
ン方式に関し、特にＬＳＩの電子回路シミュレーション
でマルチＣＰＵ下での並列シミュレーションに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel circuit simulation system, and more particularly to an electronic circuit simulation of an LSI, which is a parallel simulation under multiple CPUs.
【０００２】[0002]
【従来の技術】ＬＳＩの電子回路シミュレーションは、
大規模かつＣＰＵ依存度の高い計算機処理のうちのひと
つであり、計算コストの低減と処理の速応性の改善とを
目的として種々の改良方式が発明されている。その一例
として、特願昭６１−０２６２９３号に記載されている
マルチＣＰＵ下での並列処理方式がある。当方式を簡単
な具体例図１で示す。2. Description of the Related Art An electronic circuit simulation of an LSI is
This is one of the large-scale and highly CPU-dependent computer processes, and various improved methods have been invented for the purpose of reducing the calculation cost and improving the process responsiveness. As an example thereof, there is a parallel processing system under multi CPU described in Japanese Patent Application No. 61-026293. This method is shown in FIG.
【０００３】図１は、部分回路５，６、部分回路間の結
合回路網７から構成される回路である。結合回路網７
は、節点１，２，３，４により構成される。図１の回路
を３つのプロセッサで処理するとし、それぞれに部分回
路５，６、結合回路網７を割り当てるとする。先ずプロ
セッサ５，６はそれぞれ部分回路５，６について、外部
変数に関する等価モデル［数１］，［数２］を並列に生
成する。ここで外部変数は結合回路網７を構成する節点
の電位を独立変数とし、当節点から各部分回路に流入す
る電流を従属変数とする。FIG. 1 shows a circuit composed of partial circuits 5 and 6 and a coupling circuit network 7 between the partial circuits. Coupling network 7
Is composed of nodes 1, 2, 3, and 4. It is assumed that the circuit of FIG. 1 is processed by three processors, and the partial circuits 5 and 6 and the coupling network 7 are assigned to each. First, the processors 5 and 6 generate equivalent models [Equation 1] and [Equation 2] for external variables in parallel for the partial circuits 5 and 6, respectively. Here, the external variable is a potential of a node forming the coupling network 7 as an independent variable, and a current flowing into each partial circuit from this node as a dependent variable.
【０００４】[0004]
【表１】 [Table 1]
【０００５】ここで ｉ1 5 ，ｉ2 5 ，ｉ3 5 ，ｉ4 5 ：結合回路網７の節点
１，２，３，４から部分回路５へ流入する電流 Δｖ1 ，Δｖ2 ，Δｖ3 ，Δｖ4 ：結合回路網７の節点
１，２，３，４の電位のニュートン反復差分 ｊ1 5 ，ｊ2 5 ，ｊ3 5 ，ｊ4 5 ：結合回路網７の節点
１，２，３，４から部分回路５へ流入する電流の残差 Ｇ5 ：結合回路網７の節点
１，２，３，４から眺めた部分回路５の等価コンダクタ
ンス行列 ［数２］の各変数に対しても同様の意味を持つ。プロセ
ッサ５，６は部分回路５，６の上記等価モデルをプロセ
ッサ７に転送する。そしてプロセッサ７は結合回路網方
程式［数３］を構成し、これを求解する。[0005] Here, i 1 5, i 2 5, i 3 5, i 4 5: Current Delta] v 1 flowing from the node 1, 2, 3, 4 of the coupling network 7 to the partial circuit 5, Δv 2, Δv 3 , Delta] v 4: Newton iteration difference j 1 5 in the potential of the node 1, 2, 3, 4 of the coupling network 7, j 2 5, j 3 5, j 4 5: node 1, 2 and 3 coupling network 7 , 4 the residual of the current flowing into the partial circuit 5 G 5 : For each variable of the equivalent conductance matrix [Equation 2] of the partial circuit 5 viewed from the nodes 1, 2, 3, 4 of the coupling network 7. Have the same meaning. The processors 5 and 6 transfer the equivalent model of the partial circuits 5 and 6 to the processor 7. Then, the processor 7 forms a coupled network equation [Equation 3] and solves it.
【０００６】[0006]
【表２】 [Table 2]
【０００７】[0007]
【発明が解決しようとする課題】部分回路の等価モデル
を生成するプロセスは、部分回路の回路シミュレーショ
ンを包含する。従ってこの従来技術に従えば、分割され
た部分回路は全て並列にシミュレーション可能となる。
一方結合回路網方程式［数３］は、従来逐次処理即ち単
一プロセッサによって演算されている。この演算量は、
部分回路の数、即ちプロセッサの数とともに増加する。
特に［数３］の等価コンダクタンス行列Ｇ5 ＋Ｇ6 が密
行列であれば、次数の３剰に比例して演算量が増加す
る。従ってプロセッサ数が数十台規模以上の並列シミュ
レーションにおいては、当結合回路網方程式の演算量が
並列度のさまたげになるという大きな課題を有してい
た。The process of generating an equivalent model of a partial circuit involves circuit simulation of the partial circuit. Therefore, according to this conventional technique, all the divided partial circuits can be simulated in parallel.
On the other hand, the coupled network equation [Equation 3] is conventionally calculated by a sequential process, that is, a single processor. This calculation amount is
It increases with the number of subcircuits, that is, the number of processors.
In particular, if the equivalent conductance matrix G 5 + G 6 of [Equation 3] is a dense matrix, the amount of calculation increases in proportion to the third residue. Therefore, in the parallel simulation in which the number of processors is several tens or more, there is a big problem that the calculation amount of the coupled network equation impedes the parallelism.
【０００８】[0008]
【課題を解決するための手段】本発明の並列回路シミュ
レーション方式は、結合回路網方程式の行列構造を各プ
ロセッサがそれぞれ独自に記憶する機構と、結合回路網
方程式の行ベクトルあるいは行ベクトル群からなるロー
カルな行列構造を各プロセッサが分散し記憶する機構
と、各プロセッサは外部変数に関する部分回路の等価モ
デルを並列に生成した後に同等価モデル要素を行ベクト
ル単位で、その行に対応する結合回路網方程式の行ベク
トル演算を割り当てられたプロセッサに転送し該プロセ
ッサは結合回路網方程式のローカルな行列要素を合成す
る機構と、以上の機構の下にピボット行を割り当てられ
たプロセッサが同行ベクトルを他のプロセッサに転送
し、これをピボット順に繰り返し、結合回路網方程式の
行列演算を行ベクトル単位で並列に実行する機構とから
なる。A parallel circuit simulation method according to the present invention comprises a mechanism for each processor to independently store the matrix structure of a coupled network equation and a row vector or a row vector group of the coupled network equation. A mechanism in which each processor distributes and stores a local matrix structure, and each processor generates an equivalent model of a partial circuit related to an external variable in parallel, and then the equivalent model element is connected in a row vector unit to the connected network corresponding to that row. A mechanism for transferring the row vector operation of the equation to the assigned processor, and the processor synthesizing the local matrix elements of the coupled network equation, and the processor assigned the pivot row under the above mechanism, the same row vector to another processor Transfer to the processor, repeat this in the pivot order, and perform matrix operation of the coupled network equations as row vector Consisting of a mechanism to be executed in parallel in place.
【０００９】[0009]
【実施例】本発明について図２を用いて説明する。回路
例は図１と同一であり、また使用するプロセッサも同様
に３台とした。そのうちの２台は、２つの部分回路のシ
ミュレーションに割り当てるとし、３台を本発明の結合
回路網方程式の並列処理に割り当てるものとする。全体
のシミュレーション機構から、結合回路網方程式の並列
処理用プロセッサと、部分回路のシミュレーション用プ
ロセッサは共用可能である。先ずプロセッサ８，９，１
０は結合回路網方程式の行列構造１３をそれぞれ独自に
記憶する。またプロセッサ８は、結合回路網方程式の
，の行ベクトルからなるローカルな行列構造１７
を、プロセッサ９は同の行ベクトルのローカルな行列
構造１８を、プロセッサ１０は同の行ベクトルのロー
カルな行列構造１９をそれぞれ記憶する。プロセッサ８
のように複数の行ベクトルを割り当てる場合には可能な
限り離れた行番号を割り当てる方が並列効果が高くな
る。何故なら、行列演算は１行１列から昇順にピボット
が選ばれること、行列のスペース処理が施こされている
ので、ピボットの昇順に行列が密になって行くこと等の
理由によりこのようにした方が並列負荷バランスが良く
なるからである。EXAMPLE The present invention will be described with reference to FIG. The circuit example is the same as that of FIG. 1, and the number of processors used is also three. Two of them are assigned to the simulation of two partial circuits, and three are assigned to the parallel processing of the coupled network equation of the present invention. From the overall simulation mechanism, the processor for parallel processing of coupled network equations and the processor for simulation of partial circuits can be shared. First, the processor 8, 9, 1
0 independently stores the matrix structure 13 of the coupled network equation. Further, the processor 8 has a local matrix structure 17 consisting of row vectors of
The processor 9 stores the local matrix structure 18 of the same row vector, and the processor 10 stores the local matrix structure 19 of the same row vector. Processor 8
When allocating a plurality of row vectors as described above, it is more effective to allocate row numbers as far apart as possible. This is because, in the matrix calculation, the pivots are selected in ascending order from the 1st row and the 1st column, and since the space processing of the matrix is performed, the matrix becomes dense in the ascending order of the pivots. This is because the parallel load balance becomes better when this is done.
【００１０】第１にプロセッサ５，６は部分回路５，６
に対して、外部変数に関する等価モデル１１，１２を並
列に生成する。そしてプロセッサ５，６は等価モデル１
１，１２の要素のうち、，行ベクトルをプロセッサ
８に、行ベクトルをプロセッサ９に、行ベクトルを
プロセッサ１０に転送する。第２にプロセッサ８，９，
１０は、それぞれ結合回路網方程式のローカルな行列要
素２０，２１，２２を並列に合成する。以上が終了する
と、プロセッサ８，９，１０は同期を取り次に進む。First, the processors 5 and 6 are partial circuits 5 and 6.
On the other hand, the equivalent models 11 and 12 regarding external variables are generated in parallel. The processors 5 and 6 are equivalent models 1.
Of the elements 1 and 12, the row vector is transferred to the processor 8, the row vector is transferred to the processor 9, and the row vector is transferred to the processor 10. Secondly, the processors 8, 9,
Reference numeral 10 synthesizes local matrix elements 20, 21, 22 of the coupled network equation in parallel. When the above is completed, the processors 8, 9 and 10 synchronize and proceed to the next step.
【００１１】先ずピボットが選ばれる。そこでプロセ
ッサ８は結合回路網方程式のローカルな行列要素２０の
ピボット行をプロセッサ９，１０のバッファ１５，１
６にコピーする。次にプロセッサ８は、結合回路網方程
式のローカルな行列要素２０の行ベクトルのＬＵ分解
を行なう。その際ピボット行並びに行ベクトルの行
列構造は１７により知られる。プロセッサ９は結合回路
網方程式のローカルな行列要素２１の２行ベクトルのＬ
Ｕ分解を行なう。その際ピボット行のバッファ１５の
行列構造は１３により、又行ベクトルの行列構造は１
８により知られる。プロセッサ１０の処理は前記プロセ
ッサ９と同型である。プロセッサ８，９，１０の処理は
並列に実行可能である。First, the pivot is selected. Therefore, the processor 8 transfers the pivot row of the local matrix element 20 of the coupled network equation to the buffers 15 and 1 of the processors 9 and 10.
Copy to 6. Next, the processor 8 performs LU decomposition of the row vector of the local matrix element 20 of the coupled network equation. The pivot row as well as the row-vector matrix structure are known from 17. The processor 9 uses the two-row vector L of the local matrix element 21 of the coupled network equation.
Perform U decomposition. At that time, the matrix structure of the buffer 15 of the pivot row is 13 and the matrix structure of the row vector is 1.
Known by 8. The processing of the processor 10 is the same as that of the processor 9. The processes of the processors 8, 9 and 10 can be executed in parallel.
【００１２】以上をピボットの昇順に繰り返すことで結
合回路網方程式の行列演算を並列に処理する。By repeating the above in ascending order of the pivots, the matrix operation of the coupled network equation is processed in parallel.
【００１３】図３は、１６ＭＤＲＡＭの回路シミュレー
ションに本発明を適用した結果である。適用回路は６８
７３個のＭＯＳトランジスタ、１１８０個の配線素子、
３８３１の節点数から構成されている。プロセッサ数は
１台から６４台までを使用し評価した。図３の２３は理
想的な並列度を、２４は本発明の並列度を２５は従来技
術の並列度を示す。本発明は従来技術に比較し、高い並
列度を得ている。FIG. 3 shows a result of applying the present invention to a circuit simulation of 16M DRAM. The applicable circuit is 68
73 MOS transistors, 1180 wiring elements,
It is composed of 3831 nodes. The number of processors was evaluated from 1 to 64. In FIG. 3, reference numeral 23 indicates an ideal parallelism degree, 24 indicates the parallelism degree of the present invention, and 25 indicates the parallelism degree of the prior art. The present invention achieves a high degree of parallelism as compared with the prior art.
【００１４】[0014]
【発明の効果】以上説明したように回路分割に基づく並
列回路シミュレーションにおいて、結合回路網方程式の
演算を並列化したので、数十個の部分回路からなる回路
シミュレーションにおいても高い並列度が得られるとい
う効果を有する。As described above, in the parallel circuit simulation based on the circuit division, since the operation of the coupled network equation is parallelized, a high degree of parallelism can be obtained even in the circuit simulation composed of several tens of partial circuits. Have an effect.
【図１】従来技術の回路分割に基づく並列回路シミュレ
ーションの概念図。FIG. 1 is a conceptual diagram of parallel circuit simulation based on circuit division according to the related art.
【図２】本発明を併用した回路分割に基づく並列回路シ
ミュレーションの概念図。FIG. 2 is a conceptual diagram of parallel circuit simulation based on circuit division using the present invention together.
【図３】本発明を１６ＭＤＲＡＭの回路シミュレーショ
ンに適用した評価結果を示すグラフ。FIG. 3 is a graph showing evaluation results when the present invention is applied to circuit simulation of 16M DRAM.
１〜４ 結合回路網の節点 ５，６ 部分回路 ７ 結合回路網 ８〜１０ 結合回路網方程式を並列処理するプロセッ
サ １１，１２ 部分回路の等価モデル １３ 結合回路網方程式の行列構造 １４〜１６ ピボット行のバッファ １７〜１９ 結合回路網方程式のローカルな行列構造 ２０〜２２ 結合回路網方程式のローカルな行列要素 ２３ 理想並列度 ２４ 本発明を１６ＭＤＲＡＭの回路シミュレーショ
ンに適用したときの並列度 ２５ 同上従来技術の並列度1 to 4 nodes of a connection network 5,6 partial circuits 7 connection networks 8 to 10 processors for parallel processing of connection network equations 11 and 12 equivalent models of partial circuits 13 matrix structure of connection network equations 14 to 16 pivot rows Buffer 17 to 19 Local matrix structure of coupled network equation 20 to 22 Local matrix element of coupled network equation 23 Ideal parallelism 24 Parallelism when the present invention is applied to circuit simulation of 16M DRAM 25 Same as the prior art Degree of parallelism
Claims (1)
ョン方式において、部分回路間の結合回路網方程式の行
列構造を各プロセッサがそれぞれ独自に記憶するとし、
同結合回路網方程式の行ベクトルあるいは行ベクトル群
からなるローカルな行列構造を各プロセッサが分散し記
憶するとし、各プロセッサは外部変数に関する部分回路
の評価モデルを並列に生成した後に同等価モデル要素を
行ベクトル単位でその行に対応する結合回路網方程式の
行ベクトル演算を割り当てられたプロセッサに転送し、
該プロセッサは結合回路網方程式のローカルな行列要素
を合成する、以上のデータ構成の下にピボット行を割り
当てられたプロセッサが同行ベクトルを他のプロセッサ
に転送し、これをピボット順に繰り返し、結合回路網方
程式の行列演算を行ベクトル単位で並列に実行する並列
回路シミュレーション方式。1. A parallel circuit simulation method based on circuit division, wherein each processor independently stores a matrix structure of a coupled network equation between partial circuits,
It is assumed that each processor distributes and stores a local matrix structure consisting of row vectors or row vector groups of the same connected network equation, and each processor generates the evaluation model of the partial circuit related to the external variables in parallel and then the same model element is stored. Transfer the row vector operation of the coupled network equation corresponding to the row in row vector units to the assigned processor,
The processor synthesizes local matrix elements of the coupled network equation. A processor assigned with a pivot row under the above data structure transfers the same vector to another processor, and this is repeated in the pivot order. A parallel circuit simulation method that executes matrix operations on equations in parallel in row vector units.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4044710A JPH06282596A (en) | 1992-03-02 | 1992-03-02 | Parallel circuit simulation system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4044710A JPH06282596A (en) | 1992-03-02 | 1992-03-02 | Parallel circuit simulation system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06282596A true JPH06282596A (en) | 1994-10-07 |
Family
ID=12698980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4044710A Withdrawn JPH06282596A (en) | 1992-03-02 | 1992-03-02 | Parallel circuit simulation system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06282596A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011022693A (en) * | 2009-07-14 | 2011-02-03 | Fujitsu Semiconductor Ltd | Method, program and device for designing integrated circuit |
| CN109782625A (en) * | 2018-12-20 | 2019-05-21 | 中国电力科学研究院有限公司 | A kind of real-time emulation method and system of circuit model |
-
1992
- 1992-03-02 JP JP4044710A patent/JPH06282596A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011022693A (en) * | 2009-07-14 | 2011-02-03 | Fujitsu Semiconductor Ltd | Method, program and device for designing integrated circuit |
| CN109782625A (en) * | 2018-12-20 | 2019-05-21 | 中国电力科学研究院有限公司 | A kind of real-time emulation method and system of circuit model |
| CN109782625B (en) * | 2018-12-20 | 2023-11-14 | 中国电力科学研究院有限公司 | Real-time simulation method and system for circuit model |
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