JPH06275816A - Schottky barrier diode - Google Patents

Schottky barrier diode

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Publication number
JPH06275816A
JPH06275816A JP8417293A JP8417293A JPH06275816A JP H06275816 A JPH06275816 A JP H06275816A JP 8417293 A JP8417293 A JP 8417293A JP 8417293 A JP8417293 A JP 8417293A JP H06275816 A JPH06275816 A JP H06275816A
Authority
JP
Japan
Prior art keywords
barrier
schottky barrier
schottky
silicon substrate
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8417293A
Other languages
Japanese (ja)
Inventor
Takashi Suga
孝 菅
Junichi Ishida
純一 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP8417293A priority Critical patent/JPH06275816A/en
Publication of JPH06275816A publication Critical patent/JPH06275816A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To provide a novel structure of a Schottky diode which can further lower the loss as compared with the conventional one by using a barrier metal so as to meet demands. CONSTITUTION:A plurality of P-type island-like regions 4 is buried in an N-type silicon substrate and means 3 which generate first barrier heights are respectively provided on the main surface of the silicon substrate above the island-like areas and, at the same time, a plurality of means 5 which generate second barrier heights is provided on the main surface of the silicon substrate surrounded by the first barriers. In addition, this Schottky barrier diode is so constituted that the first barrier means 3 are just above the respective space charge layers expanding from the regions 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は従来のものより更に整流
特性が良好であって損失の少ないショット (2) キバリヤダイオ−ドに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shot-barrier diode (2) having better rectifying characteristics and less loss than conventional ones.

【0002】[0002]

【従来技術とその解決すべき課題】メタルと半導体との
接触により生ずる電位障壁を利用して整流する図1の如
き構造をもつショットキバリヤダイオ−ド(図において
(1)はシリコン基板、(2)はエピタキシャル層、
(3)はクロム(Cr)等のバリヤメタル)は、他のダ
イオ−ドに比して高速かつ正方向立上り電圧が低く低損
失であることから電力用として多く用いられている。特
に最近におけるスイッチング電源等の電圧の低圧化はそ
の必要をとみに高めつつあり、更に低損失のショットキ
バリヤダイオ−ドへの要求が強い。これを実現するため
には正方向電圧降下と逆方向電流が現在のものより小さ
く、ダイオ−ドの損失即ち正方向損失と逆方向損失の和
の小さい整流特性の良好なものの実現が必要である。一
般にショットキバリヤダイオ−ドの正方向電圧降下と逆
方向電流は、ショットキ接合(障壁)を形成するバリヤ
メタルの材質(障壁高さφB)により決定され、障壁高
さ(φB)が大きいと正方向電圧降下が大きく、逆方向
電流が小さい。又障壁高さ(φB)が小さいと正方向電
圧降下が小さく、逆方向電流が大きいという夫々正逆相
反する特性を有する。
2. Description of the Related Art A Schottky barrier diode having a structure as shown in FIG. 1 for rectifying by utilizing a potential barrier generated by contact between a metal and a semiconductor ((1) in the figure is a silicon substrate, (2) ) Is the epitaxial layer,
(3) is a barrier metal such as chrome (Cr), which is often used for electric power because it is faster than other diodes and has a low positive-direction rising voltage and low loss. Particularly in recent years, lowering of the voltage of switching power supplies and the like has been rising to meet the need, and there is a strong demand for Schottky barrier diodes with low loss. In order to realize this, it is necessary to realize a good rectification characteristic in which the forward voltage drop and the reverse current are smaller than the current one, and the diode loss, that is, the sum of the forward loss and the reverse loss is small. . Generally, the forward voltage drop and reverse current of a Schottky barrier diode are determined by the material of the barrier metal (barrier height φB) that forms the Schottky junction (barrier), and when the barrier height (φB) is large, the forward voltage is increased. Large drop and small reverse current. Further, when the barrier height (φB) is small, the forward voltage drop is small, and the reverse current is large.

【0003】因みにショットキメタルとシリコンが作る
障壁高さ(φB)は従来知られているメタルで見ればチ
タン(Ti)0.5eV、バナジウム(V)0.55e
V、クロム(Cr)0.6eV、モリブデン(Mo)0.
7eV、アルミニウム(Al)0.8eVである。従っ
て損失が正方向と逆方向損失の和で与えられるダイオ−
ドにおいては、正逆方向損失の兼ね合いによって最も低
損失が実現される材質を選ばざるを得ず、現状ではモリ
ブデン(Mo)が最も多く用いられている。しかし現在
以上に低損失のショットキバリヤダイオ−ドを現状の構
造によって実現するには、新しい材質の開拓などの難し
い課題が解決されなければならない。 (3)
Incidentally, the barrier height (φB) formed by Schottky metal and silicon is 0.5 eV for titanium (Ti) and 0.55 e for vanadium (V) in the case of conventionally known metals.
V, chrome (Cr) 0.6 eV, molybdenum (Mo) 0.
7 eV and aluminum (Al) 0.8 eV. Therefore, the loss is given by the sum of the forward loss and the backward loss.
For this reason, it is inevitable to select a material that realizes the lowest loss due to the balance of forward and reverse loss, and molybdenum (Mo) is most often used at present. However, in order to realize a Schottky barrier diode with a lower loss than the present with the existing structure, difficult problems such as the development of new materials must be solved. (3)

【0004】[0004]

【発明の目的】本発明は従来知られているバリヤメタル
を使用して、従来のものより更に低損失を実現しうるシ
ョットキバリヤダイオ−ドの新しい構造を提供し、前記
の要求に応えうるようにしたものである。
It is an object of the present invention to provide a new structure of a Schottky barrier diode which can realize a lower loss than the conventional one by using a conventionally known barrier metal so as to meet the above requirements. It was done.

【0005】[0005]

【課題を解決するための本発明の手段】本発明はN型シ
リコン基体に埋込型のP型島状領域を複数個設け、夫々
島状領域上のシリコン基体の主面上に第1の障壁高さ
(φB1)を生ずる手段を設けると共に、第1の障壁に囲
まれるシリコン基体の主面に第2の障壁高さ(φB2)を
生じせしめる手段を設け、且つ、逆方向電圧印加時に第
1の障壁手段と、島状領域から拡がる空間電荷層が重な
るように形成した点にある。
According to the present invention, a plurality of buried P-type island regions are provided in an N-type silicon substrate, and a first surface is formed on the main surface of the silicon substrate on each island region. A means for producing a barrier height (φB1) is provided, and a means for producing a second barrier height (φB2) is provided on the main surface of the silicon substrate surrounded by the first barrier. The barrier means of No. 1 and the space charge layer extending from the island region are formed so as to overlap with each other.

【0006】[0006]

【実施例】図2は本発明の一実施例を示す部分的断面図
で従来例と同一符号は同等部分を示す。図中3はショッ
トキ−メタルとしてCr、4はN型エピタキシアル層2
に埋込形成されたP型島状領域、5はアルミニウム(A
l)等のショットキメタル(a)〜(g)は寸法を示
す。図3(a)(b)は従来例と比較した本発明実施例
の特性図で(a)図は正方向電圧(VF)−正方向電流
(IF)特性図、(b)図は逆方向電圧(VR)−逆方向
電流(IR)特性図で点線(イ)は従来例、実線(ロ)は
本発明の実施例の特性を示す。下方の(ロ)はデバイス単
位面積当りの特性、上方の(ロ)はCr単位面積当りの
特性を示す。
FIG. 2 is a partial sectional view showing an embodiment of the present invention, and the same reference numerals as those in the conventional example show the same parts. In the figure, 3 is a Schottky metal, Cr, 4 is an N-type epitaxial layer 2
P-type island regions 5 embedded in the aluminum are aluminum (A
Schottky metals (a) to (g) such as l) indicate dimensions. 3A and 3B are characteristic diagrams of the embodiment of the present invention compared with the conventional example. FIG. 3A is a characteristic diagram of a forward voltage (VF) -forward current (IF), and FIG. In the voltage (VR) -reverse current (IR) characteristic diagram, the dotted line (a) shows the conventional example and the solid line (b) shows the characteristic of the embodiment of the present invention. The lower part (b) shows the characteristics per unit area of the device, and the upper part (b) shows the characteristics per unit area of Cr.

【0007】図に於いてはショットキ−バリヤメタルと
してCr3、Al5等が図示されているが必用に応じて
他のメタルはMo、V、Ti、其の他が用い得ることは
云うまでもない。本発明構造の特性は用いられるN型シ
リコン2の比抵抗ショットキ−メタル3、5とN型シリ
コンとの間のN層Ncの比抵抗、その (4) 厚さC、ショットキ−メタル3がシリコンと作る障壁高
さ(φB1)により大きく変化する。本発明の構造の特徴
はP層4上のショットキ−メタル3(図の場合Cr)が
隣接するショットキ−バリヤメタル5のφB2より小さい
ことである。また寸法Cは逆方向電圧が印加された場合
にP型4の空乏層とCr3の空乏層の少なくとも1部が
重なる厚さ以下である。本発明のショットキバリヤダイ
オ−ドの特性はエピタキシアル層2、層Ncの比抵抗、
a、b、c、d、eの寸法によって大きく変化する。本
説明に於いては低圧用のショットキバリヤダイオ−ドと
して適する様に次の様にパラタ−タ−を決めて実験を行
った。
Although Cr3, Al5, etc. are shown as Schottky barrier metals in the figure, it goes without saying that other metals such as Mo, V, Ti and others can be used if necessary. The characteristic of the structure of the present invention is that the specific resistance of the N-type silicon 2 used is the specific resistance of the N layer Nc between the N-type silicon and the specific resistance Schottky metal 3, 5 (4) The thickness C, the Schottky metal 3 is silicon. It changes greatly depending on the height of the barrier (φB1). The feature of the structure of the present invention is that the Schottky metal 3 (Cr in the figure) on the P layer 4 is smaller than φB2 of the adjacent Schottky barrier metal 5. The dimension C is equal to or less than the thickness at which at least a part of the depletion layer of P type 4 and the depletion layer of Cr3 overlap when a reverse voltage is applied. The characteristics of the Schottky barrier diode according to the present invention are: the resistivity of the epitaxial layer 2 and the layer Nc;
It greatly changes depending on the dimensions of a, b, c, d, and e. In the present description, an experiment was carried out with the following parameters determined so as to be suitable as a Schottky barrier diode for low pressure.

【0008】以下図2における諸パラメ−タを示すと、
N++基板1(3/1000Ωcm)、N層2(0.2Ωc
m)、P層4×1217/cm3層NC(0.2Ωcm)、
a(1.5μm)、b(1.0μm)、c(0.5μ
m)、d(0.5μm)、e(1.0μm)、f(3μ
m)、g(400μm)。
The various parameters in FIG. 2 are shown below.
N ++ substrate 1 (3/1000 Ωcm), N layer 2 (0.2 Ωc)
m), P layer 4 × 12 17 / cm3 layer NC (0.2 Ωcm),
a (1.5 μm), b (1.0 μm), c (0.5 μm)
m), d (0.5 μm), e (1.0 μm), f (3 μm
m), g (400 μm).

【0009】図3(a)から明確なように正方向特性は
従来例(イ)と本発明の実施例(ロ)はほゞ同等な特性
を示す。又逆方向特性は逆方向電圧(VR)の高い所で
本発明の実施例(ロ)は逆方向電流が著しく小さいこと
を示している。このことは、Crのショットキ−バリヤ
3の空乏層と島状領域4と層Ncが形成するPN接合の
空乏層が重なることによって生ずるJunction FieldE
ffect Tronsister効果である。つまり空乏層が重なり
合うとそれ以上各部の電界強度、空乏層の体積は余り変
らないので電流が飽和特性を示すことになる。
As is clear from FIG. 3 (a), the forward direction characteristics of the conventional example (a) and the embodiment (b) of the present invention are almost equivalent. The reverse characteristic shows that the reverse current is extremely small in the embodiment (B) of the present invention where the reverse voltage (VR) is high. This is due to the fact that the depletion layer of the Schottky barrier 3 of Cr and the depletion layer of the PN junction formed by the island-shaped region 4 and the layer Nc overlap each other.
ffect Tronsister effect. That is, when the depletion layers overlap, the electric field strength of each part and the volume of the depletion layer do not change much more, so that the current exhibits saturation characteristics.

【0010】以上の実施例では、バリヤメタル3(C
r)、バリヤメタル5(Al)、島状領域4を同電位と
した場合であるが、島状領域4のみを電気的に浮いてい
る構造でも同様な特性を示すと考えられる。又バリヤメ
タル3、5及び島状 (5) 領域4のパタ−ンは長さ1cmのストライプ構造で説明
しているが、矩形、正方形、円形でもよい。又第2のバ
リヤメタル5の代わりにシリコン酸化膜を用いてもよ
く、更に層Ncの部分に主面より浅いP型拡散層を形成
し、P−N接合として利用することもできる。要は第1
のバリヤメタル3とN層Ncとの接触により形成される
障壁高さ(φB1)と第2のバリヤメタル又はPN接合又
はシリコン酸化膜により形成される障壁高さ(φB2)と
の関係をφB1<φB2の関係に設定することが重要であ
る。
In the above embodiment, the barrier metal 3 (C
r), the barrier metal 5 (Al), and the island-shaped region 4 are at the same potential, but it is considered that a structure in which only the island-shaped region 4 is electrically floating exhibits similar characteristics. Further, the pattern of the barrier metal 3 and 5 and the island-shaped (5) region 4 is described as a stripe structure having a length of 1 cm, but it may be rectangular, square or circular. A silicon oxide film may be used instead of the second barrier metal 5, and a P-type diffusion layer shallower than the main surface may be formed in the layer Nc portion to be used as a P-N junction. The point is first
The relationship between the barrier height (φB1) formed by the contact between the barrier metal 3 and the N layer Nc (φB1) and the barrier height (φB2) formed by the second barrier metal or the PN junction or the silicon oxide film is φB1 <φB2. It is important to set the relationship.

【0011】図4は本発明の一実施例構造を製作するた
めの部分的工程断面図で先ず所要パラメ−タを持ちP型
埋込みエピタキシアルウェハ1を用意する(a図)、次
に該ウェハ−1の主面にクロム(Cr)等のバリヤメタ
ル3を蒸着する。(b図)次いでP型埋込層と対向する
部分のバリヤメタルを残し、他をエッチング等により除
去する。(C図)次にバリヤメタル3に跨って主面上に
電極金属(Al)を蒸着する。(d図)なお、この場合、
アルミニウム(Al)は第2のバリヤメタルとしての機
能を備えるものである。Al蒸着後はオ−ミックコンタ
クトメタルを裏面につける。また一般にはショットキ−
接合の外周はPN接合のガ−ドリングで、ショットキ接
合周辺部の逆方向特性劣化が保護されているのが一般的
である。以上はエピタキシャル法で発明の構造を作った
が拡散法でも類似の構造が出来ることは専門家であれば
常識的なことであるので省略する。
FIG. 4 is a partial process sectional view for manufacturing a structure of one embodiment of the present invention. First, a P-type buried epitaxial wafer 1 having required parameters is prepared (FIG. 4A), and then the wafer is prepared. A barrier metal 3 such as chromium (Cr) is deposited on the main surface of -1. Next, the barrier metal in the portion facing the P-type buried layer is left, and the others are removed by etching or the like. (Fig. C) Next, an electrode metal (Al) is vapor-deposited on the main surface across the barrier metal 3. (Fig. D) In this case,
Aluminum (Al) has a function as a second barrier metal. After Al deposition, an ohmic contact metal is attached to the back surface. Also, in general, Schottky
The outer periphery of the junction is generally guarded by a PN junction to protect the reverse direction characteristic deterioration of the Schottky junction peripheral portion. The above is the structure of the invention made by the epitaxial method, but it is common knowledge for a specialist that a similar structure can be made by the diffusion method, and therefore it is omitted.

【0012】[0012]

【発明の効果】以上の説明から明らかなように本発明に
よれば、電力用として好適する低損失のショットキバリ
ヤダイオ−ドを提供しうる。
As is apparent from the above description, according to the present invention, a low loss Schottky barrier diode suitable for electric power can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来構造図FIG. 1 Conventional structure diagram

【図2】 (6) 本発明の一実施例構造図(6) Structural diagram of an embodiment of the present invention

【図3】従来例と比較した本発明実施例構造の特性図で (a)図は正方向電圧−正方向電流特性図 (b)図は逆方向電圧−逆方向電流特性図FIG. 3 is a characteristic diagram of a structure of an embodiment of the present invention compared with a conventional example. (A) is a forward voltage-forward current characteristic diagram, (b) is a reverse voltage-reverse current characteristic diagram.

【図4】本発明実施例の製造工程図FIG. 4 is a manufacturing process chart of an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 N型シリコン基体 2 N型エピタキシアル層 3 ショットキバリヤメタル(第1) 4 P型島状領域 5 ショットキバリヤメタル(第2) 1 N-type silicon substrate 2 N-type epitaxial layer 3 Schottky barrier metal (first) 4 P-type island region 5 Schottky barrier metal (second)

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 N型シリコン基体に埋込形成された複数
個のP型島状領域と前記N型シリコン基体の前記P型島
状領域と対向する主面に被着されて所要の障壁高さ(φ
B1)を生ずるショットキバリヤメタルと、前記ショット
キバリヤメタルに挟まれた前記主面との間で第2の障壁
高さ(φB2)を生じせしめる手段を備え、且つ前記障壁
高さをφB1<φB2の関係に設定すると共に、前記主面か
らP型島状領域の深さを逆方向電圧印加時に前記ショッ
トキバリヤメタルから広がる空間電荷層とP型島状領域
から広がる空間電荷層の少なくとも一部が重なり合う距
離に設定したことを特徴とするショットキバリヤダイオ
−ド。
1. A plurality of P-type island regions buried in an N-type silicon substrate and a main surface of the N-type silicon substrate which faces the P-type island regions and is covered with a required barrier height. Sa (φ
B1) is provided, and a means for producing a second barrier height (φB2) between the Schottky barrier metal and the main surface sandwiched by the Schottky barrier metal, and the barrier height of φB1 <φB2 And the depth of the P-type island region from the main surface is overlapped with at least a part of the space charge layer extending from the Schottky barrier metal and the space charge layer extending from the P-type island region when a reverse voltage is applied. Schottky barrier diode characterized by being set to a distance.
【請求項2】 第2の障壁高さを生じせしめる手段とし
て第2のショットキバリヤメタルを用いたことを特徴と
する特許請求の範囲1項記載のショットキバリヤダイオ
−ド。
2. A Schottky barrier diode according to claim 1, wherein a second Schottky barrier metal is used as a means for producing the second barrier height.
【請求項3】 第2の障壁高さを生じせしめる手段とし
てN型シリコン基体に形成されたPN接合を用いたこと
を特徴とする特許請求の範囲1項記載のショットキバリ
ヤダイオ−ド。
3. A Schottky barrier diode according to claim 1, wherein a PN junction formed on an N-type silicon substrate is used as a means for producing the second barrier height.
【請求項4】 第2の障壁高さを生じせしめる手段とし
てシリコン酸化膜を用いたことを特徴とする特許請求の
範囲1項記載のショットキバリヤダイオ−ド。
4. A Schottky barrier diode according to claim 1, wherein a silicon oxide film is used as a means for producing the second barrier height.
【請求項5】 P型島状領域の形状をショットキバリヤ
メタル(第1)の形状と同等もしくは若干大きく形成し
たことを特徴とする特許請求の範囲1項乃至4項記載の
ショットキバリヤダイオ−ド。
5. The Schottky barrier diode according to any one of claims 1 to 4, wherein the shape of the P-type island region is equal to or slightly larger than the shape of the Schottky barrier metal (first). .
JP8417293A 1993-03-18 1993-03-18 Schottky barrier diode Pending JPH06275816A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8417293A JPH06275816A (en) 1993-03-18 1993-03-18 Schottky barrier diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8417293A JPH06275816A (en) 1993-03-18 1993-03-18 Schottky barrier diode

Publications (1)

Publication Number Publication Date
JPH06275816A true JPH06275816A (en) 1994-09-30

Family

ID=13823079

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8417293A Pending JPH06275816A (en) 1993-03-18 1993-03-18 Schottky barrier diode

Country Status (1)

Country Link
JP (1) JPH06275816A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2807569A1 (en) * 2000-04-10 2001-10-12 Centre Nat Rech Scient IMPROVEMENTS TO SCHOTTKY DIODES

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2807569A1 (en) * 2000-04-10 2001-10-12 Centre Nat Rech Scient IMPROVEMENTS TO SCHOTTKY DIODES
WO2001078152A3 (en) * 2000-04-10 2002-02-07 Centre Nat Rech Scient Schottky-diode semiconductor device

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