JPH06268226A - Insulated gate bipolar transistor - Google Patents
Insulated gate bipolar transistorInfo
- Publication number
- JPH06268226A JPH06268226A JP4842193A JP4842193A JPH06268226A JP H06268226 A JPH06268226 A JP H06268226A JP 4842193 A JP4842193 A JP 4842193A JP 4842193 A JP4842193 A JP 4842193A JP H06268226 A JPH06268226 A JP H06268226A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- bipolar transistor
- impurity concentration
- insulated gate
- base layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高耐圧、大電流を制御
する半導体スイッチング素子として用いられる絶縁ゲー
ト型バイポーラトランジスタ (以下ＩＧＢＴと略す) に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor (hereinafter abbreviated as IGBT) used as a semiconductor switching element for controlling a high breakdown voltage and a large current.
【０００２】[0002]
【従来の技術】ＩＧＢＴは大電流を電圧で制御できる電
力用半導体素子で、図２に示すような構造を有する。す
なわち、ｎ- ベース層１の表面層に選択的にｐウエル２
が形成され、そのｐウエル２の表面層に選択的にｎ+ ソ
ース層３が形成されている。そして、ｎ- 層１の露出面
からｎ+ 層３とにはさまれたｐウエル２の表面にかけて
絶縁膜４を介してＧ端子に接続されたゲート電極５が設
けられ、ｐウエル２とｎ + 層３とに共通にＥ端子に接続
されたエミッタ電極６が接触している。一方、ｎ - ベー
ス層１の下側には、ｎ+ バッファ層７、次いでｐ+ アノ
ード層８が形成され、そのアノード層８にＣ端子に接続
されたコレクタ電極９が接触している。この素子は、ゲ
ート電極５に電圧を印加するとｐウエル２のゲート直下
の部分がｎ形の反転領域となってＭＯＳ反転層が形成さ
れ、エミッタ電極６から電子がｎ-ベース層１へと注入
される。この電子の電流はｐ+ アノード層８とｎ- ベー
ス１およびｎ+ バッファ層７とｐウエル２とからなるｐ
ｎｐトランジスタのベース電流となって大きな電流を流
すことが可能である。このとき、正孔がｐ+ アノード層
８からバッファ層７を通してｎ- ベース層１を通過し、
ｐウエル２に至る。2. Description of the Related Art An IGBT is a power source that can control a large current with a voltage.
The force semiconductor device has a structure as shown in FIG. You
No, n-P well 2 is selectively formed on the surface layer of base layer 1.
Is formed, and n is selectively formed on the surface layer of the p well 2.+So
The base layer 3 is formed. And n-Exposed surface of layer 1
To n+Over the surface of p-well 2 sandwiched by layer 3
A gate electrode 5 connected to the G terminal through the insulating film 4 is provided.
P well 2 and n +Connected to E terminal in common with layer 3
The formed emitter electrode 6 is in contact. On the other hand, n -Base
Below the layer 1, n+Buffer layer 7, then p+Ano
Layer 8 is formed, and the anode layer 8 is connected to the C terminal
The collector electrode 9 formed is in contact. This element is
When a voltage is applied to the gate electrode 5, it is directly under the gate of the p well 2.
Is a n-type inversion region and a MOS inversion layer is formed.
The electrons from the emitter electrode 6-Injection into base layer 1
To be done. The current of this electron is p+Anode layer 8 and n-Base
S1 and n+P consisting of buffer layer 7 and p well 2
A large current flows as the base current of the np transistor.
It is possible to At this time, holes are p+Anode layer
8 through the buffer layer 7 n-Passing through the base layer 1,
Reach p-well 2.
【０００３】このＩＧＢＴは、モータなどのインダクタ
ンスを負荷とする場合が多く、Ｌ負荷での動作が重要で
ある。図３はＬ負荷における典型的なコレクタ電流波形
を31に、コレクタ電圧波形を32に示している。また、図
４はＩＧＢＴ内部におけるキャリア分布の時間的変化を
図下部の層構造に対応させて示し、線41は定常時の正孔
分布で、矢印42はストレージ期間中の正孔の動き、矢印
43はフォール期間中の正孔の動きである。This IGBT is often loaded with an inductance of a motor or the like, and operation under an L load is important. FIG. 3 shows a typical collector current waveform at L load 31 and a collector voltage waveform at 32. In addition, FIG. 4 shows the temporal change of the carrier distribution inside the IGBT corresponding to the layer structure in the lower part of the figure, the line 41 is the hole distribution in the steady state, the arrow 42 is the movement of holes during the storage period, and the arrow
43 is the movement of holes during the fall period.
【０００４】ターンオフにおいては、電流、電圧の変化
はいくつかの段階によって分類される。ストレージ期間
ｔS の間は電流ＩC は一定に保たれ、コレクタ電圧ＶC
が時間とともにクランプ電圧まで至る。それにひきつづ
いてフォール期間ｔC では、電流が急激に減少する。こ
のとき、浮遊のインダクタンスＬによって次式のΔＶに
相当する電圧が余分にかかる。At turn-off, changes in current and voltage are classified into several stages. During the storage period t S , the current I C is kept constant and the collector voltage V C
Reaches the clamp voltage with time. Then, in the fall period t C , the current sharply decreases. At this time, a voltage corresponding to ΔV in the following equation is additionally applied due to the floating inductance L.
【０００５】ΔＶ＝Ｌ dI／dt (1) これをはね上がり電圧と呼ぶ。一方素子内部では、スト
レージ期間ｔS 中は、電圧が大きくなるとともに、ｐウ
エル２とｎ- ベース１の間に空乏層が広がり、このため
空乏化したｎ- ベース１にあった正孔と電子がはき出さ
れる。これを示したのが矢印42である。フォール期間で
は、ｎ- ベース１中に残った正孔が矢印43に示すように
消滅していく。したがって、フォール期間に入った時ｎ
- ベース１中に残った正孔の量が多い程ｔC は長い。す
なわち、dI／dtは小さく、(1) 式よりΔＶも小さい。ま
た、一般にｔS ＞＞ｔC であって、ターンオフ時に発生
する損失Ｗ＝Ｖ×ＩはｔS の期間の方が大きい。なお、
素子の設計によって異なるが、一般に高速のＩＧＢＴで
はｔS は0.３μｓ、ｔC は10ｎｓ程度である。ΔV = L dI / dt (1) This is called a rising voltage. In contrast element inside, during the storage period t S, along with the voltage increase, p-well 2 and the n - depletion between the base 1 is spread, thus depleted n - holes and electrons were in the base 1 Is rubbed out. This is indicated by the arrow 42. During the fall period, holes remaining in the n − base 1 disappear as shown by an arrow 43. Therefore, when the fall period starts
- t C the greater the amount of hole remaining in the base 1 is long. That is, dI / dt is small, and ΔV is also smaller than the equation (1). Further, in general, t S >> t C , and the loss W = V × I generated at turn-off is larger in the period of t S. In addition,
Generally, in a high speed IGBT, t S is about 0.3 μs and t C is about 10 ns, though it depends on the design of the device.
【０００６】これまで、ＩＧＢＴは総合損失をなるべく
小さくする努力がなされてきた。総合損失は、定常損失
とスイッチング損失からなる。まず定常損失について説
明する。素子の耐圧はｎ- ベース１の抵抗と厚さで決ま
る。従って、ｎ- ベース１の不純物濃度を下げれば耐圧
を保ったままで厚さを薄くすることができる。前述のｐ
ｎｐトランジスタは、ベース層の厚さが薄い程大きな電
流を流すことができ、従って、定常損失を下げることが
できる。次に、スイッチング損失について説明する。前
述のようにストレージ期間ｔS 中、空乏層がｎ- ベース
１中を広がるが、不純物濃度が少ないと空乏層ののび方
が速くなり、従ってｔS が短くなる。Hitherto, efforts have been made to reduce the total loss of the IGBT as much as possible. The total loss consists of steady loss and switching loss. First, the steady loss will be described. The breakdown voltage of the device is determined by the resistance and thickness of the n − base 1. Therefore, if the impurity concentration of the n − base 1 is lowered, the thickness can be reduced while maintaining the breakdown voltage. The above p
The np transistor can flow a larger current as the thickness of the base layer is thinner, and thus the steady loss can be reduced. Next, the switching loss will be described. As described above, the depletion layer spreads in the n − base 1 during the storage period t S , but if the impurity concentration is low, the depletion layer spreads faster and thus t S becomes shorter.
【０００７】こうしてｎ- ベース１の不純物濃度を下げ
ることは、定常損失、スイッチング損失の双方の低減に
効果がある。ｎ- ベース層の抵抗率と厚さは耐圧によっ
て決まるが、600 ＶクラスのＩＧＢＴでは、30〜50Ωc
m、50〜60μｍ程度であり、抵抗率を100 Ωcm以上にす
ることで厚さを10〜20μｍ薄くすることができ、上記の
効果が得られる。Reducing the impurity concentration of the n - base 1 in this manner is effective in reducing both steady loss and switching loss. The resistivity and thickness of the n - base layer depend on the breakdown voltage, but in the 600 V class IGBT, it is 30 to 50 Ωc.
m, 50 to 60 μm, and by setting the resistivity to 100 Ωcm or more, the thickness can be reduced to 10 to 20 μm, and the above effect can be obtained.
【０００８】[0008]
【発明が解決しようとする課題】このようにｎ- ベース
層の不純物濃度を下げ厚さを薄くすると、ターンオフ時
のストレージ期間ｔS 中にｎ- ベース層１すべての領域
にわたって空乏層が広がる。するとフォール期間ｔC 中
に消滅すべき正孔は残っていないことになるため、空乏
層がバッファ層７に到達した時点で急激に電流が減少
し、大きなdI／dtが発生する。これは大きなはね上がり
電圧ΔＶを発生させ、素子破壊に通じる。また大きなdI
／dtは、浮遊の容量を通じて周辺回路に大きなノイズを
発生させるなどの問題の原因となる。When the impurity concentration of the n - base layer is lowered and the thickness thereof is reduced in this way, the depletion layer spreads over the entire region of the n - base layer 1 during the storage period t S at turn-off. Then, since there are no holes left to be extinguished during the fall period t C , the current sharply decreases when the depletion layer reaches the buffer layer 7, and a large dI / dt is generated. This causes a large rising voltage ΔV, which leads to device breakdown. Also a large dI
The / dt causes a problem such as generating a large noise in the peripheral circuit through the floating capacitance.
【０００９】本発明の目的は、総合損失低減のためにｎ
- ベース層の不純物濃度を下げ、厚さを薄くすると、タ
ーンオフ時に大きなdI／dtが発生する問題を解決し、Ｌ
負荷ターンオフ時の素子の破壊と周辺回路の大きなノイ
ズ発生のないＩＧＢＴを提供することにある。An object of the present invention is to reduce the total loss by n
- lowering the impurity concentration of the base layer, when reducing the thickness, large dI / dt is to solve the problems that occur at turn-off, L
An object of the present invention is to provide an IGBT that is free from element destruction at the time of load turn-off and large noise generation in peripheral circuits.
【００１０】[0010]
【課題を解決するための手段】上述の目的を達成するた
めに、本発明は、第一導電形の低不純物濃度ベース層の
一側の表面上に絶縁ゲート構造を有し、他側に第一導電
形の高不純物濃度のバッファ層を介して第二導電形のコ
レクタ層を備えたＩＧＢＴにおいて、バッファ層がベー
ス層側の相対的に低い不純物濃度の第一層と、コレクタ
層側の相対的に高い不純物濃度の第二層とよりなるもの
とする。そして、耐圧600 Ｖ以上で、第一導電形がｎ
形、ｎベース層の抵抗率が100 Ωcm以上であり、バッフ
ァ層の第一層の抵抗率が20Ωcm以下であることが有効で
ある。また、このＩＧＢＴが誘導負荷で用いられること
が有効である。In order to achieve the above object, the present invention has an insulated gate structure on one surface of a first conductivity type low impurity concentration base layer and a second conductivity type on the other side. In an IGBT including a collector layer of a second conductivity type through a buffer layer of one conductivity type with a high impurity concentration, the buffer layer is a base layer side relatively low impurity concentration relative to the collector layer side. The second layer has a relatively high impurity concentration. When the withstand voltage is 600 V or more and the first conductivity type is n
It is effective that the resistivity of the base layer is 100 Ωcm or more and the resistivity of the first layer of the buffer layer is 20 Ωcm or less. Further, it is effective that this IGBT is used as an inductive load.
【００１１】[0011]
【作用】ターンオフ時にベース層中に広がる空乏層がバ
ッファ層の第一層に到達すると、空乏層の伸びが抑えら
れ、ここからフォール期間となる。しかし、バッファ層
の第一層の不純物濃度が第二層の不純物濃度より低いた
め、第一層中へも幾分空乏層が広がっていく。これは図
４に示した波形でフォール期間ｔC に入るときの中間領
域にあたる。従って、バッファ層の第一層中のキャリア
減少に応じて電流が減少するため、急激な電流減少が抑
えられてはね上がり電圧を小さくすることができる。こ
のとき、フォール期間ｔC は長くなるが、前述のように
ストレージ期間ｔS の方が長く、発生損失も大きいた
め、ｔC の増大による損失増加は大きく影響しない。When the depletion layer spreading in the base layer reaches the first layer of the buffer layer at turn-off, the extension of the depletion layer is suppressed and the fall period starts from here. However, since the impurity concentration of the first layer of the buffer layer is lower than the impurity concentration of the second layer, the depletion layer spreads to some extent in the first layer. This corresponds to an intermediate region when the fall period t C is entered in the waveform shown in FIG. Therefore, the current decreases in accordance with the decrease in carriers in the first layer of the buffer layer, so that the rapid decrease in current can be suppressed and the jump voltage can be reduced. At this time, the fall period t C becomes longer, but as described above, the storage period t S is longer and the generated loss is larger. Therefore, the increase in loss due to the increase in t C does not significantly affect.
【００１２】[0012]
【実施例】図１は本発明の一実施例のＩＧＢＴを示し、
図２と共通の部分には同一の符号が付されている。図２
との相違は、ｎ+ バッファ層７とｎ- ベース層１の間に
作用の項ではバッファ層の第二層として説明した中間層
10が挿入されている。中間層10の厚さは、不純物濃度を
低くすることによってｎ- ベース層１が厚さが減少した
分より薄くなければ定常損失減少の効果が少なくなる。
従って高抵抗率化により薄くできるｎ- ベース層１の厚
さ10〜20μｍより薄い５〜10μｍ程度であることが望ま
しい。抵抗については、不純物濃度と厚さの積がｎ- ベ
ース層１と同程度にすれば空乏層が適度に広まる。例え
ば、ｎ- ベース層の抵抗率が100 Ωcm、厚さが50μｍで
あれば、厚さ５μｍの中間層10の抵抗率は10Ωcm程度と
する。このように中間層10の抵抗率は数Ωcmから数十Ω
cmの範囲で選ばれる。FIG. 1 shows an IGBT according to an embodiment of the present invention,
The same parts as those in FIG. 2 are designated by the same reference numerals. Figure 2
The difference is that between the n + buffer layer 7 and the n − base layer 1, the intermediate layer described in the section of action as the second layer of the buffer layer.
10 is inserted. As for the thickness of the intermediate layer 10, if the impurity concentration is lowered, the effect of steady-state loss reduction becomes small unless the thickness of the n − base layer 1 is reduced.
Therefore, it is desirable that the thickness of the n − base layer 1 which can be thinned by increasing the resistivity is about 5 to 10 μm, which is thinner than 10 to 20 μm. Regarding the resistance, if the product of the impurity concentration and the thickness is set to be about the same as that of the n − base layer 1, the depletion layer is appropriately widened. For example, if the n − base layer has a resistivity of 100 Ωcm and a thickness of 50 μm, the resistivity of the intermediate layer 10 having a thickness of 5 μm is about 10 Ωcm. Thus, the resistivity of the intermediate layer 10 is several Ωcm to several tens Ω.
Selected in the cm range.
【００１３】中間層10は、ｎ- シリコン基板は拡散によ
りバッファ層、コレクタ層を形成する場合、ｎ形拡散の
工程を２度にすること、あるいはｐ+ サブストレート上
にエピタキシャル法でバッファ層、ベース層を形成する
場合、バッファ層成長後ベース層成長前に、エピタキシ
ャル工程を一つ追加することにより形成する。The intermediate layer 10 is formed by diffusing an n - silicon substrate to form a buffer layer and a collector layer when the n-type diffusion process is performed twice, or on the p + substrate by an epitaxial method. When the base layer is formed, it is formed by adding an epitaxial process after the growth of the buffer layer and before the growth of the base layer.
【００１４】[0014]
【発明の効果】本発明によれば、低不純物濃度のベース
層の不純物濃度を下げ、厚さを薄くして定常損失、スイ
ッチング損失の双方を低減する場合、ターンオフ時に広
がる空乏層がバッファ層に到達することによっておこる
大きなdI／dtの発生を、バッファ層のベース層側に中間
の不純物濃度の層を設けることにより、その層への空乏
層の伸びにより大きなdI／dtの発生が防止でき、フォー
ル期間中のはね上がり電圧が抑制されるので、特にＬ負
荷ターンオフ時の素子の破壊や周辺回路における大きな
ノイズ発生の問題のない低総合損失のＩＧＢＴを得るこ
とができた。According to the present invention, when the impurity concentration of the low impurity concentration base layer is reduced and the thickness is reduced to reduce both steady loss and switching loss, a depletion layer that spreads at turn-off becomes a buffer layer. By providing a layer with an intermediate impurity concentration on the base layer side of the buffer layer, it is possible to prevent the generation of a large dI / dt caused by the arrival of a large dI / dt due to the extension of the depletion layer to that layer. Since the rising voltage during the fall period is suppressed, it is possible to obtain an IGBT with low total loss, which is free from problems such as element breakdown at the time of L load turn-off and large noise generation in peripheral circuits.
【図１】本発明の一実施例のＩＧＢＴの断面図FIG. 1 is a sectional view of an IGBT according to an embodiment of the present invention.
【図２】従来のＩＧＢＴの断面図FIG. 2 is a sectional view of a conventional IGBT.
【図３】ＩＧＢＴのＬ負荷ターンオフ時の電流・電圧波
形図[Fig. 3] Current / voltage waveform diagram when IGBT L load is turned off
【図４】ＩＧＢＴのＬ負荷ターンオフ時の正孔分布およ
びその変動を内部層構造と対応させて示すキャリア分布
図FIG. 4 is a carrier distribution diagram showing the hole distribution and its variation at the time of turning off the L load of the IGBT in association with the internal layer structure.
１ ｎ- ベース層 ２ ｐウエル ３ ｎ+ ソース層 ４ 絶縁膜 ５ ゲート電極 ６ エミッタ電極 ７ ｎ+ バッファ層 ８ ｐ+ コレクタ層 ９ コレクタ電極 １０ ｎ中間層1 n - base layer 2 p well 3 n + source layer 4 insulating film 5 gate electrode 6 emitter electrode 7 n + buffer layer 8 p + collector layer 9 collector electrode 10 n intermediate layer
Claims (3)
の表面上に絶縁ゲート構造を有し、他側に第一導電形の
高不純物濃度のバッファ層を介して第二導電形のコレク
タ層を備えたものにおいて、バッファ層がベース層側の
相対的に低い不純物濃度の第一層と、コレクタ層側の相
対的に高い不純物濃度の第二層とよりなることを特徴と
する絶縁ゲート型バイポーラトランジスタ。1. A low conductivity type base layer of the first conductivity type having an insulated gate structure on one surface, and a second conductivity type via a buffer layer of the first conductivity type high impurity concentration on the other side. In the present invention, the buffer layer comprises a first layer having a relatively low impurity concentration on the base layer side and a second layer having a relatively high impurity concentration on the collector layer side. Insulated gate bipolar transistor.
ベース層の抵抗率が100 Ωcm以上であり、バッファ層の
第一層の抵抗率が20Ωcm以下である請求項１記載の絶縁
ゲート型バイポーラトランジスタ。2. A withstand voltage of 600 V or more, the first conductivity type is n type, n
The insulated gate bipolar transistor according to claim 1, wherein the resistivity of the base layer is 100 Ωcm or more and the resistivity of the first layer of the buffer layer is 20 Ωcm or less.
記載の絶縁ゲート型バイポーラトランジスタ。3. The method according to claim 1 or 2 used in an inductive load.
The insulated gate bipolar transistor described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4842193A JPH06268226A (en) | 1993-03-10 | 1993-03-10 | Insulated gate bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4842193A JPH06268226A (en) | 1993-03-10 | 1993-03-10 | Insulated gate bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06268226A true JPH06268226A (en) | 1994-09-22 |
Family
ID=12802863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4842193A Pending JPH06268226A (en) | 1993-03-10 | 1993-03-10 | Insulated gate bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06268226A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996032749A1 (en) * | 1995-04-11 | 1996-10-17 | Rohm Co., Ltd. | Semiconductor device having planar type high withstand voltage vertical devices, and production method thereof |
| US6384431B1 (en) | 1999-10-08 | 2002-05-07 | Denso Corporation | Insulated gate bipolar transistor |
| KR20020053713A (en) * | 2000-12-27 | 2002-07-05 | 니시무로 타이죠 | Semiconductor device |
| KR100351042B1 (en) * | 2000-04-04 | 2002-09-05 | 페어차일드코리아반도체 주식회사 | Insulated gate bipolar transistor having high breakdown voltage in reverse blocking mode and method for fabricating the same |
| US6683343B2 (en) | 2001-02-28 | 2004-01-27 | Kabushiki Kaisha Toshiba | High voltage semiconductor device having two buffer layer |
| US8283697B2 (en) | 2009-12-04 | 2012-10-09 | Fuji Electric Co., Ltd. | Internal combustion engine igniter semiconductor device |
| CN104103682A (en) * | 2013-04-09 | 2014-10-15 | 比亚迪股份有限公司 | IGBT with novel buffer layer structure and manufacturing method thereof |
-
1993
- 1993-03-10 JP JP4842193A patent/JPH06268226A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996032749A1 (en) * | 1995-04-11 | 1996-10-17 | Rohm Co., Ltd. | Semiconductor device having planar type high withstand voltage vertical devices, and production method thereof |
| US6384431B1 (en) | 1999-10-08 | 2002-05-07 | Denso Corporation | Insulated gate bipolar transistor |
| KR100351042B1 (en) * | 2000-04-04 | 2002-09-05 | 페어차일드코리아반도체 주식회사 | Insulated gate bipolar transistor having high breakdown voltage in reverse blocking mode and method for fabricating the same |
| US6448588B2 (en) | 2000-04-04 | 2002-09-10 | Fairchild Korea Semiconductor Ltd. | Insulated gate bipolar transistor having high breakdown voltage in reverse blocking mode |
| KR20020053713A (en) * | 2000-12-27 | 2002-07-05 | 니시무로 타이죠 | Semiconductor device |
| US6683343B2 (en) | 2001-02-28 | 2004-01-27 | Kabushiki Kaisha Toshiba | High voltage semiconductor device having two buffer layer |
| US8283697B2 (en) | 2009-12-04 | 2012-10-09 | Fuji Electric Co., Ltd. | Internal combustion engine igniter semiconductor device |
| CN104103682A (en) * | 2013-04-09 | 2014-10-15 | 比亚迪股份有限公司 | IGBT with novel buffer layer structure and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3243902B2 (en) | Semiconductor device | |
| JP2942732B2 (en) | Shorted anode horizontal insulated gate bipolar transistor | |
| JP2020053466A (en) | Semiconductor device | |
| JP3356644B2 (en) | Driving method of semiconductor rectifier | |
| JP2862027B2 (en) | Insulated gate bipolar transistor | |
| JP2008021981A (en) | Insulated gate bipolar transistor, and method for manufacturing it | |
| US5079607A (en) | Mos type semiconductor device | |
| US7034357B2 (en) | Insulated gate semiconductor device | |
| KR100490801B1 (en) | Power semiconductor device manufacturing method | |
| JP2946750B2 (en) | Semiconductor device | |
| JPH06268226A (en) | Insulated gate bipolar transistor | |
| JP3226075B2 (en) | Vertical MOS semiconductor device | |
| US6388306B1 (en) | Semiconductor device with rapid reverse recovery characteristic | |
| JPH06318706A (en) | Semiconductor device | |
| JP2004088012A (en) | Diode | |
| JPH0693511B2 (en) | Insulated gate semiconductor device | |
| JPS6153877B2 (en) | ||
| JP3216315B2 (en) | Insulated gate bipolar transistor | |
| Chow et al. | The effect of substrate doping on the performance of anode-shorted n-channel lateral insulated-gate bipolar transistors | |
| JPH05114737A (en) | Conductivity modulated mosfet | |
| US7067900B2 (en) | Insulated gate bipolar transistor having a reduced tail current and method of fabricating the same | |
| US20050110076A1 (en) | Insulated gate bipolar transistor and method of fabricating the same | |
| JPS6123667B2 (en) | ||
| JP2637173B2 (en) | Semiconductor device | |
| JPH06163908A (en) | Double gate mos device |