JPH06268207A - Insulated gate type power semiconductor device - Google Patents
Insulated gate type power semiconductor deviceInfo
- Publication number
- JPH06268207A JPH06268207A JP4953393A JP4953393A JPH06268207A JP H06268207 A JPH06268207 A JP H06268207A JP 4953393 A JP4953393 A JP 4953393A JP 4953393 A JP4953393 A JP 4953393A JP H06268207 A JPH06268207 A JP H06268207A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- impurity diffusion
- conductivity
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 239000012535 impurity Substances 0.000 abstract description 88
- 238000009792 diffusion process Methods 0.000 abstract description 77
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 239000010410 layer Substances 0.000 description 252
- 238000010586 diagram Methods 0.000 description 9
- 108091006146 Channels Proteins 0.000 description 8
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 4
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 4
- 239000000969 carrier Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電力用半導体素子に係
り、特に絶縁ゲート型電力用半導体素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly to an insulated gate power semiconductor device.
【０００２】[0002]
【従来の技術】近年、コンピュータや通信機器の重要部
分には、多数のトランジスタや抵抗等を電気回路を達成
するようにむすびつけ、１チップ上に集積化して形成し
た集積回路（ＩＣ）が多用されている。このようなＩＣ
中で、高耐圧素子を含むものはパワーＩＣと呼ばれてい
る。2. Description of the Related Art In recent years, an integrated circuit (IC) formed by integrating a large number of transistors, resistors and the like so as to achieve an electric circuit and forming them on one chip has been widely used in important parts of computers and communication equipment. ing. IC like this
Among them, a device including a high breakdown voltage element is called a power IC.
【０００３】高耐圧素子の一つとして従来よりＥＳＴ
（Emitter Switched Tyhristor）と呼ばれる絶縁ゲート
型電力用半導体素子が知られている（B.J.Baliga,Proce
eding.of 1990 Ineternational Symposium on Power Se
miconductor Devices &ICs p.117-121）。図７は、従来
のＥＳＴの構造を示す図、同図（ａ）は平面図を示し、
同図（ｂ）は同図（ａ）のＥＳＴのＦ−Ｆ´断面図を示
している。Conventionally, EST has been used as one of the high breakdown voltage elements.
An insulated gate type power semiconductor device called (Emitter Switched Tyhristor) is known (BJBaliga, Proce
eding.of 1990 Ineternational Symposium on Power Se
miconductor Devices & ICs p.117-121). FIG. 7 is a diagram showing a structure of a conventional EST, FIG. 7 (a) is a plan view,
FIG. 16B shows a cross-sectional view of the EST shown in FIG.
【０００４】このＥＳＴは、Ｎ型ベース層８１と、この
Ｎ型ベース層８１の一方の表面に形成され、不純物濃度
が高いＰ+ 型エミッタ層８３と、Ｎ型ベース層８１の他
方の表面に選択的に形成されたＰ型ベース層８２と、こ
のＰ型ベース層８２の表面に選択的に形成され、不純物
濃度が高いＮ+ 型エミッタ層８４とを有している。これ
ら半導体層８１，８３，８２，８４によりＰＮＰＮサイ
リスタ構造が形成されている。更に、Ｐ型ベース層８２
の表面には不純物濃度が高いＰ+ 型不純物拡散層９１が
選択され、このＰ+ 型不純物拡散層９１の表面の一部か
らＰ型ベース層８２の表面にかけては不純物濃度が高い
Ｎ+ 型不純物拡散層８５が選択的に形成されている。The EST is formed on the N-type base layer 81 and one surface of the N-type base layer 81, and has a high impurity concentration P +. -Type emitter layer 83, P-type base layer 82 selectively formed on the other surface of N-type base layer 81, and N + having a high impurity concentration formed selectively on the surface of P-type base layer 82. And a type emitter layer 84. These semiconductor layers 81, 83, 82, 84 form a PNPN thyristor structure. Further, the P-type base layer 82
Surface has a high impurity concentration of P + The type impurity diffusion layer 91 is selected, and the P + From the part of the surface of the type impurity diffusion layer 91 to the surface of the P-type base layer 82, N + having a high impurity concentration is formed. The type impurity diffusion layer 85 is selectively formed.
【０００５】また、Ｎ+ 型エミッタ層８４とＮ+ 型不純
物拡散層８５と間のＰ型ベース層８２上にはゲート絶縁
膜８６を介してゲート電極８７が配設されている。更
に、Ｐ型エミッタ層８３の表面にはアノード電極８９が
配設され、そして、Ｎ+ 型不純物拡散層８５およびＰ+
型不純物拡散層９１にコンタクトするカソード電極８８
がゲート絶縁膜９０を介してゲート電極８７と隣接して
配設されている。In addition, N + Type emitter layer 84 and N + A gate electrode 87 is provided on the P-type base layer 82 between the type impurity diffusion layer 85 and the gate insulating film 86. Further, an anode electrode 89 is provided on the surface of the P-type emitter layer 83, and N + -Type impurity diffusion layer 85 and P +
Type cathode 88 that contacts the impurity diffusion layer 91
Are disposed adjacent to the gate electrode 87 via the gate insulating film 90.
【０００６】このように構成されたＥＳＴをターンオン
するには、アノード電極８９，カソード電極８８にそれ
ぞれ正電圧，負電圧を印加した状態で、ゲート電極８７
に正電圧を印加する。In order to turn on the EST thus constructed, the gate electrode 87 is applied with a positive voltage and a negative voltage applied to the anode electrode 89 and the cathode electrode 88, respectively.
Apply a positive voltage to.
【０００７】このような電圧が印加されると、ゲート電
極８７の下部のＰ型ベース層８２の表面にＮ型チャネル
が形成され、Ｎ+ 型エミッタ層８４とカソード電極８８
とが短絡される。この状態にて、図示はされていない
が、例えば、ｐ型ベース層８２の端部に設けられたオン
用ＭＯＳＦＥＴによりトリガ電圧を与えると、Ｎ+ 型エ
ミッタ層８４からＮ型ベース層８１に電子が注入され、
Ｐ+ 型エミッタ層８３からＰ型ベース層８２に正孔が注
入される。このような電子，正孔の流れによって半導体
層８１，８３，８２，８４で構成されたサイリスタがタ
ーンオンする。一方、ターンオフにするには、ゲート電
極８７に負電圧を印加して上記Ｎ型チャネルを消滅さ
せ、Ｎ+ 型エミッタ層８４への電子の供給を遮断すれば
良い。しかしながら、この種のＥＳＴには次のような問
題があった。When such a voltage is applied, an N-type channel is formed on the surface of the P-type base layer 82 below the gate electrode 87, and N + Type emitter layer 84 and cathode electrode 88
And are short-circuited. In this state, although not shown, for example, when a trigger voltage is applied by an ON MOSFET provided at the end of the p-type base layer 82, N + Electrons are injected into the N type base layer 81 from the type emitter layer 84,
P + Holes are injected from the type emitter layer 83 to the P type base layer 82. The thyristor formed of the semiconductor layers 81, 83, 82 and 84 is turned on by the flow of the electrons and holes. On the other hand, to turn off, a negative voltage is applied to the gate electrode 87 to extinguish the N-type channel, and N + The supply of electrons to the type emitter layer 84 may be cut off. However, this kind of EST has the following problems.
【０００８】素子内の正孔は、ターンオフの際に、Ｎ+
型不純物拡散層８５の下部のＰ+ 型不純物拡散層９１を
通ってカソード電極８８から素子外に排出される。この
ような正孔の流れ（ホール電流）によりＰ+ 型不純物拡
散層９１に電圧降下が生じるため、Ｐ+ 型不純物拡散層
９１の電位がＮ+ 型不純物拡散層８５のそれより高くな
る。このため、メインのサイリスタがオフ状態であって
も、Ｎ+ 型不純物拡散層８５からＮ型ベース層８１に電
子が注入され、半導体層８１，８３，８５，９１で構成
された寄生サイリスタがラッチアップし、アノード・カ
ソード間に電流が流れ続けるという問題があった。The holes in the device are N + + when turned off.
Lower type impurity diffusion layer 85 of the P + It is discharged from the cathode electrode 88 to the outside of the element through the type impurity diffusion layer 91. Due to such hole flow (hole current), P + Since a voltage drop occurs in the type impurity diffusion layer 91, P + -Type impurity diffusion layer 91 has a potential of N + It is higher than that of the type impurity diffusion layer 85. Therefore, even if the main thyristor is off, N + Electrons are injected into the N-type base layer 81 from the n-type impurity diffusion layer 85, the parasitic thyristor composed of the semiconductor layers 81, 83, 85, 91 latches up, and a current continues to flow between the anode and the cathode. It was
【０００９】このような寄生サイリスタのラッチアップ
は、Ｎ+ 型不純物拡散層８５のチャネル方向の寸法を小
さくすれば、Ｎ+ 型不純物拡散層８５の下部におけるＰ
型ベース層８２の電圧降下が小さくなるので防止でき
る。しかしながら、この場合、Ｎ+ 型不純物拡散層８５
とカソード電極８８とのコンタクト面積が小さくなるの
で、オン抵抗が大きくなるという問題があった。The latch-up of such a parasitic thyristor is N + If the dimension of the impurity diffusion layer 85 in the channel direction is reduced, N + At the bottom of the impurity diffusion layer 85
This can be prevented because the voltage drop of the mold base layer 82 becomes small. However, in this case N + Type impurity diffusion layer 85
Since the contact area between the cathode electrode 88 and the cathode electrode 88 is small, there is a problem that the on-resistance increases.
【００１０】[0010]
【発明が解決しようとする課題】上述の如く、従来のＥ
ＳＴにあっては、ターンオフの際に、Ｎ+ 型不純物拡散
層の下部のｐ+ 型不純物拡散層に電圧降下が生じる結
果、寄生サイリスタがラッチアップし、オフ駆動ができ
なくなるという問題があった。この問題を解決するため
に、Ｎ+ 型不純物拡散層のチャネル方向の寸法を小さく
するという手法が提案されたが、この場合、Ｎ+ 型不純
物拡散層とカソード電極８８とのコンタクト面積が小さ
くなり、オン抵抗が大きくなるという問題があった。As described above, the conventional E
In ST, when turning off, N + P + under the impurity diffusion layer As a result of the voltage drop in the type impurity diffusion layer, the parasitic thyristor is latched up, and the OFF drive cannot be performed. To solve this problem, N + A method of reducing the dimension of the impurity diffusion layer in the channel direction has been proposed. In this case, N + There is a problem that the contact area between the type impurity diffusion layer and the cathode electrode 88 is reduced, and the on-resistance is increased.
【００１１】本発明は、上記事情を考慮してなされたも
ので、その目的とするところは、オン抵抗の増加を招か
ずに寄生サイリスタのラッチアップを防止できる絶縁ゲ
ート型電力用半導体素子を提供することにある。The present invention has been made in consideration of the above circumstances, and an object thereof is to provide an insulated gate type power semiconductor element capable of preventing latch-up of a parasitic thyristor without increasing the on-resistance. To do.
【００１２】[0012]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の絶縁ゲート型電力用半導体素子は、１導
電型エミッタ層に接した第２導電型ベース層と、この第
２導電型ベース層に接した第１導電型ベース層と、この
第１導電型ベース層の表面に選択的に形成された第２導
電型エミッタ層と、この第２導電型エミッタ層とは別に
前記第１導電型ベース層の表面に選択的に形成された第
１の第１導電型半導体層と、この第１の第１導電型半導
体層の表面の一部から、前記第２導電型エミッタ層側の
前記第１導電型ベース層の表面にまたがって形成された
第２導電型半導体層と、この第２導電型半導体層と前記
第２導電型エミッタ層との間の前記第１導電型ベース層
上にゲート絶縁膜を介して設けられたゲート電極と、こ
のゲート電極と電気的に分離され、前記第２導電型半導
体層に設けられた第１の主電極と、前記第１導電型エミ
ッタ層に設けられた第２の主電極とを有する絶縁ゲート
型電力用半導体素子において、前記第２導電型半導体層
内に設けられ、且つ前記第１の第１導電型半導体層およ
び前記第１の主電極に接した第２の第１導電型半導体
層、並びに前記第２導電型エミッタ層内に設けられ、且
つ前記第１導電型ベース層および前記第１の主電極に接
続した第２の第１導電型半導体層の少なくとも一方の前
記第２の第１導電型半導体層を有することを特徴とするIn order to achieve the above object, an insulated gate power semiconductor device of the present invention comprises a second conductivity type base layer in contact with a one conductivity type emitter layer and a second conductivity type base layer. The first conductivity type base layer in contact with the first conductivity type base layer, the second conductivity type emitter layer selectively formed on the surface of the first conductivity type base layer, and the second conductivity type emitter layer separately from the first conductivity type base layer. A first first-conductivity-type semiconductor layer selectively formed on the surface of the first-conductivity-type base layer, and a portion of the surface of the first first-conductivity-type semiconductor layer from the second-conductivity-type emitter layer side. Second conductive type semiconductor layer formed over the surface of the first conductive type base layer, and the first conductive type base layer between the second conductive type semiconductor layer and the second conductive type emitter layer. The gate electrode provided above the gate insulating film and the gate electrode and the electrode. Insulated gate type power semiconductor device having a first main electrode provided in the second conductivity type semiconductor layer and a second main electrode provided in the first conductivity type emitter layer A second conductive type semiconductor layer provided in the second conductive type semiconductor layer and in contact with the first first conductive type semiconductor layer and the first main electrode, and the second conductive type It has the second first-conductivity-type semiconductor layer which is provided in the emitter layer and is connected to the first-conductivity-type base layer and the first main electrode and at least one of the second first-conductivity-type semiconductor layers. Characterized by
【００１３】ここで、上記第２導電型半導体層内に設け
られた第２の第１導電型半導体層は、第１の第１導電型
半導体層と同一のものでも良いし、また、第１の第１導
電型半導体層とは別の第２の第１導電型半導体層であっ
ても良い。同様に、上記第２導電型エミッタ層内に設け
られた第２の第１導電型半導体層は、第１導電型ベース
層と同一のものでも良いし、また、第１導電型ベース層
とは別の第２の第１導電型半導体層であっても良い。Here, the second first-conductivity-type semiconductor layer provided in the second-conductivity-type semiconductor layer may be the same as the first first-conductivity-type semiconductor layer or the first first-conductivity-type semiconductor layer. It may be a second first-conductivity-type semiconductor layer different from the first-conductivity-type semiconductor layer. Similarly, the second first-conductivity-type semiconductor layer provided in the second-conductivity-type emitter layer may be the same as the first-conductivity-type base layer or the first-conductivity-type base layer. It may be another second first conductivity type semiconductor layer.
【００１４】また、上記第２導電型半導体層内に設けら
れた第２の第１導電型半導体層は、単数でも複数でも良
い。同様に、上記第２導電型エミッタ層内に設けられた
第２の第１導電型半導体層も、単数でも複数でも良い。Further, the second semiconductor layer of the first conductivity type provided in the semiconductor layer of the second conductivity type may be a single layer or a plurality of layers. Similarly, the number of second semiconductor layers of the first conductivity type provided in the emitter layer of the second conductivity type may be single or plural.
【００１５】[0015]
【作用】本発明の絶縁ゲート型電力用半導体素子は、第
１の第１導電型半導体層および第１の主電極と接した第
２の第１導電型半導体層、並びに第２導電型エミッタ層
内に設けられ、且つ第１導電型ベース層および第１の主
電極に接続した第２の第１導電型半導体層の少なくとも
一方の第２の第１導電型半導体層を備えている。すなわ
ち、第２導電型半導体層は第２の第１導電型半導体層に
より複数の領域に分けられるか、又は第２導電型エミッ
タ層は第２の第１導電型半導体層により複数の領域に分
けられるか、又は第２導電型半導体層および第２導電型
エミッタ層は第１導電型半導体層により複数の領域に分
けられる。The insulated gate power semiconductor device of the present invention comprises a second first conductivity type semiconductor layer in contact with the first first conductivity type semiconductor layer and the first main electrode, and a second conductivity type emitter layer. A second first-conductivity-type semiconductor layer that is provided inside and is connected to the first-conductivity-type base layer and the first main electrode is at least one of the second first-conductivity-type semiconductor layers. That is, the second conductive type semiconductor layer is divided into a plurality of regions by the second first conductive type semiconductor layer, or the second conductive type emitter layer is divided into a plurality of regions by the second first conductive type semiconductor layer. Alternatively, the second conductive type semiconductor layer and the second conductive type emitter layer are divided into a plurality of regions by the first conductive type semiconductor layer.
【００１６】ここで、第２導電型半導体層が第２の第１
導電型半導体層により複数の領域に分けられている場合
には、ターンオフ時における個々の領域の第２導電型半
導体層の下部の第１の第１導電型半導体層内におけるキ
ャリア（第１導電型エミッタ層の多数キャリア）の走行
距離は、いずれも第２の第１導電型半導体層が無い従来
の場合のそれに比べて小さいものとなる。Here, the second conductivity type semiconductor layer is the second first semiconductor layer.
When divided into a plurality of regions by the conductive type semiconductor layer, carriers (first conductive type) in the first conductive type semiconductor layer below the second conductive type semiconductor layer in each region at the time of turn-off are separated. The traveling distances of majority carriers in the emitter layer are smaller than those in the conventional case where the second semiconductor layer of the first conductivity type is not provided.
【００１７】このため、第１の主電極と第２導電型半導
体層とのコンタクト面積を大きくしても、ターンオフ時
における個々の領域の第２導電型半導体層の下部の第１
の第１導電型半導体層の電圧降下は、いずれも第２の第
１導電型半導体層が無い従来の場合のそれに比べて小さ
いものとなる。Therefore, even if the contact area between the first main electrode and the second conductive type semiconductor layer is increased, the first conductive layer below the second conductive type semiconductor layer in each region is turned off.
The voltage drop of the first conductivity type semiconductor layer is smaller than that in the conventional case where the second first conductivity type semiconductor layer is not provided.
【００１８】したがって、オン抵抗の増加を招くこと無
く、第１導電型エミッタ層，第２導電型ベース層，第１
導電型ベース層および第１の第１導電型半導体層で構成
された寄生サイリスタのラッチアップを防止できる。Therefore, the first conductivity type emitter layer, the second conductivity type base layer, the first conductivity type emitter layer
It is possible to prevent the parasitic thyristor composed of the conductive type base layer and the first first conductive type semiconductor layer from latching up.
【００１９】[0019]
【実施例】以下、図面を参照しながら実施例を説明す
る。Embodiments will be described below with reference to the drawings.
【００２０】図１は、本発明の第１の実施例に係るＥＳ
Ｔの構造を示す図であり、同図（ａ）は平面図を示し、
同図（ｂ）は同図（ａ）のＥＳＴのＡ−Ａ´断面図を示
している。FIG. 1 shows an ES according to the first embodiment of the present invention.
It is a figure which shows the structure of T, The figure (a) shows a top view,
The figure (b) has shown the AA 'cross section figure of EST of the figure (a).
【００２１】図中、１はＮ型ベース層１（第２導電型ベ
ース層）を示しており、このＮ型ベース層１の一方の表
面には不純物濃度が高いＰ+ 型エミッタ層３（第１導電
型エミッタ層）が接し、このＰ+ 型エミッタ層３にはア
ノード電極９（第２の主電極）が設けられている。ま
た、Ｎ型ベース層１の他方の表面にはＰ型ベース層２
（第１導電型ベース層）が接しており、このＰ型ベース
層２の表面には不純物濃度が高いＮ+ 型エミッタ層４
（第２導電型エミッタ層）が選択的に形成されている。
更に、不純物濃度が高いＰ+ 型不純物拡散層１０（第１
の第１導電型半導体層）がＰ型ベース層２の表面にＮ+
型エミッタ層４と別に選択的に形成されている。In the figure, reference numeral 1 denotes an N-type base layer 1 (second conductivity type base layer), and one surface of the N-type base layer 1 is P + having a high impurity concentration. Type emitter layer 3 (first conductivity type emitter layer) is in contact with this P + The mold emitter layer 3 is provided with an anode electrode 9 (second main electrode). The P-type base layer 2 is formed on the other surface of the N-type base layer 1.
(First conductivity type base layer) is in contact with the surface of the P type base layer 2 and N + having a high impurity concentration Type emitter layer 4
(Second conductivity type emitter layer) is selectively formed.
Furthermore, P + with high impurity concentration Type impurity diffusion layer 10 (first
First conductive type semiconductor layer) of N + on the surface of the P type base layer 2
It is selectively formed separately from the mold emitter layer 4.
【００２２】上記Ｐ+ 型不純物拡散層１０の表面の一部
からＰ型ベース層２の表面にかけては不純物濃度が高い
Ｎ+ 型不純物拡散層５（第２導電型半導体層）が選択的
に形成され、このＮ+ 型不純物拡散層５内にはＰ+ 型不
純物拡散層１０およびカソード電極８（第１の主電極）
に接する複数の不純物濃度が高いＰ+ 型不純物拡散層１
２（第２の第１導電型半導体層）が設けられている。す
なわち、カソード電極８はＮ+ 型不純物拡散層５にコン
タクトするとともに、Ｐ+ 型不純物拡散層１２を介して
Ｐ+ 型不純物拡散層１０にもコンタクトしている。The above P + From the part of the surface of the p-type impurity diffusion layer 10 to the surface of the p-type base layer 2, the impurity concentration of N + is high . Type impurity diffusion layer 5 (second conductivity type semiconductor layer) is selectively formed, and this N + In the impurity diffusion layer 5 of the type, P + -Type impurity diffusion layer 10 and cathode electrode 8 (first main electrode)
P + with a high concentration of impurities Type impurity diffusion layer 1
2 (second first conductivity type semiconductor layer) is provided. That is, the cathode electrode 8 is N + Contact with the impurity diffusion layer 5 of the type, and P + P + via the impurity diffusion layer 12 The type impurity diffusion layer 10 is also contacted.
【００２３】更に、図１（ｂ）に示すように、Ｐ+ 型不
純物拡散層１２により分けられた個々の領域のＮ+ 型不
純物拡散層５のチャネル方向の寸法Ｌは、ホール電流に
よって生じる個々のＮ+ 型不純物拡散層５の下部のＰ+
型不純物拡散層１０の電圧降下が、Ｐ+ 型不純物拡散層
１０とＮ+ 型不純物拡散層５とで形成されるＰＮ接合の
ビルトイン電圧よりも小さくなるように選ばれている。
また、Ｎ+ 型不純物拡散層５のチャネル方向の寸法は、
ゲート電極７から離れほど小さくする。Further, as shown in FIG. 1 (b), P + Individual regions of N which are divided by type impurity diffusion layer 12 + The dimension L of the impurity diffusion layer 5 in the channel direction is determined by the individual N + generated by the hole current. Of P + under the impurity diffusion layer 5
The voltage drop of the impurity diffusion layer 10 is P + -Type impurity diffusion layer 10 and N + It is selected to be smaller than the built-in voltage of the PN junction formed with the type impurity diffusion layer 5.
Also, N + The dimension of the type impurity diffusion layer 5 in the channel direction is
The smaller the distance from the gate electrode 7, the smaller.
【００２４】このようなＰ+ 型不純物拡散層１２は、例
えば、Ｐ+ 型不純物拡散層１０を形成した後、Ｎ型不純
物をＰ+ 型不純物拡散層１０に選択的に拡散して形成し
たり、Ｐ+ 型不純物拡散層１０を形成し、更に、このＰ
+ 型不純物拡散層１０の表面全体にＮ+ 型不純物拡散層
５を形成した後、Ｐ型不純物をＮ+ 型不純物拡散層５に
選択的に拡散して形成しても良い。すなわち、Ｐ+ 型不
純物拡散層１２とＰ+ 型不純物拡散層１０とはもともと
同じものであっても良いし、別工程で形成されたもので
あっても良い。Such a P+ Type impurity diffusion layer 12 is an example
For example, P+ After forming the impurity diffusion layer 10, the N-type impurity
Thing P+ Formed by selectively diffusing into the type impurity diffusion layer 10.
Or P+ A type impurity diffusion layer 10 is formed, and further P
+ N on the entire surface of the impurity diffusion layer 10+ Type impurity diffusion layer
5 is formed, P-type impurities are added to N+ Type impurity diffusion layer 5
It may be selectively diffused and formed. That is, P+ Typeless
Pure substance diffusion layer 12 and P+ Type impurity diffusion layer 10 originally
It may be the same, or it may be formed in a separate process.
It may be.
【００２５】また、Ｎ+ 型エミッタ層４とＮ+ 型不純物
拡散層５との間のＰ型ベース層２上にはゲート絶縁膜６
を介してゲート電極７が配設されている。このゲート電
極７は絶縁膜１１によりカソード電極と電気的に分離さ
れている。Also, N + Type emitter layer 4 and N + On the P-type base layer 2 between the gate-type impurity diffusion layer 5 and the gate-type impurity diffusion layer 5.
The gate electrode 7 is provided via the. The gate electrode 7 is electrically separated from the cathode electrode by the insulating film 11.
【００２６】このように構成されたＥＳＴをターンオン
するには、アノード電極９，カソード電極８にそれぞれ
正電圧，負電圧を印加した状態で、ゲート電極７に正電
圧を印加する。To turn on the EST having the above structure, a positive voltage is applied to the gate electrode 7 while a positive voltage and a negative voltage are applied to the anode electrode 9 and the cathode electrode 8, respectively.
【００２７】このような電圧が印加されると、ゲート電
極７の下部のＰ型ベース層２の表面にＮ型チャネルが形
成され、Ｎ+ 型エミッタ層４とカソード電極８とが短絡
される。この状態にて、図示はされていないが、例え
ば、ｐ型ベース層２の端部に設けられたオン用ＭＯＳＦ
ＥＴによりトリガ電圧を与えると、Ｎ+ 型エミッタ層４
からＮ型ベース層１に電子が注入され、Ｐ+ 型エミッタ
層３からＰ型ベース層２に正孔が注入される。When such a voltage is applied, an N-type channel is formed on the surface of the P-type base layer 2 below the gate electrode 7, and N + The mold emitter layer 4 and the cathode electrode 8 are short-circuited. In this state, although not shown, for example, an on-state MOSF provided at the end of the p-type base layer 2 is provided.
When a trigger voltage is given by ET, N + Type emitter layer 4
Electrons are injected into the N-type base layer 1 from P + Holes are injected from the type emitter layer 3 to the P-type base layer 2.
【００２８】このような電子，正孔の流れによって、Ｐ
+ 型エミッタ層３，Ｎ型ベース層１およびＰ型ベース層
２で構成されたトランジスタと、Ｎ型ベース層１，Ｐ型
ベース層２およびＮ型エミッタ層４で構成されたトラン
ジスタとが互いのコレクタ電流を増幅し合う結果、半導
体層１，２，３，４で構成されたサイリスタがターンオ
ンする。Due to such a flow of electrons and holes, P
+ Type emitter layer 3, N-type base layer 1 and P-type base layer 2 and a transistor formed of N-type base layer 1, P-type base layer 2 and N-type emitter layer 4 are collectors of each other. As a result of mutually amplifying the currents, the thyristors formed of the semiconductor layers 1, 2, 3, 4 are turned on.
【００２９】一方、ターンオフにするには、ゲート電極
７に負電圧を印加して上記Ｎ型チャネルを消滅させ、Ｎ
+ 型エミッタ層４への電子の供給を遮断すれば良い。こ
のとき、素子内に蓄積されていた正孔は、Ｎ+ 型不純物
拡散層５下部のＰ+ 型不純物拡散層１０を通った後、Ｐ
+ 型不純物拡散層１２を通ってカソード電極８から素子
外に排出される。On the other hand, to turn off, a negative voltage is applied to the gate electrode 7 to extinguish the N-type channel,
+ The supply of electrons to the mold emitter layer 4 may be cut off. At this time, the holes accumulated in the element are N + Of P + under the impurity diffusion layer 5 After passing through the type impurity diffusion layer 10, P
+ It is discharged from the cathode electrode 8 to the outside of the device through the type impurity diffusion layer 12.
【００３０】ここで、個々の領域のＮ+ 型不純物拡散層
５のチャネル方向の寸法Ｌは、上述した条件の寸法に選
んであるので、Ｐ+ 型不純物拡散層１０内にホール電流
が流れても、Ｎ+ 型不純物拡散層５からＮ型ベース層１
に電子が注入されることはない。このため、ターンオフ
時に半導体層１，３，５，１０で構成された寄生サイリ
スタがラッチアップし、アノード・カソード間に電流が
流れ続けるという問題は生じない。Here, N + of each region The dimension L in the channel direction of the type impurity diffusion layer 5 is selected according to the above-mentioned conditions, and therefore P + Even if a hole current flows in the impurity diffusion layer 10, the N + Type impurity diffusion layer 5 to N type base layer 1
No electrons are injected into. Therefore, there is no problem that the parasitic thyristor composed of the semiconductor layers 1, 3, 5, 10 latch up at the time of turn-off, and the current continues to flow between the anode and the cathode.
【００３１】また、個々の領域のＮ+ 型不純物拡散層５
とカソード電極８とのコンタクト面積は小さいものとな
るが、全体としては大きいものとなるので、Ｎ+ 型不純
物拡散層５とカソード電極８とのコンタクト抵抗が増加
するという問題は生じない。以上述べたように本実施例
によれば、Ｎ+ 型不純物拡散層５内にカソード電極８お
よびＰ+ 型不純物拡散層１０に接するＰ+ 型不純物拡散
層１２を設けて、各領域のＮ+ 型不純物拡散層５のチャ
ネル方向の寸法を従来より短くすることにより、コンタ
クト抵抗の増加を招くこと無く、寄生サイリスタのラッ
チアップを防止できる。なお、本実施例では、Ｐ+ 型不
純物拡散層１０を設けたがＰ+ 型不純物拡散層１２の分
布を適当に選ぶことにより省くことも可能である。In addition, N + of each area Type impurity diffusion layer 5
The contact area between the cathode electrode 8 and the cathode electrode 8 is small, but it is large as a whole, so N + The problem that the contact resistance between the type impurity diffusion layer 5 and the cathode electrode 8 increases does not occur. As described above, according to this embodiment, N + In the impurity diffusion layer 5 of cathode type and P + P + in contact with the impurity diffusion layer 10 By providing the type impurity diffusion layer 12, N + of each region is By making the dimension of the type impurity diffusion layer 5 in the channel direction shorter than in the conventional case, latch-up of the parasitic thyristor can be prevented without causing an increase in contact resistance. In this embodiment, P + Type impurity diffusion layer 10 is provided, but P + It is also possible to omit it by appropriately selecting the distribution of the type impurity diffusion layer 12.
【００３２】図２は、本発明の第２の実施例に係るＥＳ
Ｔの構造を示す図であり、同図（ａ）は平面図を示し、
同図（ｂ）は同図（ａ）のＥＳＴのＢ−Ｂ´断面図を示
している。なお、以下の実施例で参照する図において、
図１のＥＳＴと対応する部分には図１と同一符号を付
し、詳細な説明は省略する。FIG. 2 shows an ES according to the second embodiment of the present invention.
It is a figure which shows the structure of T, The figure (a) shows a top view,
FIG. 11B shows a cross-sectional view of the EST of FIG. In the drawings referred to in the following examples,
The parts corresponding to the EST in FIG. 1 are assigned the same reference numerals as those in FIG. 1, and detailed description thereof will be omitted.
【００３３】本実施例のＥＳＴが先の実施例のそれと主
として異なる点は、Ｎ+ 型不純物拡散層５でなく、Ｎ+
型エミッタ層４内に不純物濃度が高いＰ+ 型不純物拡散
層１３を設けたことにある。また、カソード電極８はＮ
+ 型エミッタ層４側まで延在しており、更に、この延在
したカソード電極８はＮ+ 型エミッタ層４にコンタクト
しないようにＰ+ 型不純物拡散層１３上に開口部が形成
された絶縁膜を介してＰ+ 型不純物拡散層１３にコンタ
クトしている。The EST of this embodiment is mainly the same as that of the previous embodiment.
Is different from N+ Type impurity diffusion layer 5, not N+
P with a high impurity concentration in the emitter layer 4+ Type impurity diffusion
The layer 13 is provided. In addition, the cathode electrode 8 is N
+ Type emitter layer 4 side, and this extension
The cathode electrode 8 is N+ Type emitter layer 4 contact
Do not do P+ An opening is formed on the type impurity diffusion layer 13.
Through the insulating film+ Type impurity diffusion layer 13
I am working.
【００３４】このように構成されたＥＳＴによれば、タ
ーンオフ時における正孔の排出経路は、Ｐ+ 型エミッタ
層３，Ｎ型ベース層１，Ｐ+ 型不純物拡散層１０，カソ
ード電極８という従来の排出経路の他に、Ｐ+ 型エミッ
タ層３，Ｎ型ベース層１，Ｐ型ベース層２，Ｐ+ 型不純
物拡散層１３，カソード電極８という排出経路が追加さ
れる。According to the EST thus constructed, the hole discharge path at the time of turn-off is P +. Type emitter layer 3, N type base layer 1, P + Type impurity diffusion layer 10 and cathode electrode 8 in addition to the conventional discharge path, P + Type emitter layer 3, N type base layer 1, P type base layer 2, P + A discharge route including the type impurity diffusion layer 13 and the cathode electrode 8 is added.
【００３５】したがって、本実施例によれば、新たな排
出経路が増えた分だけＰ+ 型不純物拡散層１０に流れる
正孔の量が減少するので、ターンオフ時およびターンオ
ン時におけるＮ+ 型不純物拡散層５の下部のＰ+ 型不純
物拡散層１０の電圧降下が小さくなり、寄生サイリスタ
のラッチアップが起こり難くなる。また、オン状態のと
きは、新たな排出経路により、Ｎ+ 型エミッタ層４の下
部のＮ型ベース層１およびＰ型ベース層２中の正孔の密
度が高くなるので、オン抵抗が小さくなる。Therefore, according to this embodiment, P + is increased by the number of new discharge routes. Since the amount of holes flowing in the impurity diffusion layer 10 decreases, N + at turn-off and at turn-on Of P + under the impurity diffusion layer 5 The voltage drop of the type impurity diffusion layer 10 becomes small, and the latch-up of the parasitic thyristor hardly occurs. When it is on, N + Since the density of holes in the N-type base layer 1 and the P-type base layer 2 below the type emitter layer 4 becomes high, the on-resistance becomes small.
【００３６】図３は、本発明の第３の実施例に係るＥＳ
Ｔの構造を示す図であり、同図（ａ）は平面図を示し、
同図（ｂ）は同図（ａ）のＥＳＴのＣ−Ｃ´断面図を示
している。FIG. 3 shows an ES according to the third embodiment of the present invention.
It is a figure which shows the structure of T, The figure (a) shows a top view,
FIG. 11B shows a sectional view taken along the line CC ′ of the EST shown in FIG.
【００３７】本実施例のＥＳＴは図１のＥＳＴと図２の
ＥＳＴとを組み合わせたものとなっている。すなわち、
Ｎ+ 型不純物拡散層５，Ｎ+ 型エミッタ層４内にそれぞ
れＰ+ 型不純物拡散層１２，１３が設けられている。The EST of this embodiment is a combination of the EST of FIG. 1 and the EST of FIG. That is,
N + Type impurity diffusion layer 5, N + P + in the emitter layer 4 Type impurity diffusion layers 12 and 13 are provided.
【００３８】このように構成されたＥＳＴによれば、素
子内の電流密度が高くなって、Ｐ型ベース層２中を横方
向に流れるホール電流が増加した場合でも、Ｎ+ 型不純
物拡散層５からＮ型ベース層１への電子注入を招かずに
カソード電極８にホール電流を流すことができ、寄生サ
イリスタのラッチアップ耐量を大幅に増大させることが
可能となる。According to the EST constructed as described above, even when the current density in the element is increased and the hole current flowing in the P type base layer 2 in the lateral direction is increased, N + A hole current can be passed through the cathode electrode 8 without injecting electrons from the type impurity diffusion layer 5 into the N-type base layer 1, and the latch-up resistance of the parasitic thyristor can be significantly increased.
【００３９】図４は、本発明の第４の実施例に係るＥＳ
Ｔの構造を示す図であり、同図（ａ）は平面図を示し、
同図（ｂ）は同図（ａ）のＥＳＴのＤ−Ｄ´断面図を示
している。FIG. 4 shows an ES according to the fourth embodiment of the present invention.
It is a figure which shows the structure of T, The figure (a) shows a top view,
FIG. 16B shows a DD ′ cross-sectional view of the EST of FIG.
【００４０】本実施例のＥＳＴは図２のＥＳＴの一部を
変形したのもので、ゲート絶縁膜６とＮ型ベース層１と
の距離を縮めた例である。本実施例のＥＳＴによれば、
図２のＥＳＴに比べて、Ｐ型ベース層２中を横方向に流
れるホール電流が減少するので、寄生サイリスタのラッ
チアップ耐量が大きくなる。The EST of this embodiment is a modification of the EST of FIG. 2 and is an example in which the distance between the gate insulating film 6 and the N-type base layer 1 is shortened. According to the EST of this embodiment,
As compared with the EST shown in FIG. 2, since the hole current flowing in the P-type base layer 2 in the lateral direction is reduced, the latch-up resistance of the parasitic thyristor is increased.
【００４１】図５は、本発明の第５の実施例に係るＥＳ
Ｔの構造を示す図であり、同図（ａ）は平面図を示し、
同図（ｂ）は同図（ａ）のＥＳＴのＥ−Ｅ´断面図を示
している。FIG. 5 shows an ES according to the fifth embodiment of the present invention.
It is a figure which shows the structure of T, The figure (a) shows a top view,
FIG. 11B shows a cross-sectional view of the EST shown in FIG.
【００４２】本実施例のＥＳＴは図４のＥＳＴの一部を
変形したのもので、ゲート絶縁膜６とＮ型ベース層１と
が接している例である。本実施例のＥＳＴによれば、図
４のＥＳＴに比べて、Ｐ型ベース層２中を横方向に流れ
るホール電流が更に減少するので、寄生サイリスタのラ
ッチアップ耐量がより大きくなる。図６は、本発明の第
６の実施例に係るＩＧＢＴの構造を示す図である。本実
施例のＩＧＢＴが従来のそれと異なる点は、図２のＥＳ
Ｔの場合と同様に、Ｎ型エミッタ層４内にＰ+ 型不純物
拡散層１３が設けられてることにある。The EST of this embodiment is a modification of a part of the EST of FIG. 4, and is an example in which the gate insulating film 6 and the N-type base layer 1 are in contact with each other. According to the EST of the present embodiment, the hole current that flows laterally in the P-type base layer 2 is further reduced as compared with the EST of FIG. 4, so that the latch-up resistance of the parasitic thyristor becomes larger. FIG. 6 is a diagram showing the structure of the IGBT according to the sixth embodiment of the present invention. The IGBT of this embodiment is different from the conventional one in that the ES of FIG.
As in the case of T, P + in the N-type emitter layer 4 The type impurity diffusion layer 13 is provided.
【００４３】このように構成されたＩＧＢＴによれば、
チャネル総長の減少やチャネル抵抗を招かずに、Ｎ+ 型
エミッタ層４，Ｐ型ベース層２およびＮ型ベース層１で
構成された寄生トランジスタのラッチアップを防止でき
る。According to the IGBT thus constructed,
N + without reducing the total channel length or channel resistance It is possible to prevent the latch-up of the parasitic transistor formed of the type emitter layer 4, the P type base layer 2 and the N type base layer 1.
【００４４】[0044]
【発明の効果】以上詳述したように本発明によれば、第
２導電型半導体層内に設けられ、第１の第１導電型半導
体層および第１の主電極に接した第２の第１導電型半導
体層によって、第１の主電極と第２導電型半導体層との
コンタクト面積の低下を招くこと無く、ターンオフ時に
おける第２導電型半導体層の下部の第１の第１導電型半
導体層の電圧降下を小さくできるので、オン抵抗の増加
を招くこと無く寄生サイリスタのラッチアップの防止で
きる。As described above in detail, according to the present invention, the second conductive type semiconductor layer provided in the second conductive type semiconductor layer and in contact with the first first conductive type semiconductor layer and the first main electrode is provided. The first-conductivity-type semiconductor layer prevents the contact area between the first main electrode and the second-conductivity-type semiconductor layer from decreasing, and the first-first-conductivity-type semiconductor layer under the second-conductivity-type semiconductor layer is turned off. Since the voltage drop in the layers can be reduced, the latch-up of the parasitic thyristor can be prevented without increasing the on-resistance.
【図１】本発明の第１の実施例に係るＥＳＴの構造を示
す図。FIG. 1 is a diagram showing a structure of an EST according to a first embodiment of the present invention.
【図２】本発明の第２の実施例に係るＥＳＴの構造を示
す図。FIG. 2 is a diagram showing a structure of an EST according to a second embodiment of the present invention.
【図３】本発明の第３の実施例に係るＥＳＴの構造を示
す図。FIG. 3 is a diagram showing a structure of an EST according to a third embodiment of the present invention.
【図４】本発明の第４の実施例に係るＥＳＴの構造を示
す図。FIG. 4 is a diagram showing a structure of an EST according to a fourth embodiment of the present invention.
【図５】本発明の第５の実施例に係るＥＳＴの構造を示
す図。FIG. 5 is a diagram showing a structure of an EST according to a fifth embodiment of the present invention.
【図６】本発明の第６の実施例に係るＩＧＢＴの構造を
示す図。FIG. 6 is a diagram showing a structure of an IGBT according to a sixth embodiment of the present invention.
【図７】従来のＥＳＴの構造を示す図。FIG. 7 is a diagram showing a structure of a conventional EST.
１…Ｎ型ベース層（第２導電型ベース層） ２…Ｐ型ベース層（第１導電型ベース層） ３…Ｐ+ 型エミッタ層（第１導電型エミッタ層） ４…Ｎ+ 型エミッタ層（第２導電型エミッタ層） ５…Ｎ+ 型不純物拡散層（第２導電型半導体層） ６…ゲート絶縁膜 ７…ゲート電極 ８…カソード電極（第１の主電極） ９…アノード電極（第２の主電極） １０…Ｐ+ 型半導体層（第１の第１導電型半導体層） １１…絶縁膜 １２，１３…Ｐ+ 型半導体層（第２の第１導電型半導体
層）1 ... N-type base layer (second conductivity type base layer) 2 ... P-type base layer (first conductivity type base layer) 3 ... P + Type emitter layer (first conductivity type emitter layer) 4 ... N + Type emitter layer (second conductivity type emitter layer) 5 ... N + Type impurity diffusion layer (second conductivity type semiconductor layer) 6 ... Gate insulating film 7 ... Gate electrode 8 ... Cathode electrode (first main electrode) 9 ... Anode electrode (second main electrode) 10 ... P + Type semiconductor layer (first first conductivity type semiconductor layer) 11 ... Insulating film 12, 13, ... P + Type semiconductor layer (second first conductivity type semiconductor layer)
Claims (1)
ベース層と、 この第２導電型ベース層に接した第１導電型ベース層
と、 この第１導電型ベース層の表面に選択的に形成された第
２導電型エミッタ層と、 この第２導電型エミッタ層とは別に前記第１導電型ベー
ス層の表面に選択的に形成された第１の第１導電型半導
体層と、 この第１の第１導電型半導体層の表面の一部から、前記
第２導電型エミッタ層側の前記第１導電型ベース層の表
面にまたがって形成された第２導電型半導体層と、 この第２導電型半導体層と前記第２導電型エミッタ層と
の間の前記第１導電型ベース層上にゲート絶縁膜を介し
て設けられたゲート電極と、 このゲート電極と電気的に分離され、前記第２導電型半
導体層に設けられた第１の主電極と、 前記第１導電型エミッタ層に設けられた第２の主電極と
を有する絶縁ゲート型電力用半導体素子において、 前記第２導電型半導体層内に設けられ、且つ前記第１の
第１導電型半導体層および前記第１の主電極に接した第
２の第１導電型半導体層、並びに前記第２導電型エミッ
タ層内に設けられ、且つ前記第１導電型ベース層および
前記第１の主電極に接続した第２の第１導電型半導体層
の少なくとも一方の前記第２の第１導電型半導体層を有
することを特徴とする絶縁ゲート型電力用半導体素子。1. A second conductivity type base layer in contact with the first conductivity type emitter layer, a first conductivity type base layer in contact with the second conductivity type base layer, and a surface of the first conductivity type base layer. A second conductive type emitter layer selectively formed, and a first first conductive type semiconductor layer selectively formed on the surface of the first conductive type base layer separately from the second conductive type emitter layer A second conductivity type semiconductor layer formed so as to extend from a part of the surface of the first conductivity type semiconductor layer to the surface of the first conductivity type base layer on the side of the second conductivity type emitter layer, A gate electrode provided on the first conductive type base layer between the second conductive type semiconductor layer and the second conductive type emitter layer via a gate insulating film, and electrically isolated from the gate electrode. A first main electrode provided on the second conductivity type semiconductor layer; An insulated gate power semiconductor element having a second main electrode provided on a first emitter type semiconductor layer, wherein the first conductive type semiconductor layer and the first first conductive type semiconductor layer are provided in the second conductive type semiconductor layer. A second semiconductor layer of the first conductivity type which is in contact with the first main electrode, and a second layer which is provided in the second conductivity type emitter layer and is connected to the first conductivity type base layer and the first main electrode. 2. An insulated gate power semiconductor device having the second first-conductivity-type semiconductor layer of at least one of the first-conductivity-type semiconductor layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4953393A JPH06268207A (en) | 1993-03-10 | 1993-03-10 | Insulated gate type power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4953393A JPH06268207A (en) | 1993-03-10 | 1993-03-10 | Insulated gate type power semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06268207A true JPH06268207A (en) | 1994-09-22 |
Family
ID=12833807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4953393A Pending JPH06268207A (en) | 1993-03-10 | 1993-03-10 | Insulated gate type power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06268207A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100713904B1 (en) * | 2001-06-29 | 2007-05-07 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| CN109887992A (en) * | 2018-12-10 | 2019-06-14 | 章美云 | A kind of metal-oxide semiconductor (MOS) cutoff thyristor and preparation method thereof |
-
1993
- 1993-03-10 JP JP4953393A patent/JPH06268207A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100713904B1 (en) * | 2001-06-29 | 2007-05-07 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| CN109887992A (en) * | 2018-12-10 | 2019-06-14 | 章美云 | A kind of metal-oxide semiconductor (MOS) cutoff thyristor and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6724043B1 (en) | Bipolar MOSFET device | |
| JP3163820B2 (en) | Semiconductor device | |
| JPH04146674A (en) | Semiconductor device and manufacture thereof | |
| US5444273A (en) | MOSFET controlled thyristor | |
| US5498884A (en) | MOS-controlled thyristor with current saturation characteristics | |
| US5923055A (en) | Controllable semiconductor component | |
| JPH10173170A (en) | Semiconductor device | |
| US5298769A (en) | GTO thyristor capable of preventing parasitic thyristors from being generated | |
| US5463231A (en) | Method of operating thyristor with insulated gates | |
| US5925900A (en) | Emitter-switched thyristor having a floating ohmic contact | |
| US6111278A (en) | Power semiconductor devices having discontinuous emitter regions therein for inhibiting parasitic thyristor latch-up | |
| JP3338276B2 (en) | Power semiconductor device | |
| US5336907A (en) | MOS gate controlled thyristor having improved turn on/turn off characteristics | |
| JP3522983B2 (en) | Horizontal IGBT | |
| KR100316723B1 (en) | Power MOSFET having low on-resistance and high ruggedness | |
| US6803609B1 (en) | Bipolar high-voltage power component | |
| US5194927A (en) | Semiconductor device | |
| KR0163928B1 (en) | Emitter switch thrystor | |
| US6683348B1 (en) | Insulated gate bipolar semiconductor device transistor with a ladder shaped emitter | |
| JPH06268207A (en) | Insulated gate type power semiconductor device | |
| JP3300482B2 (en) | Thyristor with insulated gate | |
| JP3200328B2 (en) | Composite semiconductor device | |
| JP4407172B2 (en) | Horizontal insulated gate bipolar transistor | |
| JPH0758783B2 (en) | Conduction modulation type MOSFET | |
| JP3342944B2 (en) | Horizontal high voltage semiconductor device |