JPH06260577A - Coating structure of wiring electrode - Google Patents
Coating structure of wiring electrodeInfo
- Publication number
- JPH06260577A JPH06260577A JP4618893A JP4618893A JPH06260577A JP H06260577 A JPH06260577 A JP H06260577A JP 4618893 A JP4618893 A JP 4618893A JP 4618893 A JP4618893 A JP 4618893A JP H06260577 A JPH06260577 A JP H06260577A
- Authority
- JP
- Japan
- Prior art keywords
- plated layer
- palladium
- nickel
- plating
- thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置のリードフ
レームやバンプ電極の下地電極等の配線電極に関し、特
にこれら配線電極の基体を被覆する配線電極の被膜構造
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring electrode such as a lead frame of a semiconductor device or a base electrode of a bump electrode, and more particularly to a coating structure of a wiring electrode covering a base of these wiring electrodes.
【０００２】[0002]
【従来の技術】従来、半導体装置のプリント回路基板へ
の実装は、半導体装置の外郭体より突出するリードフレ
ームの外部リードやバンプ電極とプリント回路基板の導
電部材であるランド部とをはんだ接続することによって
行なわれていた。特にリードフレームの場合は、そのイ
ンナーリード部及びアイランド部の外表面に施されるめ
っき被膜と半導体装置の樹脂封止材との密着性、金属細
線とインナーリード部と接続するワイヤボンディング特
性及び樹脂外郭体から突出する外部リード部のはんだ付
け性がともに優れていることが求めれていた。2. Description of the Related Art Conventionally, a semiconductor device is mounted on a printed circuit board by soldering external leads or bump electrodes of a lead frame protruding from an outer casing of the semiconductor device and a land portion which is a conductive member of the printed circuit board. It was done by Particularly in the case of a lead frame, the adhesion between the plating film applied to the outer surface of the inner lead part and the island part and the resin encapsulant of the semiconductor device, the wire bonding characteristics and the resin for connecting the thin metal wire and the inner lead part It has been required that the external lead portions protruding from the outer shell have excellent solderability.
【０００３】図３（ａ）及び（ｂ）は配線電極の被膜構
造の従来技術の例をそれぞれ断面で示すリードフレーム
の部分図である。FIGS. 3 (a) and 3 (b) are partial views of a lead frame, each showing a cross section of a conventional example of a coating structure of a wiring electrode.
【０００４】図３（ａ）に示す構造は、特開平３一６２
５６０号公報に開示されていように、銅合金あるいはニ
ッケル鉄材料であるリードフレームのめっきすべき板部
材５の最外表面に直接あるいはニッケルめっき層を介し
て１０〜９０パーセント重量のパラジウムを含むパラジ
ウムと銀のＰｄ・Ａｇ合金を厚さ０．１乃至０．５μｍ
のめっきを薄くコーティングし、リードフレームの低廉
化とはんだ付け性を改善したものである。The structure shown in FIG. 3A is disclosed in Japanese Unexamined Patent Publication No. Hei 3-162.
As disclosed in Japanese Patent Laid-Open No. 560, palladium containing 10 to 90% by weight of palladium on the outermost surface of the plate member 5 of the lead frame to be plated, which is a copper alloy or a nickel-iron material, directly or through a nickel plating layer. And silver Pd-Ag alloy with a thickness of 0.1 to 0.5 μm
Is a thin coating of the lead frame, which reduces the cost of the lead frame and improves solderability.
【０００５】一方、図３（ｂ）に示す構造は、特開平３
一１０２８５８号公報に開示されているように、リード
フレームのうちワイヤボンディングざれる部分及び樹脂
封止される板部材５のみに錫とニッケルとのＳｎ・Ｎｉ
合金の一層目のめっきを施し、その上に直接あるいは銅
めっき層を介してパラジウムもしくはパラジウム基合金
であるＰｄ，Ｐｄ合金の膜を０．１乃至１．０μｍを施
している。そして、この被膜構造は、低廉化を図るとと
もにワイヤボンディング特性及び樹脂の密着性を改善し
たものがある。On the other hand, the structure shown in FIG.
As disclosed in Japanese Patent Laid-Open No. 102852/1990, Sn / Ni containing tin and nickel is formed only in a portion of the lead frame which is subject to wire bonding and the resin-sealed plate member 5.
A first layer of the alloy is plated, and a film of Pd or Pd alloy, which is palladium or a palladium-based alloy, is applied to the thickness of 0.1 to 1.0 μm directly or through the copper plating layer. In addition, this coating structure has a structure in which the cost is reduced and the wire bonding characteristics and the resin adhesion are improved.
【０００６】この外表面にパラジウムあるいはパラジウ
ム基合を被覆する被覆構造をもつリードフレームは、そ
のアイランド部に半導体チップが搭載され、半導体チッ
プとインナーリード部とを金線でワイヤボンディングし
てから樹脂封止して半導体装置に組込まれる。また、こ
のように組立てられた半導体装置をプリント回路基板に
実装する場合は、プリント回路基板の予備はんだされた
ランド部に半導体装置の外郭体より突出するリードフレ
ームの外部リード部を載せ、リフロー等により予備はん
だを加熱溶融することではんだ接続し実装を行なってい
た。In the lead frame having a coating structure for coating palladium or a palladium base on the outer surface, a semiconductor chip is mounted on the island portion, and the semiconductor chip and the inner lead portion are wire-bonded with a gold wire and then a resin is formed. It is sealed and incorporated into a semiconductor device. When mounting the thus assembled semiconductor device on a printed circuit board, the external lead portion of the lead frame protruding from the outer shell of the semiconductor device is placed on the pre-soldered land portion of the printed circuit board, and reflowing or the like is performed. Therefore, the pre-solder is heated and melted to be soldered and mounted.
【０００７】[0007]
【発明が解決しようとする課題】上述した従来の配線電
極の被膜構造では、パラジウムあるいはパラジウム基合
金を被膜し、その被膜の厚さを低廉化するために薄く
し、パラジウムあるいはパラジウム基合によるはんだ付
け性あるいはワイヤボンディング性及び樹脂との密着性
を改善を図ったものである。しかしながら、この低廉化
を図るあまりこの被膜を薄くすると、しばしば、この薄
いＰｄあるいはＰｄ合金めっき膜が、めっき時に発生す
る水素ガス圧を阻止することができずピンホールが発生
する。このため、ピンホールより露出した下地が組立時
の熱で酸化しはんだぬれ性及びワイヤボンディング特性
を著しく低下させる。このことは、金線とインナーリー
ドとの接続強度が不足しヒートサイクル等による剥れ起
し信頼性を損なう問題がある。また、はんだ付け実装に
おいてもルーズコンタクトの問題を引起すことになる。
さらに、長期保存したものではパラジウム自身が酸化し
接続自体が困難になるという問題がある。In the above-mentioned conventional coating structure of the wiring electrode, palladium or a palladium-based alloy is coated, and the thickness of the coating is thinned to reduce the cost. The adhesiveness or wire bonding property and the adhesiveness with resin are improved. However, if this coating is made too thin for the purpose of cost reduction, the thin Pd or Pd alloy plating film often cannot prevent the hydrogen gas pressure generated during plating, resulting in pinholes. For this reason, the base exposed from the pinhole is oxidized by heat during assembly, and solder wettability and wire bonding characteristics are significantly deteriorated. This causes a problem that the connection strength between the gold wire and the inner lead is insufficient and peeling occurs due to a heat cycle or the like to deteriorate reliability. Also, it causes a loose contact problem in solder mounting.
Further, if stored for a long period of time, there is a problem that the palladium itself is oxidized and the connection itself becomes difficult.
【０００８】このピンホールの防止対策として、例え
ば、特開昭６１一１４０００６号公報に開示されている
ように、パラジウム被膜に１μｍの比較的に厚い金めっ
きを施し、真空中で４５０℃で３０加熱し合金化してピ
ンホールを埋める方法があるが、この方法では、真空加
熱処理するという余計な工程が増えるばかりか金めっき
のコストが高くなる。さらに、必要以上に下地金属がパ
ラジウムに拡散しはんだ付け性を著しく劣化させる。こ
のような被膜構造は電気接点の適用にはともかく配線電
極には適用出来ない。As a measure for preventing this pinhole, for example, as disclosed in JP-A-61-1140006, a palladium film is plated with a relatively thick gold layer of 1 μm, and it is heated at 450 ° C. in vacuum at 30 ° C. There is a method of heating and alloying to fill the pinholes, but this method not only increases the extra step of vacuum heat treatment but also increases the cost of gold plating. Further, the base metal diffuses into palladium more than necessary, and the solderability is significantly deteriorated. Such a coating structure cannot be applied to a wiring electrode regardless of the application of an electrical contact.
【０００９】従って、本発明の目的は、コストの上昇さ
せることなく酸化を抑え、はんだぬれ性及びワイヤボン
デイング特性を改善し、接続強度の高い配線電極の被膜
構造を提供することである。Therefore, an object of the present invention is to provide a film structure of a wiring electrode which suppresses oxidation without increasing cost, improves solder wettability and wire bonding characteristics, and has high connection strength.
【００１０】[0010]
【課題を解決するための手段】本発明の特徴は、導電板
部材の外表面に被着された銅膜に重ね披着されるニッケ
ル膜と、このニッケル膜を被覆する０．５μｍ以下の厚
さのパラジウム膜と、このパラジウム膜に重ね披着され
る０．００２５μｍ以上の厚さの金膜を有する配線電極
の被膜構造である。The present invention is characterized by a nickel film overlaid on a copper film deposited on the outer surface of a conductive plate member, and a thickness of 0.5 μm or less that coats the nickel film. And a palladium film and a gold film having a thickness of 0.0025 μm or more, which is overlaid on the palladium film.
【００１１】[0011]
【作用】図１はパラジウムめっきの上に種々の厚さの金
めっきを施したときのはんだぬれ性を示すグラフであ
る。本発明は、展延性があって耐蝕性に優れ金線及びは
んだに対して溶着性のある金に着目し、価格を考慮しな
がら金めっき厚を薄くしポーラスなパラジウムめっき面
に施したら、はんだぬれ性及びワイヤボンディング性を
確保出来るかを実証するために、金めっき厚さを種々変
えて実験を行なってみた。1 is a graph showing solder wettability when gold plating having various thicknesses is applied on palladium plating. The present invention focuses on gold that has spreadability, excellent corrosion resistance, and weldability to gold wire and solder, and when applied to a porous palladium-plated surface by reducing the gold plating thickness while considering the price, solder In order to verify whether the wettability and wire bondability can be ensured, experiments were conducted with various gold plating thicknesses.
【００１２】その結果、図１に示すように、はんだぬれ
性を示す指標であるゼロックスタイム（はんだがなじむ
まで要する時間）は、金めっきの厚さが０．００２５μ
ｍ以上になると急激にゼロックスタイムが短くなり、そ
の後厚くしてもあまり短かくならないことが判明した。
このことはピンホールより露出する下地面を含むパラジ
ウムめっき面が薄い金膜で覆われていることが考えられ
る。言い換えれば、薄くとも０．００２５μｍの金めっ
きをパラジウムめっき面に施せば、パラジウムめっき面
は凹凸があっても薄い金膜で一様に覆われ、所望のはん
だ付け性及び耐蝕性が得られることが出来る。As a result, as shown in FIG. 1, the Xerox time (the time required for the solder to fit in), which is an index indicating the wettability of the solder, was 0.0025 μm when the thickness of the gold plating was 0.0025 μm.
It was found that the Xerox time suddenly became shorter when the length was more than m, and the thickness did not become so short even if the thickness was increased thereafter.
This is probably because the palladium-plated surface including the underlying surface exposed from the pinhole is covered with a thin gold film. In other words, if at least 0.0025 μm of gold plating is applied to the palladium-plated surface, the palladium-plated surface is uniformly covered with a thin gold film even if there are irregularities, and desired solderability and corrosion resistance can be obtained. Can be done.
【００１３】[0013]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【００１４】図２は本発明の配線電極の被膜構造の一実
施例を断面で示すリードフレームの部分図である。この
配線電極の被膜構造は、図２に示すように、リードフレ
ームの基体である導電性のある板部材５に、ニッケルと
披着性の良い銅めっきを施しＣｕめっき層４を厚さ０．
１μｍに形成する。そして、このＣｕめっき層４の上を
ニッケルめっきを施しＮｉめっき層３を厚さ１乃至２μ
ｍ、例えば、１．５μｍに形成する。さらに、このＮｉ
めっき層３の上に酸化防止用にパラジウムめっきを施
し、厚さ０．３μｍの薄いＰｄめっき層２を形成する。
そして最後にＰｄめっき層２の上から金フラッシュめっ
きを施し、ピンホール６のあるＰｄめっき層２を覆う
０．００３μｍの薄いＡｕめっき層１を形成する。FIG. 2 is a partial view of a lead frame showing a cross section of one embodiment of the coating structure of the wiring electrode of the present invention. As shown in FIG. 2, the film structure of this wiring electrode is such that a conductive plate member 5 which is a base of a lead frame is plated with nickel and copper, which has a good adhesive property, to form a Cu plating layer 4 having a thickness of 0.
It is formed to 1 μm. Then, nickel plating is applied on the Cu plating layer 4 to form the Ni plating layer 3 having a thickness of 1 to 2 μm.
m, for example, 1.5 μm. Furthermore, this Ni
Palladium plating is applied on the plating layer 3 to prevent oxidation to form a thin Pd plating layer 2 having a thickness of 0.3 μm.
Finally, gold flash plating is applied on the Pd plated layer 2 to form a 0.003 μm thin Au plated layer 1 covering the Pd plated layer 2 having the pinholes 6.
【００１５】ここで、Ｃｕめっき層４は、ニッケルとの
密着性を得るために施すもので、もし銅めっきを省略す
ると、リードフレームの基体とニッケルめっき層が剥離
することになる。また、このＮｉめっき層３は、その下
の銅めっき層４の拡散を防止する役目と、その上のＰｄ
めっき層２を薄く形成させるために施すものである。Here, the Cu plating layer 4 is provided in order to obtain adhesion to nickel, and if copper plating is omitted, the lead frame substrate and the nickel plating layer are separated. Further, the Ni plating layer 3 has a role of preventing diffusion of the copper plating layer 4 therebelow, and a Pd layer formed thereon.
It is applied to form the plating layer 2 thin.
【００１６】一方、Ｐｄめっき層２は、Ｎｉめっき層３
の酸化防止のために施すことが目的であるが、パラジウ
ム自体の価格が高価なため薄くすることが要求される。
そこで、コストの上昇を抑え得る厚さと発生するピンホ
ール確率を考慮すると、実用上の厚さの上限は０．５μ
ｍである。しかし、０．５μｍの厚さでもピンホールは
無くならない。そこでＰｄが析出する際に発生するピン
ホール６が発生した状態で、このＰｄめっき層２とピン
ホール６より露出するＮｉめっき層を含めた面に覆うよ
うに０．００３μｍ程度の薄いＡｕめっき層１を形成し
た。このことにより最表面に露出するＮｉめっき層３と
無くし、Ｎｉめっき層３とＰｄめっき層の酸化防止を行
なった。On the other hand, the Pd plating layer 2 is the Ni plating layer 3
The purpose of this is to prevent the oxidation of palladium, but since the price of palladium itself is expensive, it is required to be thin.
Therefore, considering the thickness that can suppress the increase in cost and the probability of pinholes that occur, the practical upper limit of the thickness is 0.5 μm.
m. However, even if the thickness is 0.5 μm, the pinhole cannot be eliminated. Therefore, in the state where the pinhole 6 generated when Pd is deposited is formed, a thin Au plating layer of about 0.003 μm is formed so as to cover the surface including the Pd plating layer 2 and the Ni plating layer exposed from the pinhole 6. 1 was formed. As a result, the Ni plating layer 3 exposed on the outermost surface was eliminated, and the Ni plating layer 3 and the Pd plating layer were prevented from being oxidized.
【００１７】ちなみに、この被膜構造をもつリードフレ
ームを使用した半導体装置と、ＰｄもしくはＰｄ合金の
めっきによる被膜構造をもつ従来のリードフレームとを
使用した半導体装置とを試作し、両者のはんだぬれ性及
びワイヤボンディング性の比較試験を行なってみた。By the way, a semiconductor device using a lead frame having this coating structure and a semiconductor device using a conventional lead frame having a coating structure formed by plating Pd or a Pd alloy were prototyped, and the solder wettability of both was produced. And a comparative test of wire bondability was performed.
【００１８】その結果、表１に示すように、はんだ付け
性を裏付けるはんだぬれ性は、従来と比較して大幅に改
善されている。通常、ゼロクスタイムが０．１〜０．５
秒程度であれば、はんだ接続性が良いと判定され、はん
だ接続実装が効率良く実施出来る見通しを得た。As a result, as shown in Table 1, the solder wettability that supports the solderability is significantly improved as compared with the conventional one. Xerox time is usually 0.1 to 0.5
If it is about a second, it is judged that the solder connection property is good, and it is expected that the solder connection mounting can be efficiently performed.
【００１９】 [0019]
【００２０】また、ワイヤボンディング特性において
は、２５μｍ直径の金線をワイヤボンダでインナーリー
ド部に溶接して接続し、接続後に引張試験を行なったと
ころ、表２に示すように、従来と比較して不着発生率が
皆無となり、その接続強度も１０パーセント以上向上し
た。Regarding the wire bonding characteristics, a gold wire having a diameter of 25 μm was welded and connected to the inner lead portion with a wire bonder, and a tensile test was conducted after the connection. The non-sticking occurrence rate was zero and the connection strength was improved by 10% or more.
【００２１】 [0021]
【００２２】なお、本発明の実施例では配線電極をリー
ドフレームで説明したが、リードフレームに限定するも
でなく半導体装置の外郭体から露出するバンプ電極の下
地電極にも適用出来る。この場合は、めっき法による披
膜形成だけでなくスパッタリング法あるいは蒸着法等を
適用することである。。In the embodiment of the present invention, the wiring electrode is described as the lead frame, but the present invention is not limited to the lead frame and can be applied to the base electrode of the bump electrode exposed from the outer casing of the semiconductor device. In this case, not only the coating film formation by the plating method but also the sputtering method or the vapor deposition method is applied. .
【００２３】[0023]
【発明の効果】以上説明したように本発明は、配線電極
の基体である板部材の銅めっき層にコストを考慮して薄
いパラジウムめっき層をニッケルめっき層を介して形成
し、このパラジウムめっき層及び発生するピンホールか
ら露呈するニッケル下地面を含めた面を被せる耐蝕性及
びはんだ付け性の優れた金めっき層を極めて薄く形成す
ることによって、酸化し易い膜を外気に露呈させること
が無くなりはんだぬれ性及び金線との接続性を改善しよ
り高い接続強度が得られるという効果がある。また、パ
ラジウム膜もコストの上昇を招かない程度に薄くし、こ
のパラジウム膜を覆う金膜も極力薄くしトータルコスト
の上昇を抑えることが出来た。As described above, according to the present invention, a thin palladium plating layer is formed on the copper plating layer of the plate member which is the base of the wiring electrode via the nickel plating layer in consideration of the cost. And, by forming a very thin gold plating layer with excellent corrosion resistance and solderability that covers the surface including the nickel underlayer exposed from the generated pinholes, it is possible to prevent exposing a film that is easily oxidized to the outside air. There is an effect that the wettability and the connectivity with the gold wire are improved and higher connection strength can be obtained. Also, the palladium film was made thin to the extent that the cost did not increase, and the gold film covering this palladium film was made as thin as possible to suppress the increase in total cost.
【図１】パラジウムめっきの上に種々の厚さの金めっき
を施したときのはんだぬれ性を示すグラフである。FIG. 1 is a graph showing solder wettability when gold plating having various thicknesses is applied on palladium plating.
【図２】本発明の配線電極の被膜構造の一実施例を断面
で示すリードフレームの部分図である。FIG. 2 is a partial view of a lead frame showing an embodiment of a coating structure of a wiring electrode of the present invention in cross section.
【図３】配線電極の被膜構造の従来技術の例のそれぞれ
を断面で示すリードフレームの部分図である。FIG. 3 is a partial view of a lead frame showing, in cross section, each of the examples of the related art of the film structure of the wiring electrode.
１ Ａｕめっき層 ２ Ｐｄめっき層 ３ Ｎｉめっき層 ４ Ｃｕめっき層 ５ 板部材 ６ ピンホール 1 Au plated layer 2 Pd plated layer 3 Ni plated layer 4 Cu plated layer 5 Plate member 6 Pinhole
Claims (1)
重ね被着されるニッケル膜と、このニッケル膜を被覆す
る０．５μｍ以下の厚さのパラジウム膜と、このパラジ
ウム膜に重ね披着される０．００２５μｍ以上の厚さの
金膜を有することを特徴とする配線電極の被膜構造1. A nickel film overlaid on a copper film deposited on the outer surface of a conductive plate member, a palladium film having a thickness of 0.5 μm or less and covering the nickel film, and the palladium film. A film structure of a wiring electrode having a gold film with a thickness of 0.0025 μm or more that is overlaid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4618893A JPH06260577A (en) | 1993-03-08 | 1993-03-08 | Coating structure of wiring electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4618893A JPH06260577A (en) | 1993-03-08 | 1993-03-08 | Coating structure of wiring electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06260577A true JPH06260577A (en) | 1994-09-16 |
Family
ID=12740079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4618893A Pending JPH06260577A (en) | 1993-03-08 | 1993-03-08 | Coating structure of wiring electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06260577A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100450091B1 (en) * | 1999-10-01 | 2004-09-30 | 삼성테크윈 주식회사 | Multiplated lead frame for semiconductor device |
| JP2007063042A (en) * | 2005-08-30 | 2007-03-15 | Hitachi Metals Ltd | Ceramic substrate and electronic component using it |
| JP2014099637A (en) * | 2009-03-12 | 2014-05-29 | Lg Innotek Co Ltd | Lead frame and method for manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04115558A (en) * | 1990-09-05 | 1992-04-16 | Shinko Electric Ind Co Ltd | Lead frame for semiconductor device |
-
1993
- 1993-03-08 JP JP4618893A patent/JPH06260577A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04115558A (en) * | 1990-09-05 | 1992-04-16 | Shinko Electric Ind Co Ltd | Lead frame for semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100450091B1 (en) * | 1999-10-01 | 2004-09-30 | 삼성테크윈 주식회사 | Multiplated lead frame for semiconductor device |
| JP2007063042A (en) * | 2005-08-30 | 2007-03-15 | Hitachi Metals Ltd | Ceramic substrate and electronic component using it |
| JP2014099637A (en) * | 2009-03-12 | 2014-05-29 | Lg Innotek Co Ltd | Lead frame and method for manufacturing the same |
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| A02 | Decision of refusal |
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