JPH06244309A - Structure of multi-chip package - Google Patents

Structure of multi-chip package

Info

Publication number
JPH06244309A
JPH06244309A JP2557093A JP2557093A JPH06244309A JP H06244309 A JPH06244309 A JP H06244309A JP 2557093 A JP2557093 A JP 2557093A JP 2557093 A JP2557093 A JP 2557093A JP H06244309 A JPH06244309 A JP H06244309A
Authority
JP
Japan
Prior art keywords
substrate
sealant
chip package
chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2557093A
Other languages
Japanese (ja)
Inventor
Tadashi Komiyama
忠 込山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2557093A priority Critical patent/JPH06244309A/en
Publication of JPH06244309A publication Critical patent/JPH06244309A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a multi-chip package in which unfilled portions or voids do not easily occur, by an arrangement of the semiconductor chip or electronic component in the package. CONSTITUTION:On a substrate 1 on which a wiring pattern 2 was preformed, a semiconductor 3 or a sealed semiconductor device 8 and a plurality of other electronic components 4 are arranged, an electrical contact with the wiring pattern 2 on the substrate 1 is made, and after an electrode 7 on the substrate 1 is electrically contacted with leads 11 by means of wires 5 of gold wires or the like, the structure is seald by resin and cut off from a lead frame 10, and the leads 11 is formed, forming the structure. In particular, a structure of the multi-chip package in which the arrangement is made so that the angle formed by the longitudinal direction of at least the one having the maximum volume among the electronic components such as the semiconductor chip for the substrate with a radial line along the injection direction of the sealing agent falls within the range of + or -45 degrees.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、マルチチップパッケー
ジの構造に関するもので、特にパッケージ内部に搭載す
る半導体チップ等の電子部品の配列方向に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a multi-chip package, and more particularly to an arrangement direction of electronic parts such as semiconductor chips mounted inside the package.

【０００２】[0002]

【従来の技術】従来、この種のマルチチップパッケージ
は、図５に従来のマルチチップパッケージの一実施例を
示す透視図を示すが、本実施例によると、予め配線パタ
ーン２の形成された基板１上に半導体チップ３、または
封止された半導体装置８、またはその他電子部品４を配
列し、金線等のワイヤ５または銀ペースト６等の導電性
接続手段で半導体チップ３、または封止された半導体装
置８、その他の電子部品４と基板１上の配線パターン２
との電気的コンタクトをとり、さらに基板１の電極７を
リード１１と金線等のワイヤ５によって電気的コンタク
トをとった後、樹脂等の封止剤９で封止し、リードフレ
ーム枠１０から切断分離し、リード１１を整形すること
によって形成するマルチチップパッケージにおいて、半
導体チップ３、または封止された半導体装置８、電子部
品４の配列方向は、図６に従来のマルチチップパッケー
ジの一実施例における基板の平面図を示すが、図６によ
れば、半導体チップ３、または封止された半導体装置
８、または電子部品４は、それらの各辺が長方形に加工
された基板１の外周の辺１８に直角または平行に配置さ
れており、封止剤の注入口１２から放射状に広がる封止
剤の注入方向１２については、特に考慮はされていなか
った。2. Description of the Related Art Conventionally, a multi-chip package of this type is shown in FIG. 5 which is a perspective view showing one embodiment of a conventional multi-chip package. According to this embodiment, a substrate on which a wiring pattern 2 is formed in advance is shown. The semiconductor chip 3 or the encapsulated semiconductor device 8 or other electronic component 4 is arranged on the semiconductor chip 1, and the semiconductor chip 3 or the encapsulated semiconductor device 8 is sealed by a conductive connecting means such as a wire 5 such as a gold wire or a silver paste 6. Semiconductor device 8, other electronic components 4 and wiring pattern 2 on substrate 1.
After making electrical contact with the electrode 7 of the substrate 1 with the lead 11 and the wire 5 such as a gold wire, the electrode 7 is sealed with a sealant 9 such as resin, and the lead frame 10 is removed. In the multi-chip package formed by cutting and separating and shaping the leads 11, the arrangement direction of the semiconductor chip 3, the sealed semiconductor device 8 and the electronic component 4 is shown in FIG. FIG. 6 shows a plan view of the substrate in the example. According to FIG. 6, the semiconductor chip 3, the sealed semiconductor device 8, or the electronic component 4 has a rectangular shape on each side of the outer periphery of the substrate 1. The injection direction 12 of the sealant, which is arranged at right angles or parallel to the side 18 and radially spreads from the injection port 12 of the sealant, was not particularly considered.

【０００３】この時、図７に従来の一実施例に関するパ
ッケージの断面図を示すが、半導体チップ３や封止され
た半導体装置８等がある部分の封止剤流入断面ａ１４
は、それらの周辺部の封止剤流入断面ｂ１５より狭いた
め、封止剤９は、半導体チップ３や封止された半導体装
置８等のある部分の周辺部（即ち、封止剤流入断面ｂ１
８の部分）に優先的に回り込む。また、また図６におけ
るような途中に封止剤流入経路の分岐箇所１６がある
と、この部分から先では封止剤の流入経路が分岐しない
場合に比べ封止剤の流入が遅れる。At this time, FIG. 7 shows a cross-sectional view of a package according to a conventional example. The cross-section a14 of the sealant inflow of a portion having the semiconductor chip 3, the semiconductor device 8 and the like sealed therein.
Is narrower than the sealant inflow cross section b15 in the peripheral portion thereof, the sealant 9 is applied to the peripheral portion of a portion of the semiconductor chip 3 or the sealed semiconductor device 8 (that is, the sealant inflow cross section b1).
Priority 8). Further, if there is a branch point 16 of the sealant inflow route in the middle as shown in FIG. 6, the inflow of the sealant is delayed from this part onward as compared to the case where the inflow route of the sealant is not branched.

【０００４】[0004]

【発明が解決しようとする課題】前述のマルチチップパ
ケージの構造では、封止剤９が充填される際に、封止剤
９は、基板上の半導体チップ３、または封止された半導
体装置８、その他の電子部品４などの周辺部の抵抗が小
さい部分（流入断面積の大きい部分であり、図５でいう
封止剤流入断面ｂ１５の部分）に沿って複雑に流入経路
や流入速度を変化させながら流動する。このため、抵抗
が小さい部分は封止剤９が早く回り込み、一方、抵抗が
大きい部分（流入断面積の小さい部分で、図７でいう封
止剤流入断面ａ１４の部分）は封止剤９の注入が遅れ、
早く回り込んだ封止剤との間の空気が逃げ場を失い、未
充填やボイドとして残り、品質の低下をもたらすという
不具合があった。In the structure of the multi-chip package described above, when the encapsulant 9 is filled, the encapsulant 9 is the semiconductor chip 3 on the substrate or the encapsulated semiconductor device 8. In addition, the inflow path and the inflow velocity are changed intricately along the peripheral portion of the other electronic component 4 or the like having a small resistance (a portion having a large inflow cross-sectional area, that is, a sealant inflow cross-section b15 in FIG. 5). Let it flow. For this reason, the sealant 9 quickly wraps around the portion having a small resistance, while the portion having a large resistance (a portion having a small inflow cross-sectional area, that is, a portion of the sealant inflow cross-section a14 in FIG. 7) is the sealant 9. Delayed injection,
There is a problem that the air between the sealing agent that has swirled around quickly loses an escape area, remains unfilled or remains as a void, and deteriorates the quality.

【０００５】本発明の目的は、以上のようなパッケージ
内部の半導体チップ等の電子部品によって、未充填やボ
イドの発生しないようなマルチチップパッケージを提供
するものである。An object of the present invention is to provide a multi-chip package in which unfilling or voids do not occur due to the electronic components such as semiconductor chips inside the package as described above.

【０００６】[0006]

【課題を解決するための手段】上記目的は、予め配線の
形成された基板上に半導体チップ、または封止された半
導体装置、またはその他の電子部品を複数配列し、金線
等のワイヤまたは銀ペースト等で半導体チップまたは電
子部品と基板上の配線との電気的コンタクトをとり、さ
らに基板の電極をリードと金線等によって電気的コンタ
クトをとった後、樹脂封止し、リードフレーム枠から切
断分離し、リードを成形することによって形成する、マ
ルチチップパッケージにおいて、基板に対する半導体装
置等の電子部品のうち少なくとも最大の体積を有するも
のの長手方向と封止剤の注入方向に沿った放射状の線と
のなす角θが±４５°の範囲内になるように配列する構
造によって達成される。The above object is to arrange a plurality of semiconductor chips, sealed semiconductor devices, or other electronic components on a substrate on which wiring has been formed in advance, and wire such as gold wire or silver. Make electrical contact between the semiconductor chip or electronic component and the wiring on the board with paste, etc., and then make electrical contact with the electrodes of the board with leads and gold wires, etc., then seal with resin and cut from the lead frame frame. In a multi-chip package formed by separating and molding leads, radial lines along the longitudinal direction of the electronic component such as a semiconductor device having the maximum volume with respect to the substrate and the injection direction of the sealant, This is achieved by the structure in which the angle θ formed by is arranged within the range of ± 45 °.

【０００７】[0007]

【作用】マルチチップパッケージの構造に関し、基板に
対する半導体チップの、配列方向を封止剤の注入方向に
沿って放射状にすることによって、封止剤は基板上の半
導体チップ等のの電子部品によって注入経路を複雑に変
えられにくくなり、パッケージ全体に同程度の速度で封
止剤が注入されるため、未充填やボイドが発生しにくく
なる。With respect to the structure of the multi-chip package, by arranging the semiconductor chips with respect to the substrate in the arrangement direction radially along the injection direction of the encapsulant, the encapsulant is injected by the electronic components such as the semiconductor chips on the substrate. It becomes difficult to change the path in a complicated manner, and the sealant is injected into the entire package at the same speed, so that unfilling and voids hardly occur.

【０００８】[0008]

【実施例】本発明の一実施例を以下に説明する。EXAMPLE An example of the present invention will be described below.

【０００９】図１は、本発明のマルチチップパッケージ
の内部構造の透視図である。FIG. 1 is a perspective view of the internal structure of the multi-chip package of the present invention.

【００１０】図１によれば、予め配線パターン２の形成
された基板１上に半導体チップ３、または封止された半
導体装置８、その他の電子部品４を複数配列し、金線等
のワイヤ５または銀ペースト６等で半導体チップ３また
は電子部品４と基板１上の配線パターン２との電気的コ
ンタクトをとり、さらに基板１の電極７をリード１１と
金線等のワイヤ５によって電気的コンタクトをとった
後、封止剤９で封止し、リードフレーム枠１０から切断
分離し、リード１１を成形することによって形成するこ
とになるが、本発明によれば、基板１上の配線パターン
２は、封止剤の注入口１３に対して、基板１上に設置さ
れる半導体チップ３または封止された半導体装置８やそ
の他の電子部品４のうち少なくとも最大の体積を有する
ものの長手方向と封止剤の注入方向に沿った放射状の線
とのなす角θ1１９またはθ1に隣接した、封止剤の注入
方向に沿った放射状の線と半導体装置等の電子部品４の
長手方向とのなす角θ2２０が±４５°の範囲内になる
ように配列する。封止剤は、封止剤の注入口１３から放
射状に注入される。According to FIG. 1, a plurality of semiconductor chips 3 or sealed semiconductor devices 8 and other electronic components 4 are arranged on a substrate 1 on which a wiring pattern 2 is formed in advance, and wires 5 such as gold wires are used. Alternatively, the semiconductor chip 3 or the electronic component 4 and the wiring pattern 2 on the substrate 1 are electrically contacted with a silver paste 6 or the like, and the electrode 7 of the substrate 1 is electrically contacted with the lead 11 and the wire 5 such as a gold wire. After that, the wiring pattern 2 is sealed by the sealing agent 9, cut and separated from the lead frame frame 10, and the leads 11 are molded. According to the present invention, the wiring pattern 2 on the substrate 1 is formed. With respect to the injection port 13 of the sealant, the longitudinal direction and the sealing of the semiconductor chip 3 mounted on the substrate 1, the sealed semiconductor device 8 or other electronic components 4 having at least the maximum volume are sealed. Adjacent to the angle theta 1 19 or theta 1 between radial line along the injection direction of the material, formed between the longitudinal direction of the electronic component 4 such as radial lines and the semiconductor device along the injection direction of the sealant angle theta 2 20 are arranged to be within a range of ± 45 °. The sealant is radially injected from the sealant injection port 13.

【００１１】次に、図２に本発明のマルチチップパッケ
ージを樹脂封止する時の初期における封止剤の充填状態
を示す平面図を示すが、図２によれば、半導体チップ３
等を搭載した基板１は、金型１７に載せられ、封止剤の
注入口１３より、封止剤９を注入されて封止されるので
あるが、この封止時においては、封止剤９は封止剤の注
入口１３から注入された後、金型内を放射状に広がって
行き、やがて半導体チップ３等に達する。次に図３に本
発明のマルチチップパッケージを樹脂封止する時の途中
における封止剤の充填状況を示す平面図を示すが、封止
剤は、半導体チップ３、または封止された半導体装置
８、その他の電子部品４の周辺部を周りながら放射状に
広がっていき、封止剤充填の最後に、図４に本発明のマ
ルチチップパッケージを封止する時の最終段階直前にお
ける封止剤の充填状況を示す平面図を示すが、封止剤９
は、半導体チップ３、または封止された半導体装置８、
その他の電子部品４によって注入経路を複雑に変えられ
ることなく本来の注入方向である封止剤の注入口１３よ
り放射状に広がるという経路を確保し、経路を複雑に変
えられることや流入経路の分岐に起因する注入タイミン
グのずれによる未充填やボイドの発生はなく、封止が完
了する。Next, FIG. 2 is a plan view showing the filling state of the encapsulant at the initial stage of resin-sealing the multi-chip package of the present invention. According to FIG.
The substrate 1 on which the above components are mounted is placed on the mold 17, and the sealant 9 is injected from the sealant injection port 13 to seal the sealant. After 9 is injected from the injection port 13 of the sealant, it spreads radially inside the mold, and eventually reaches the semiconductor chip 3 and the like. Next, FIG. 3 is a plan view showing a filling state of a sealant during resin sealing of the multi-chip package of the present invention. The sealant is the semiconductor chip 3 or the sealed semiconductor device. 8. The sealant spreads radially around the periphery of the other electronic components 4, and at the end of the sealant filling, the sealant just before the final stage of sealing the multi-chip package of the present invention is shown in FIG. Although the plan view showing the filling state is shown, the sealing agent 9
Is the semiconductor chip 3 or the sealed semiconductor device 8,
It is possible to secure a route that spreads radially from the injection port 13 of the sealant, which is the original injection direction, without being able to change the injection route in a complicated manner by the other electronic components 4, and to be able to change the route in a complicated manner or branch the inflow route. There is no filling or void due to the deviation of the injection timing due to the above, and the sealing is completed.

【００１２】尚、本発明では、リード１１と基板１上の
電極７との接続は、金線等のワイヤ５によって接続する
ことで説明したが、この接続手段は、リード１１と基板
１上の電極７を熱圧着、半田付けなどで直接接続しても
よい。In the present invention, the connection between the lead 11 and the electrode 7 on the substrate 1 has been described by connecting with the wire 5 such as a gold wire. The electrodes 7 may be directly connected by thermocompression bonding or soldering.

【００１３】[0013]

【発明の効果】以上述べたように、本発明によれば、マ
ルチチップパッケージの封止時に、封止剤は注入経路上
に存在する半導体チップ等の電子部品の抵抗によって、
注入経路を複雑に変えられることなく本来の注入方向で
ある封止剤の注入口より放射状に広がるという経路を確
保でき、経路を妨げられることに起因する注入タイミン
グのずれによる未充填やボイドの発生を防ぐことがで
き、歩留りを向上させ、かつ品質を向上させることがで
きるという効果を有する。As described above, according to the present invention, at the time of encapsulating a multi-chip package, the encapsulant is formed by the resistance of electronic parts such as semiconductor chips existing on the injection path.
It is possible to secure a path that spreads radially from the sealant injection port, which is the original injection direction, without being able to change the injection path in a complicated manner, and the occurrence of unfilling or voids due to the injection timing shift due to the path being blocked. Can be prevented, yield can be improved, and quality can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明のマルチチップパッケージの内部構造の
透視図。FIG. 1 is a perspective view of an internal structure of a multi-chip package of the present invention.

【図２】 本発明のマルチチップパッケージを樹脂封止
する時の初期における封止剤の充填状態を示す平面図。FIG. 2 is a plan view showing a filling state of an encapsulant at the initial stage of resin-sealing the multi-chip package of the present invention.

【図３】本発明のマルチチップパッケージを樹脂封止す
る時の途中における封止剤の充填状況を示す平面図。FIG. 3 is a plan view showing a filling state of a sealant in the middle of resin-sealing the multi-chip package of the present invention.

【図４】本発明のマルチチップパッケージを樹脂封止す
る時の最終段階における封止剤の充填状況を示す平面
図。FIG. 4 is a plan view showing a filling state of a sealing agent at the final stage when resin-sealing the multi-chip package of the present invention.

【図５】従来のマルチチップパッケージの一実施例を示
す透視図。FIG. 5 is a perspective view showing an example of a conventional multi-chip package.

【図６】従来のマルチチップパッケージの一実施例にお
ける基板の平面図。FIG. 6 is a plan view of a substrate in an example of a conventional multi-chip package.

【図７】従来の一実施例に関するパッケージの断面図。FIG. 7 is a cross-sectional view of a package according to a conventional example.

【符号の説明】[Explanation of symbols]

１．基 板 ２．配線パターン ３．半導体チップ ４．電子部品 ５．ワイヤ ６．銀ペースト ７．電 極 ８．封止された半導体装置 ９．封止剤 １０．リードフレーム枠 １１．リード １２．封止剤の注入方向 １３．封止剤の注入口 １４．封止剤流入断面ａ １５．封止剤流入断面ｂ １６．封止剤流入経路の分岐箇所 １７．金 型 １８．基板の外周の辺 １９．封止剤の注入方向に沿った放射状の線と半導体装
置等の電子部品４の長手方向とのなす角θ１ ２０．θ１に隣接した、封止剤の注入方向に沿った放射
状の線と半導体装置等の電子部品４の長手方向とのなす
角θ２1. Base plate 2. Wiring pattern 3. Semiconductor chip 4. Electronic components 5. Wire 6. Silver paste 7. Electrode 8. 8. Sealed semiconductor device Sealing agent 10. Lead frame frame 11. Lead 12. Injection direction of sealant 13. Sealant injection port 14. Sealant inflow cross section a 15. Sealant inflow cross section b 16. Branch point of sealant inflow route 17. Mold 18. Edge of outer periphery of substrate 19. An angle θ1 formed by a radial line along the injection direction of the sealant and the longitudinal direction of the electronic component 4 such as a semiconductor device 20. An angle θ2 formed by a radial line adjacent to θ1 along the injection direction of the sealant and the longitudinal direction of the electronic component 4 such as a semiconductor device.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 // Ｈ０１Ｌ 23/50 Ｇ 9272−4Ｍ ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location // H01L 23/50 G 9272-4M

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】予め配線パターンの形成された基板上に、
半導体チップ等の電子部品を配列し、金属ワイヤ等の導
電性接続手段で半導体チップ等の電子部品と基板上の配
線パターンとの電気的コンタクトをとり、さらに基板の
周辺に配置されたリードと基板の電極を金属ワイヤ等の
導電性接続手段によって電気的コンタクトをとった後、
封止剤で封止し、リードフレーム枠から切断分離し、リ
ードを整形することによって形成するマルチチップパッ
ケージの構造に関するもので、特に基板に対する半導体
チップ等の電子部品のうち少なくとも最大の体積を有す
るものの長手方向と、封止剤の注入方向に沿った放射状
の線とのなす角が±４５°の範囲内になるように配列す
る構造を有することを特徴とするマルチチップパッケー
ジの構造。1. A substrate on which a wiring pattern is formed in advance,
An electronic component such as a semiconductor chip is arranged, and an electrical contact is made between the electronic component such as the semiconductor chip and the wiring pattern on the substrate by a conductive connecting means such as a metal wire, and the lead and the substrate arranged around the substrate. After making electrical contact to the electrodes of the above by a conductive connecting means such as a metal wire,
The present invention relates to a structure of a multi-chip package that is formed by sealing with a sealing agent, cutting and separating from a lead frame frame, and shaping leads, and particularly has at least the largest volume of electronic components such as semiconductor chips with respect to a substrate. A structure of a multi-chip package having a structure in which an angle between a longitudinal direction of the object and a radial line along the injection direction of the sealant is within a range of ± 45 °.
JP2557093A 1993-02-15 1993-02-15 Structure of multi-chip package Pending JPH06244309A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2557093A JPH06244309A (en) 1993-02-15 1993-02-15 Structure of multi-chip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2557093A JPH06244309A (en) 1993-02-15 1993-02-15 Structure of multi-chip package

Publications (1)

Publication Number Publication Date
JPH06244309A true JPH06244309A (en) 1994-09-02

Family

ID=12169594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2557093A Pending JPH06244309A (en) 1993-02-15 1993-02-15 Structure of multi-chip package

Country Status (1)

Country Link
JP (1) JPH06244309A (en)

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