JPH06204077A - Ceramic chip capacitor and its manufacture - Google Patents
Ceramic chip capacitor and its manufactureInfo
- Publication number
- JPH06204077A JPH06204077A JP35977692A JP35977692A JPH06204077A JP H06204077 A JPH06204077 A JP H06204077A JP 35977692 A JP35977692 A JP 35977692A JP 35977692 A JP35977692 A JP 35977692A JP H06204077 A JPH06204077 A JP H06204077A
- Authority
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- Prior art keywords
- layer
- palladium
- chip capacitor
- ceramic chip
- silver
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は外部電極技術を改良した
セラミックチップコンデンサ及びその製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic chip capacitor with improved external electrode technology and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、セラミックチップコンデンサは、
図２に示すようにセラミック誘電体１０と内部電極１１
が交互に積層されコンデンサ素子１２の両端部に、両端
部から交互に露出された内部電極１１と接続して設ける
外部電極１３として、銀パラジウム又は銀の金属粉末に
ガラスフリット粉末を添加し、さらにバインダとしてポ
リマーと溶剤を加えた導電性ペーストを塗布し、６００
〜９００℃の高温度で焼成することで形成していた。2. Description of the Related Art Conventionally, ceramic chip capacitors are
As shown in FIG. 2, the ceramic dielectric 10 and the internal electrode 11
Glass frit powder is added to silver-palladium or silver metal powder as external electrodes 13 provided at both ends of the capacitor element 12 that are alternately laminated and connected to the internal electrodes 11 that are alternately exposed from both ends. Apply a conductive paste containing a polymer and a solvent as a binder to 600
It was formed by firing at a high temperature of up to 900 ° C.
【０００３】この外部電極１３の機能は、複数の内部電
極１１を電気的に並列に接続するとともにチップコンデ
ンサをプリント配線基板のランドにはんだ付けするため
の端子であり、外部電極１３はコンデンサ素子１２と十
分な機械的接合強度と良好なはんだ濡れ性を持つことが
要求される。The function of the external electrode 13 is a terminal for electrically connecting the plurality of internal electrodes 11 in parallel and soldering the chip capacitor to the land of the printed wiring board. The external electrode 13 is a capacitor element 12. It is required to have sufficient mechanical bond strength and good solder wettability.
【０００４】しかしながら、上記の構成になる外部電極
１３は、コンデンサ素子１２との機械的接合強度を保持
するために加えられたガラスフリットが外部電極１３の
はんだ濡れ性を阻害する作用がある。このためこれらセ
ラミックチップコンデンサは外部電極１３のはんだ濡れ
性が不十分で、プリント配線基板にはんだ付けする際の
歩留りが低く手直し作業が必要であった。However, in the external electrode 13 having the above-mentioned structure, the glass frit added to maintain the mechanical bonding strength with the capacitor element 12 has an effect of hindering the solder wettability of the external electrode 13. Therefore, in these ceramic chip capacitors, the solder wettability of the external electrodes 13 is insufficient, so that the yield when soldering to the printed wiring board is low and reworking is required.
【０００５】また、はんだ付けの温度が高かったり時間
が長過ぎたりすると外部電極１３の銀が溶融はんだ中に
拡散し電極機能が消失する、いわゆるはんだ食われが生
じる場合があり信頼性に欠ける面があった。Further, if the soldering temperature is high or the time is too long, silver of the external electrode 13 may diffuse into the molten solder and the electrode function may be lost, so-called solder erosion may occur, which is unreliable. was there.
【０００６】そのため、これを回避する技術として、図
３に示すようにセラミック誘電体１０と内部電極１１が
交互に積層されコンデンサ素子１２の両端部に形成した
外部電極１３の上にはんだ食われを防止するニッケル層
１４とはんだ濡れ性の良いはんだ又はすず層１５を順次
電気めっき法で形成する方法が実用化されているが、こ
の技術にも次のような問題点がある。Therefore, as a technique for avoiding this, as shown in FIG. 3, the ceramic dielectrics 10 and the internal electrodes 11 are alternately laminated, and solder erosion is caused on the external electrodes 13 formed at both ends of the capacitor element 12. A method of sequentially forming a nickel layer 14 for prevention and a solder or tin layer 15 having good solder wettability by electroplating has been put into practical use, but this technique also has the following problems.
【０００７】すなわち、第一に、電気めっき浴が酸性で
あるため、めっき中にめっき液が下地電極のガラスフリ
ットを溶解しながら外部電極１３と内部電極１１の接合
箇所まで浸透しこの部分に残存し、これがコンデンサを
長期に使用する間に次第に内部電極１１間のセラミック
誘電体１０層の隙間に浸透して絶縁抵抗が低下する故障
となる場合があり、信頼性上問題である。That is, firstly, since the electroplating bath is acidic, the plating solution permeates the glass frit of the base electrode during plating and penetrates to the joint between the external electrode 13 and the internal electrode 11 and remains in this portion. However, this may cause a failure that the insulating resistance is lowered by gradually penetrating into the gap between the ceramic dielectric 10 layers between the internal electrodes 11 during long-term use of the capacitor, which is a reliability problem.
【０００８】第二に、ニッケル層１４とはんだ又はすず
層１５の二種類の電気めっきが必要であり大規模な設備
と長時間を要するため工業的に不利である。Secondly, two kinds of electroplating of the nickel layer 14 and the solder or tin layer 15 are required, which requires large-scale equipment and a long time, which is industrially disadvantageous.
【０００９】第三に、電気めっきの際、チップに通電す
るためにダミーと称する金属の小球又は線片を大量に使
用するが、めっき膜はこのダミーにも付着し、この分め
っき液が無駄に消費され製造コスト的に不利である。Thirdly, in electroplating, a large amount of metal balls or wire pieces called a dummy are used to energize the chip, but the plating film adheres to this dummy as well, and the plating solution It is wasted and is disadvantageous in manufacturing cost.
【００１０】第四に、電気めっきは一定のめっき膜厚及
び膜性状を得るために、液組成、液温度、濃度、時間、
ｐＨ、電流密度及びチップとダミーの比などを厳密に管
理する必要がある。管理が不十分の場合は不良発生や市
場故障につながる場合があり製造困難である。Fourthly, in electroplating, in order to obtain a certain plating film thickness and film property, liquid composition, liquid temperature, concentration, time,
It is necessary to strictly control pH, current density, chip-dummy ratio and the like. Insufficient management can lead to defects and market failures, making manufacturing difficult.
【００１１】[0011]
【発明が解決しようとする課題】以上のように、従来の
外部電極形成技術は、はんだ食われ現象があり、これを
防止するために、外部電極の上にニッケル層とはんだ又
はすず層を順次電気めっき法で形成する手段もあるが、
電気めっき手段をこの種セラミックチップコンデンサに
適用した場合、絶縁抵抗低下要因を抱えると同時に、コ
スト高、製造の困難性を伴い、必ずしも有効な手段とは
言えなかった。As described above, the conventional external electrode forming technique has a phenomenon of solder erosion. To prevent this, a nickel layer and a solder or tin layer are sequentially formed on the external electrode. There is also a means to form by electroplating,
When the electroplating means is applied to this type of ceramic chip capacitor, it is not always an effective means because it has a factor of lowering the insulation resistance, and at the same time, it is costly and difficult to manufacture.
【００１２】本発明は、上記の課題を解決するために成
されたもので、簡易な手段で、且つはんだ濡れ性の改善
とはんだ食われ現象の解消を可能としたセラミックチッ
プコンデンサ及びその製造方法を提供することを目的と
するものである。The present invention has been made in order to solve the above problems, and is a ceramic chip capacitor and a method of manufacturing the same which are capable of improving solder wettability and eliminating a solder erosion phenomenon by a simple means. It is intended to provide.
【００１３】[0013]
【課題を解決するための手段】本発明のセラミックチッ
プコンデンサは、セラミック誘電体と内部電極が交互に
積層され、この内部電極が交互に露出された両端部に外
部電極を設けたセラミックチップコンデンサにおいて、
前記外部電極が銀パラジウム合金及びガラスフリットか
らなる第一層とリンを１〜１０ｗｔ％含む厚さ０．１ミ
クロン以上のパラジウムからなる第二層とからなること
を特徴とするものである。The ceramic chip capacitor of the present invention is a ceramic chip capacitor in which ceramic dielectrics and internal electrodes are alternately laminated, and external electrodes are provided at both ends where the internal electrodes are alternately exposed. ,
The external electrode comprises a first layer made of a silver-palladium alloy and a glass frit, and a second layer made of palladium having a thickness of 0.1 micron or more containing 1 to 10 wt% of phosphorus.
【００１４】また、本発明のセラミックチップコンデン
サの製造方法は、セラミック誘電体と内部電極が交互に
積層され、この内部電極が交互に露出された両端部に外
部電極を形成してなるセラミックチップコンデンサの製
造方法において、前記外部電極形成手段として粉末状の
銀とパラジウム又は銀パラジウム合金粉末にガラスフリ
ットを添加した導電性ペーストを塗布−焼成して第一層
を形成し、次にこの第一層上に無電解めっき法によりリ
ンを１〜１０ｗｔ％含み、厚さ０．１ミクロン以上のパ
ラジウム膜からなる第二層を形成することを特徴とする
ものである。The method for manufacturing a ceramic chip capacitor according to the present invention is also a ceramic chip capacitor in which ceramic dielectrics and internal electrodes are alternately laminated, and external electrodes are formed at both ends where the internal electrodes are alternately exposed. In the manufacturing method of the above, as the external electrode forming means, a conductive paste obtained by adding glass frit to powdered silver and palladium or a silver-palladium alloy powder is applied and baked to form a first layer, and then the first layer is formed. It is characterized in that a second layer containing a palladium film having a thickness of 0.1 micron or more and containing 1 to 10 wt% of phosphorus is formed thereon by an electroless plating method.
【００１５】[0015]
【作用】以上の構成によれば、外部電極を構成する第一
層の銀パラジウムは、金属粉末を高温度で焼成すること
により内部電極であるパラジウム又は銀パラジウムと粉
末冶金的に接合し内部電極を電気的に接続する作用を有
すると共に第二層となるパラジウム−リンの無電解めっ
きの活性点となり、無電解めっき膜は銀パラジウムの面
にのみ選択的に付着しセラミック素体にはめっきされな
い。また、第一層に含まれるガラスフリットは外部電極
とセラミック素体との機械的強度を与える無機バインダ
としての作用を有する。According to the above construction, the silver-palladium of the first layer constituting the external electrode is powder metallurgically bonded to the internal electrode of palladium or silver-palladium by firing the metal powder at a high temperature to form the internal electrode. The second layer is the active point of the electroless plating of palladium-phosphorus that has the function of electrically connecting the electroless plating film, and the electroless plating film selectively adheres only to the surface of silver-palladium and is not plated on the ceramic body. . Further, the glass frit contained in the first layer acts as an inorganic binder that gives mechanical strength to the external electrode and the ceramic body.
【００１６】そして、第二層のパラジウム−リンは、は
んだ濡れ性が良好であるためプリント配線基板にはんだ
付けするときの歩留りが極めて高く、また、高温度の溶
融はんだ中でもはんだ食われが全くないため基板実装後
の信頼性向上に貢献する。Since the second layer of palladium-phosphorus has good solder wettability, it has an extremely high yield when soldered to a printed wiring board, and there is no solder erosion even in high temperature molten solder. Therefore, it contributes to the improvement of reliability after mounting on the board.
【００１７】さらに、第二層を構成するリンの含有量及
び厚さを上記の範囲にするのは、リンの含有量が１ｗｔ
％未満ではめっきの付着が不十分で、１０ｗｔ％を越え
るとはんだ濡れ性が悪くなり、また、第二層のめっき厚
さ０．１ミクロン未満では、はんだ耐熱性及びはんだ濡
れ性の経時変化に問題があるなどの理由に基づくもので
ある。Further, the content and thickness of phosphorus constituting the second layer is set within the above range so that the content of phosphorus is 1 wt.
If it is less than 10% by weight, the adhesion of the plating is insufficient, and if it exceeds 10% by weight, the solder wettability deteriorates. It is based on reasons such as problems.
【００１８】[0018]
【実施例】以下、本発明の一実施例について説明する。
すなわち、公知の手段で製造された、例えば図１に示す
ようにセラミック誘電体１と内部電極２が交互に積層さ
れ長さ３．２ｍｍ、幅１．６ｍｍのセラミックコンデン
サ素子３の内部電極２が露出する両端面に、Ａｇ粉末８
０重量％とＰｄ２０重量％を混合した金属粉末とガラス
フリットと有機バインダと有機溶剤を成分とする導電性
ペーストを浸漬法により塗布し、乾燥後８００℃で焼成
することによって外部電極４として銀パラジウム合金及
びガラスフリットからなる第一層５を形成する。EXAMPLES An example of the present invention will be described below.
That is, as shown in FIG. 1, for example, the internal electrodes 2 of the ceramic capacitor element 3 having a length of 3.2 mm and a width of 1.6 mm, which are manufactured by known means, are alternately laminated with the ceramic dielectrics 1 and the internal electrodes 2. Ag powder 8 on both exposed end faces
Silver powder is used as the external electrode 4 by applying a conductive paste containing a metal powder, a glass frit, an organic binder, and an organic solvent as components as a mixture of 0% by weight and 20% by weight of Pd by a dipping method, and drying and baking at 800 ° C. A first layer 5 of alloy and glass frit is formed.
【００１９】次に、ＰｄイオンとＰイオン、錯化剤及び
還元剤を含み、例えば、Ｐｄ濃度１．１％、ｐＨ８．
０、温度５０℃に調整しためっき浴に、前記外部電極４
として形成した第一層５を形成した試料を２０分間浸漬
し、次に脱イオン水で超音波洗浄を水洗槽をかえて２回
行い１５０℃で２時間の乾燥を行い、前記第一層５上に
リンを含むパラジウム膜からなる第二層６を形成する。Next, it contains Pd ions and P ions, a complexing agent and a reducing agent. For example, Pd concentration is 1.1%, pH is 8.
The external electrode 4 is placed in a plating bath adjusted to 0 and a temperature of 50 ° C.
The sample having the first layer 5 formed thereon as described above is immersed for 20 minutes, and then ultrasonic cleaning is performed twice with deionized water by changing the water washing tank and dried at 150 ° C. for 2 hours. A second layer 6 made of a palladium film containing phosphorus is formed on top.
【００２０】なお、この第二層６のリンを含むパラジウ
ム膜として、リンを１〜１０ｗｔ％含み、厚さ０．１ミ
クロン以上のパラジウムで構成するものとするが、その
根拠は、リンの含有量が１ｗｔ％未満ではめっきの付着
が不十分で、１０ｗｔ％を越えるとはんだ濡れ性が悪く
なり、また、第二層６のめっき厚さ０．１ミクロン未満
では、はんだ耐熱性及びはんだ濡れ性の経時変化に問題
があるなどの理由に基づくものであり、本発明者の実験
結果（第二層のめっき厚を蛍光Ｘ線分析機で測定した）
から、例えば、厚さ０．３ミクロンのパラジウム−リン
をメッキするのに１５〜２０分で容易に得ることができ
る。The palladium film containing phosphorus of the second layer 6 is made of palladium having a thickness of 0.1 micron or more containing 1 to 10 wt% of phosphorus. If the amount is less than 1 wt%, the adhesion of the plating is insufficient, and if it exceeds 10 wt%, the solder wettability deteriorates. If the plating thickness of the second layer 6 is less than 0.1 micron, the solder heat resistance and the solder wettability are deteriorated. It is based on the reason that there is a problem with the change with time of, and the experimental result of the present inventor (the plating thickness of the second layer was measured by a fluorescent X-ray analyzer).
, For example, it can be easily obtained in 15 to 20 minutes to plate palladium-phosphorus with a thickness of 0.3 micron.
【００２１】以上のような構成によれば、外部電極４の
外装がはんだ付け性及びはんだ耐熱性に優れるパラジウ
ム−リンであることから、従来の銀又は銀パラジウムか
らなる外部電極を有するセラミックチップコンデンサの
欠点が著しく改善される。According to the above-mentioned structure, since the outer electrode 4 is made of palladium-phosphorus which is excellent in solderability and solder heat resistance, the conventional ceramic chip capacitor having an external electrode made of silver or silver-palladium. The drawbacks of are significantly improved.
【００２２】また、前記最外装の形成手段は、セラミッ
クに悪影響を与えない弱アルカリ性のめっき液を用い、
短時間にめっきが終了できる無電解めっき液であること
から、従来のニッケル及びはんだ層を形成するための電
気めっき法に比べコンデンサの信頼性に悪影響を与える
ことがない。The means for forming the outermost package uses a weak alkaline plating solution that does not adversely affect the ceramics.
Since it is an electroless plating solution that can finish plating in a short time, it does not adversely affect the reliability of the capacitor as compared with the conventional electroplating method for forming nickel and solder layers.
【００２３】さらに、電気めっき法でみられるダミーの
無駄なめっき膜生成がないため、めっき液の消費が著し
く低減でき、製造コスト上も有利で、従来技術の課題を
一気に解決できる優れた効果を得ることが可能となる。Furthermore, since there is no useless dummy plating film formation as seen in the electroplating method, the consumption of the plating solution can be remarkably reduced, the manufacturing cost is also advantageous, and the excellent effect of being able to solve the problems of the prior art at a stretch. It becomes possible to obtain.
【００２４】また、第二層６形成に用いるめっき装置と
しては、めっき浴の容器、５０℃程度の温度調節装置、
上下に揺動を与える装置及び水洗槽などで工業的には非
常に簡単なものでよいことから、製造作業容易にして低
コスト化に貢献できるなどの効果をも有する。As the plating apparatus used for forming the second layer 6, a plating bath container, a temperature adjusting device at about 50 ° C.,
Since a device for vertically swinging, a washing tank, and the like can be industrially very simple, it also has an effect of facilitating manufacturing work and contributing to cost reduction.
【００２５】以下、実験結果に基づき本発明の実施例と
従来例の比較について述べる。すなわち、前述した構成
によって得られた図１に示す構成からなる実施例Ａと、
外部電極として実施例Ａと同じ第１層の外部電極層のみ
でめっきを行わない図２に示す構成からなる従来例Ｂ
と、外部電極として実施例Ａと同じ第一層の上に、公知
の方法でニッケル及びはんだ又はすずを電気めっきした
図３に示す構成からなる従来例ＣのＪＩＳ Ｃ ５１０
２によるはんだ付け性及びはんだ耐熱性試験、さらには
８５℃−８５％ＲＨで直流２Ｖ印加２０００時間の耐湿
負荷試験結果を表１及び表２に示す。The comparison between the example of the present invention and the conventional example will be described below based on the experimental results. That is, Example A having the configuration shown in FIG. 1 obtained by the above configuration,
Conventional example B having the structure shown in FIG. 2 in which only the first external electrode layer, which is the same as in example A, is not used as the external electrode for plating
And JIS C 510 of Conventional Example C having the structure shown in FIG. 3 in which nickel and solder or tin are electroplated by a known method on the same first layer as the external electrode.
Tables 1 and 2 show the solderability and solder heat resistance tests according to No. 2 and further the humidity resistance load test results under application of 2 V DC for 2000 hours at 85 ° C.-85% RH.
【００２６】なお、試料はいずれも定格５０Ｖ−０．１
μＦで、それぞれ１００個である。All samples are rated at 50V-0.1.
There are 100 μF each.
【００２７】[0027]
【表１】 [Table 1]
【００２８】[0028]
【表２】 [Table 2]
【００２９】表１及び表２から明らかなように、従来例
Ｂは耐湿負荷試験後における累積故障率は皆無である
が、はんだ付け性及びはんだ耐熱性特性が極度に悪く、
また、従来例Ｃははんだ付け性及びはんだ耐熱性におけ
る不良は皆無であるが、耐湿負荷試験において時間の経
過と共に故障率が増加し、両者とも実用上大きな問題を
抱える結果となったのに対して、実施例Ａははんだ付け
性及びはんだ耐熱性はもとより耐湿負荷特性においても
何ら問題なく、本発明の優れた効果を実証した。As is clear from Tables 1 and 2, the conventional example B has no cumulative failure rate after the moisture resistance load test, but the solderability and solder heat resistance characteristics are extremely poor.
Further, in Conventional Example C, although there were no defects in solderability and solder heat resistance, the failure rate increased with the passage of time in the moisture resistance load test, and both of them resulted in serious problems in practical use. In Example A, the excellent effect of the present invention was demonstrated without any problem in humidity resistance load characteristics as well as solderability and solder heat resistance.
【００３０】なお、上記実施例では、第一層形成手段と
して粉末状の銀とパラジウムにガラスフリットを添加し
た導電性ペーストを用いるものを例示して説明したが、
銀パラジウム合金粉末にガラスフリットを添加した導電
性ペーストを用いても同効である。In the above embodiments, the conductive paste prepared by adding glass frit to powdery silver and palladium is used as the first layer forming means.
The same effect can be obtained by using a conductive paste obtained by adding glass frit to silver-palladium alloy powder.
【００３１】[0031]
【発明の効果】以上のように本発明の方法によれば、従
来の銀又は銀パラジウム電極の欠点であるはんだ付け性
及びはんだ耐熱性において著しい改善が図られるととも
に、従来のニッケルとはんだの電気めっきの欠点である
信頼性も向上できる。さらに、従来の電気めっきより工
程を短縮でき、且つ製造装置も簡単なもので良いことか
らその工業的価値は大きい。As described above, according to the method of the present invention, the solderability and solder heat resistance, which are the drawbacks of the conventional silver or silver-palladium electrode, can be remarkably improved, and the electrical conductivity of conventional nickel and solder can be improved. The reliability, which is a drawback of plating, can also be improved. Further, the process is shorter than the conventional electroplating, and the manufacturing apparatus is simple, so that its industrial value is great.
【図１】本発明の一実施例に係るセラミックチップコン
デンサを示す正断面図。FIG. 1 is a front sectional view showing a ceramic chip capacitor according to an embodiment of the present invention.
【図２】従来例に係るセラミックチップコンデンサを示
す正断面図。FIG. 2 is a front sectional view showing a ceramic chip capacitor according to a conventional example.
【図３】他の従来例に係るセラミックチップコンデンサ
を示す正断面図。FIG. 3 is a front sectional view showing a ceramic chip capacitor according to another conventional example.
１ セラミック誘電体 ２ 内部電極 ３ セラミックコンデンサ素子 ４ 外部電極 ５ 第一層 ６ 第二層 1 Ceramic Dielectric 2 Internal Electrode 3 Ceramic Capacitor Element 4 External Electrode 5 First Layer 6 Second Layer
Claims (2)
層され、この内部電極が交互に露出された両端部に外部
電極を設けたセラミックチップコンデンサにおいて、前
記外部電極が銀パラジウム合金及びガラスフリットから
なる第一層と、リンを１〜１０ｗｔ％含む厚さ０．１ミ
クロン以上のパラジウムからなる第二層との２層構造か
らなることを特徴とするセラミックチップコンデンサ。1. A ceramic chip capacitor in which ceramic dielectrics and internal electrodes are alternately laminated, and external electrodes are provided at both ends where the internal electrodes are alternately exposed, wherein the external electrodes are made of silver-palladium alloy and glass frit. A ceramic chip capacitor having a two-layer structure of a first layer consisting of 1 to 10 wt% of phosphorus and a second layer consisting of palladium having a thickness of 0.1 micron or more and having a thickness of 0.1 micron or more.
層され、この内部電極が交互に露出された両端部に外部
電極を形成してなるセラミックチップコンデンサの製造
方法において、前記外部電極形成手段として、前記両端
面に粉末状の銀とパラジウム又は銀パラジウム合金粉末
にガラスフリットを添加した導電性ペーストを塗布−焼
成して第一層を形成し、次に、この第一層上にリン−パ
ラジウム無電解めっき法によりリンを１〜１０ｗｔ％含
む厚さ０．１ミクロン以上のパラジウム膜からなる第二
層を形成することを特徴とするセラミックチップコンデ
ンサの製造方法。2. A method of manufacturing a ceramic chip capacitor, wherein ceramic dielectrics and internal electrodes are alternately laminated, and external electrodes are formed on both ends of which the internal electrodes are alternately exposed. A conductive paste prepared by adding glass frit to powdered silver and palladium or silver-palladium alloy powder is applied to both end faces of the conductive paste to form a first layer, and then phosphorus-palladium is formed on the first layer. A method of manufacturing a ceramic chip capacitor, which comprises forming a second layer made of a palladium film having a thickness of 0.1 micron or more containing 1 to 10 wt% of phosphorus by an electroless plating method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35977692A JPH06204077A (en) | 1992-12-28 | 1992-12-28 | Ceramic chip capacitor and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP35977692A JPH06204077A (en) | 1992-12-28 | 1992-12-28 | Ceramic chip capacitor and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06204077A true JPH06204077A (en) | 1994-07-22 |
Family
ID=18466241
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35977692A Pending JPH06204077A (en) | 1992-12-28 | 1992-12-28 | Ceramic chip capacitor and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06204077A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111755249A (en) * | 2019-03-27 | 2020-10-09 | 三星电机株式会社 | Multilayer capacitor |
-
1992
- 1992-12-28 JP JP35977692A patent/JPH06204077A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111755249A (en) * | 2019-03-27 | 2020-10-09 | 三星电机株式会社 | Multilayer capacitor |
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