JPH06188379A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH06188379A JPH06188379A JP34003692A JP34003692A JPH06188379A JP H06188379 A JPH06188379 A JP H06188379A JP 34003692 A JP34003692 A JP 34003692A JP 34003692 A JP34003692 A JP 34003692A JP H06188379 A JPH06188379 A JP H06188379A
- Authority
- JP
- Japan
- Prior art keywords
- forming
- gate electrode
- type region
- metal film
- refractory metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関するもので、特にＧａＡｓなどの化合物半導体ＩＣ
の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a compound semiconductor IC such as GaAs.
The present invention relates to a manufacturing method of.
【０００２】[0002]
【従来の技術】近年、半導体の進歩はめざましくあらゆ
る分野で使用されている。特にＳｉ半導体の高集積化は
システムの小型化や高性能化に大きく寄与している。ま
た、化合物半導体ＩＣも集積度は低いものの実用化され
始めている。なかでも、ＧａＡｓＩＣはＳｉＩＣに比べ
て高速動作が可能や、低消費電力化が可能といった特徴
があり携帯電話をはじめとする移動体通信機器で実用化
が本格的に始まっている。2. Description of the Related Art In recent years, semiconductors have been remarkably used in various fields. In particular, high integration of Si semiconductors has greatly contributed to downsizing and high performance of the system. In addition, compound semiconductor ICs are beginning to be put to practical use although they have a low degree of integration. Among them, GaAsIC has characteristics that it can operate at higher speed and lower power consumption than SiIC, and has been put into practical use in mobile communication devices such as mobile phones.
【０００３】ＧａＡｓＩＣでは、能動素子としてＭＥＳ
ＦＥＴ（金属半導体接合型電界効果トランジスタ）が広
く用いられ、プロセスにおいては特性の高性能化、均一
化のために自己整合プロセスが一般的に用いられてい
る。この自己整合プロセスはイオン注入法を用いてソー
ス・ドレイン抵抗を下げるために、高融点金属からなる
ゲート金属を形成して、そのゲート金属をマスクとして
ゲート金属の両側に自己整合でキャリア濃度が高いソー
スドレイン領域を形成する方法である。一方、受動素子
としては抵抗素子および容量素子が主に用いられてい
る。In GaAs IC, MES is used as an active element.
FETs (metal-semiconductor junction type field effect transistors) are widely used, and in the process, a self-alignment process is generally used in order to achieve high performance and uniform characteristics. This self-alignment process uses an ion implantation method to reduce the source / drain resistance, so that a gate metal made of a refractory metal is formed, and the gate metal is used as a mask to self-align on both sides of the gate metal so that the carrier concentration is high. This is a method of forming a source / drain region. On the other hand, resistive elements and capacitive elements are mainly used as passive elements.
【０００４】従来のＧａＡｓＩＣの製造方法を図５
（ａ）−（ｄ）に示す。図５において２１は半絶縁性Ｇ
ａＡｓ基板、２２は活性層、２３はゲート電極、２４は
ｎ型高濃度層、２５はオーミック電極、２６は絶縁膜、
２７は抵抗素子、２８は金属配線、２９は保護膜であ
る。半絶縁性ＧａＡｓ基板２１にイオン注入で活性層２
２を形成し、高融点金属薄膜例えばＷＳｉを全面に形成
し所望のゲート電極２３に形成する（ａ）。次にオーミ
ックコンタクト形成のためにｎ型高濃度層２４をイオン
注入で形成し、注入層の活性化のためにアニールを行う
（ｂ）。その後、オーミック電極２５を形成し、全面に
絶縁膜２６例えばシリコン窒化膜を堆積後、薄膜例えば
ＷＳｉＮで抵抗素子２７を形成する（ｃ）。次に、ゲー
ト電極およびオーミック電極のコンタクトを開口し金属
配線２８を引き回し、最後に保護膜２９を形成してＧａ
ＡｓＩＣを完成する（ｄ）。A conventional GaAs IC manufacturing method is shown in FIG.
It shows in (a)-(d). In FIG. 5, 21 is semi-insulating G
aAs substrate, 22 active layer, 23 gate electrode, 24 n-type high concentration layer, 25 ohmic electrode, 26 insulating film,
Reference numeral 27 is a resistance element, 28 is a metal wiring, and 29 is a protective film. The active layer 2 is formed by ion implantation into the semi-insulating GaAs substrate 21.
2, a refractory metal thin film such as WSi is formed on the entire surface to form a desired gate electrode 23 (a). Next, the n-type high concentration layer 24 is formed by ion implantation for ohmic contact formation, and annealing is performed for activation of the implantation layer (b). After that, an ohmic electrode 25 is formed, an insulating film 26 such as a silicon nitride film is deposited on the entire surface, and then a resistance element 27 is formed of a thin film such as WSiN (c). Next, the contacts of the gate electrode and the ohmic electrode are opened, the metal wiring 28 is laid out, and finally the protective film 29 is formed to form Ga.
Complete the AsIC (d).
【０００５】[0005]
【発明が解決しようとする課題】しかしながら前述のよ
うな従来のＧａＡｓＩＣの製造方法ではＦＥＴ、抵抗素
子および配線の製造がそれぞれ別々の工程からなり、総
工程数はかなりの数となりリードタイムの増加や製造コ
ストの増大、ましては歩留低下の大きな原因となるとい
う問題があった。However, in the conventional GaAs IC manufacturing method as described above, the manufacturing of the FET, the resistance element and the wiring comprises separate steps, and the total number of steps increases considerably, leading to an increase in lead time. There has been a problem that this is a major cause of an increase in manufacturing cost and a decrease in yield.
【０００６】本発明は、このような課題を解決して自己
整合プロセスにおけるＧａＡｓＩＣの製造工程で、ひと
つの素子の製造工程で他の素子も製造することにより工
程の大幅な短縮を実現し、しいては歩留の向上を図れる
半導体装置の製造方法を提供することである。The present invention solves such a problem and realizes a drastic reduction in the process by manufacturing one device in the GaAs IC manufacturing process in the self-alignment process and the other device. Another object of the present invention is to provide a method for manufacturing a semiconductor device that can improve the yield.
【０００７】[0007]
【課題を解決するための手段】本発明は上記課題を解決
するために、半導体基板にイオン注入によりｎ型領域を
形成する工程と、全面に高融点金属膜を形成する工程
と、前記ｎ型領域上の前記高融点金属膜を加工しゲート
電極および抵抗素子を形成する工程と、前記ゲート電極
の両側にソース・ドレイン高濃度領域を形成する工程
と、注入イオンの活性化を行なうためのアニールを行う
工程からなる。In order to solve the above problems, the present invention provides a step of forming an n-type region in a semiconductor substrate by ion implantation, a step of forming a refractory metal film on the entire surface, and the n-type region. A step of processing the refractory metal film on the region to form a gate electrode and a resistance element; a step of forming source / drain high-concentration regions on both sides of the gate electrode; and an anneal for activating implanted ions. Is performed.
【０００８】また、本発明は半導体基板にイオン注入に
よりｎ型領域を形成する工程と、全面に高融点金属膜を
形成する工程と、前記ｎ型領域上の前記高融点金属膜を
ゲート電極および配線パターンに形成する工程と、前記
ゲート電極の両側にソース・ドレイン高濃度領域を形成
する工程と、注入イオンの活性化を行なうためのアニー
ルを行う工程と、オーッミック金属を前記ソース・ドレ
イン領域上および前記配線パターン上に形成する工程
と、シンターによりオーッミック電極を形成する工程か
らなる。Further, according to the present invention, a step of forming an n-type region in a semiconductor substrate by ion implantation, a step of forming a refractory metal film on the entire surface, and a step of forming the refractory metal film on the n-type region as a gate electrode and Forming a wiring pattern, forming source / drain high concentration regions on both sides of the gate electrode, annealing for activating implanted ions, and ohmic metal on the source / drain regions. And a step of forming on the wiring pattern and a step of forming an ohmic electrode by sintering.
【０００９】[0009]
【作用】本発明は上述したように、高融点金属を用いた
自己整合プロセスによるＧａＡｓＩＣの製造方法で、高
融点金属ゲート形成時に抵抗素子を形成することや、高
融点金属とオーミック金属を用いて配線を形成すること
により従来行っていた工程を大幅に省略することができ
るのでＧａＡｓＩＣプロセスの工程の短縮、しいては歩
留の向上を図ることができる。As described above, the present invention is a method for manufacturing a GaAs IC by a self-alignment process using a refractory metal, and by forming a resistance element at the time of forming a refractory metal gate, and using a refractory metal and an ohmic metal. By forming the wiring, the steps conventionally performed can be largely omitted, so that the steps of the GaAs IC process can be shortened and the yield can be improved.
【００１０】[0010]
【実施例】（実施例１）図１（ａ）〜（ｄ）に本発明半
導体装置の製造方法の第１の実施例を示す。図１におい
て１は半絶縁性ＧａＡｓ基板、２はｎ型領域、３はゲー
ト電極、４は抵抗素子、５はｎ型高濃度層、６はオーミ
ック電極、７は絶縁膜、８は金属配線、９は保護膜であ
る。半絶縁性ＧａＡｓ基板１にイオン注入でＦＥＴの活
性層および抵抗部にｎ型領域２を形成し、高融点金属薄
膜例えばＷＳｉを全面に形成した後、前記ｎ型領域２上
の前記高融点金属をゲート電極３および抵抗素子４に加
工する（ａ）。次に前記ゲート電極３の両側にソース・
ドレイン電極形成のためのｎ型高濃度層５をイオン注入
で形成し、活性化のためのアニールを行う（ｂ）。その
後、オーミック電極６を形成し、全面に絶縁膜７例えば
シリコン窒化膜を堆積する（ｃ）。次に、ゲート電極
３、オーミック電極６および抵抗素子４のコンタクトを
開口し金属配線８を形成し、最後に保護膜９を形成して
ＧａＡｓＩＣを完成する（ｄ）。(Embodiment 1) FIGS. 1A to 1D show a first embodiment of a method for manufacturing a semiconductor device of the present invention. In FIG. 1, 1 is a semi-insulating GaAs substrate, 2 is an n-type region, 3 is a gate electrode, 4 is a resistance element, 5 is an n-type high concentration layer, 6 is an ohmic electrode, 7 is an insulating film, 8 is a metal wiring, 9 is a protective film. After the n-type region 2 is formed in the active layer and the resistance portion of the FET by ion implantation on the semi-insulating GaAs substrate 1 and a refractory metal thin film, for example, WSi is formed on the entire surface, the refractory metal on the n-type region 2 is formed. Is processed into the gate electrode 3 and the resistance element 4 (a). Next, the source on both sides of the gate electrode 3
An n-type high concentration layer 5 for forming a drain electrode is formed by ion implantation, and annealing for activation is performed (b). After that, the ohmic electrode 6 is formed, and the insulating film 7 such as a silicon nitride film is deposited on the entire surface (c). Next, the contacts of the gate electrode 3, the ohmic electrode 6 and the resistance element 4 are opened to form the metal wiring 8, and finally the protective film 9 is formed to complete the GaAs IC (d).
【００１１】第１の実施例ではゲート電極３と抵抗素子
４は同一の高融点金属で同一の工程で形成されており、
工程の簡略化が図れる。また、本実施例では抵抗素子４
に接するＧａＡｓ基板をｎ型層に形成しているため、図
２に示すようなショットキ電極を半絶縁性ＧａＡｓ基板
上に形成したときに近傍のオーミック電極間に発生する
異常リークを防止することができる。そして、このｎ型
層もＦＥＴの活性層と同時に形成するため工程の増加は
ない。In the first embodiment, the gate electrode 3 and the resistance element 4 are made of the same refractory metal in the same step,
The process can be simplified. Further, in this embodiment, the resistance element 4
Since the GaAs substrate in contact with the n-type layer is formed in the n-type layer, it is possible to prevent abnormal leakage that occurs between the ohmic electrodes in the vicinity when the Schottky electrode as shown in FIG. 2 is formed on the semi-insulating GaAs substrate. it can. Since this n-type layer is also formed at the same time as the active layer of the FET, the number of steps is not increased.
【００１２】（実施例２）図３（ａ）〜（ｄ）に本発明
半導体装置の製造方法の第２の実施例を示す。図３にお
いて１１は半絶縁性ＧａＡｓ基板、１２はｎ型領域、１
３はゲート電極、１４は配線パターン、１５はｎ型高濃
度層、１６はオーミック電極、１７第１の金属配線、１
８は絶縁膜、１９は第２の金属配線、２０は保護膜であ
る。半絶縁性ＧａＡｓ基板１１にイオン注入でＦＥＴの
活性層および配線部にｎ型領域１２を形成し、高融点金
属薄膜例えばＷＳｉを全面に形成した後、前記ｎ型領域
１２上の前記高融点金属膜をゲート電極１３および配線
パターン１４に加工する（ａ）。次に前記ゲート電極１
３の両側にソース・ドレイン領域形成のためのｎ型高濃
度層１５をイオン注入で形成し、活性化のためのアニー
ルを行う（ｂ）。その後、オーッミク金属を前記ソース
・ドレイン領域および前記配線パターン１４上に形成
し、シンターによりオーミック電極１６および第１の金
属配線１７を形成し、全面に絶縁膜１８例えばシリコン
窒化膜を堆積する（ｃ）。次に、ゲート電極１３、オー
ミック電極１６および第１の金属配線１７よりコンタク
トを開口し第２の金属配線１９を形成し、最後に保護膜
２０を形成してＧａＡｓＩＣを完成する（ｄ）。(Embodiment 2) FIGS. 3A to 3D show a second embodiment of the method for manufacturing a semiconductor device of the present invention. In FIG. 3, 11 is a semi-insulating GaAs substrate, 12 is an n-type region, 1
3 is a gate electrode, 14 is a wiring pattern, 15 is an n-type high concentration layer, 16 is an ohmic electrode, 17 is a first metal wiring, 1
Reference numeral 8 is an insulating film, 19 is a second metal wiring, and 20 is a protective film. After the n-type region 12 is formed in the active layer and the wiring portion of the FET by ion implantation in the semi-insulating GaAs substrate 11 and a refractory metal thin film, for example, WSi is formed on the entire surface, the refractory metal on the n-type region 12 is formed. The film is processed into the gate electrode 13 and the wiring pattern 14 (a). Next, the gate electrode 1
An n-type high concentration layer 15 for forming source / drain regions is formed on both sides of 3 by ion implantation, and annealing for activation is performed (b). After that, ohmic metal is formed on the source / drain regions and the wiring pattern 14, the ohmic electrode 16 and the first metal wiring 17 are formed by sintering, and an insulating film 18 such as a silicon nitride film is deposited on the entire surface (c). ). Next, a contact is opened from the gate electrode 13, the ohmic electrode 16 and the first metal wiring 17 to form a second metal wiring 19, and finally a protective film 20 is formed to complete the GaAs IC (d).
【００１３】第２の実施例は、集積度が高くなり２層配
線を余儀なくされる昨今のＧａＡｓＩＣにおいて、従来
の１層配線を本発明のゲート高融点金属／オーミック金
属配線に置き換えることにより１層配線プロセスで製造
できることになる。このことは、２層目配線の形成工程
を省略できるだけでなく層間膜の形成工程およびコンタ
クト形成工程といった大幅な工程数の削減になる。ま
た、本発明ではオーミック金属とゲート金属の２層構造
としているが、この構造は通常オーミック電極形成時に
起こるＧａＡｓとオーッミク金属の合金化反応を高融点
金属で防止することができる。図４に本発明の配線金属
のシート抵抗値とオーミック電極のシート抵抗値の４５
０℃熱処理による変化を示す。５分の熱処理でオーミッ
ク電極ではシート抵抗値が１０倍にも大きくなるが、本
発明の配線金属ではほとんど変化はな句安定しているこ
とがわかる。In the second embodiment, in a recent GaAs IC in which the degree of integration is increased and two-layer wiring is inevitable, the conventional one-layer wiring is replaced with the gate refractory metal / ohmic metal wiring of the present invention to form one layer. It can be manufactured by the wiring process. This not only eliminates the step of forming the second layer wiring, but also significantly reduces the number of steps such as the step of forming an interlayer film and the step of forming a contact. Further, in the present invention, a two-layer structure of ohmic metal and gate metal is used, but this structure can prevent the alloying reaction of GaAs and ohmic metal that normally occurs at the time of forming an ohmic electrode with a refractory metal. FIG. 4 shows a sheet resistance value of the wiring metal of the present invention and a sheet resistance value of the ohmic electrode of 45.
The change due to 0 ° C. heat treatment is shown. It can be seen that the sheet resistance value of the ohmic electrode is increased ten times by the heat treatment for 5 minutes, but the wiring metal of the present invention is stable with almost no change.
【００１４】なお、本発明第１および第２の実施例で高
融点金属膜にＷＳｉ用いたが、高融点金属はこれに限ら
ずＷＳｉＮなど他の高融点金属膜であっても良い。Although WSi is used for the refractory metal film in the first and second embodiments of the present invention, the refractory metal is not limited to this and may be another refractory metal film such as WSiN.
【００１５】[0015]
【発明の効果】上述したように本発明は、高融点金属を
用いた自己整合プロセスによるＧａＡｓＩＣの製造方法
で、高融点金属ゲート形成時に抵抗素子を形成すること
や、高融点金属とオーミック金属を用いて配線を形成す
ることにより従来行っていた工程を大幅に省略すること
ができるのでＧａＡｓＩＣプロセスの工程の短縮、しい
ては歩留の向上を図ることができる。As described above, the present invention is a method of manufacturing a GaAs IC by a self-alignment process using a refractory metal, in which a resistive element is formed at the time of forming a refractory metal gate, and a refractory metal and an ohmic metal are formed. By using the wiring to form the wiring, the steps conventionally performed can be largely omitted, so that the steps of the GaAs IC process can be shortened and the yield can be improved.
【図１】本発明第１の実施例を示す工程断面FIG. 1 is a process cross section showing a first embodiment of the present invention.
【図２】本発明の効果を示す図FIG. 2 is a diagram showing the effect of the present invention.
【図３】本発明第２の実施例を示す工程断面FIG. 3 is a process cross section showing a second embodiment of the present invention.
【図４】本発明の効果を示す図FIG. 4 is a diagram showing the effect of the present invention.
【図５】従来の半導体装置の製造方法を示す工程断面図5A to 5C are process sectional views showing a conventional method for manufacturing a semiconductor device.
１ 半導体基板 ２ ｎ型領域 ３ ゲート電極 ４ 抵抗素子 ５ ｎ型高濃度層 ６ オーミック電極 1 semiconductor substrate 2 n-type region 3 gate electrode 4 resistance element 5 n-type high concentration layer 6 ohmic electrode
Claims (5)
形成する工程と、全面に高融点金属膜を形成する工程
と、前記ｎ型領域上の前記高融点金属膜を加工しゲート
電極および抵抗素子を形成する工程と、前記ゲート電極
の両側にソース・ドレイン高濃度領域を形成する工程
と、注入イオンの活性化を行なうためのアニールを行う
工程を有することを特徴とする半導体装置の製造方法。1. A step of forming an n-type region in a semiconductor substrate by ion implantation, a step of forming a refractory metal film on the entire surface, and a step of processing the refractory metal film on the n-type region to form a gate electrode and a resistor. A method of manufacturing a semiconductor device, comprising: a step of forming an element; a step of forming high-concentration source / drain regions on both sides of the gate electrode; and a step of annealing to activate implanted ions. .
形成する工程と、全面に高融点金属膜を形成する工程
と、前記ｎ型領域上の前記高融点金属膜をゲート電極お
よび配線パターンに形成する工程と、前記ゲート電極の
両側にソース・ドレイン高濃度領域を形成する工程と、
注入イオンの活性化を行なうためのアニールを行う工程
と、オーッミック金属を前記ソース・ドレイン領域上お
よび前記配線パターン上に形成する工程と、シンターに
よりオーッミック電極を形成する工程を有することを特
徴とする半導体装置の製造方法。2. A step of forming an n-type region in a semiconductor substrate by ion implantation, a step of forming a refractory metal film on the entire surface, and a step of forming the refractory metal film on the n-type region into a gate electrode and a wiring pattern. Forming a source / drain high-concentration region on both sides of the gate electrode;
The method has a step of performing annealing for activating the implanted ions, a step of forming ohmic metal on the source / drain regions and the wiring pattern, and a step of forming an ohmic electrode by sintering. Manufacturing method of semiconductor device.
イドからなることを特徴とする請求項１または請求項２
記載の半導体装置の製造方法。3. The refractory metal film is made of a silicide containing tungsten.
A method for manufacturing a semiconductor device as described above.
記ｎ型領域上にあることを特徴とする請求項１記載の半
導体装置の製造方法。4. A method of manufacturing a semiconductor device according to claim 1, wherein a resistance element formed by processing a refractory metal film is entirely on the n-type region.
面前記ｎ型領域上にあることを特徴とする請求項２記載
の半導体装置の製造方法。5. The method of manufacturing a semiconductor device according to claim 2, wherein a wiring pattern formed by processing a refractory metal film is entirely on the n-type region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4340036A JP2996034B2 (en) | 1992-12-21 | 1992-12-21 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4340036A JP2996034B2 (en) | 1992-12-21 | 1992-12-21 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06188379A true JPH06188379A (en) | 1994-07-08 |
| JP2996034B2 JP2996034B2 (en) | 1999-12-27 |
Family
ID=18333128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4340036A Expired - Fee Related JP2996034B2 (en) | 1992-12-21 | 1992-12-21 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2996034B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6255679B1 (en) | 1998-06-29 | 2001-07-03 | Nec Corporation | Field effect transistor which can operate stably in millimeter wave band |
-
1992
- 1992-12-21 JP JP4340036A patent/JP2996034B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6255679B1 (en) | 1998-06-29 | 2001-07-03 | Nec Corporation | Field effect transistor which can operate stably in millimeter wave band |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2996034B2 (en) | 1999-12-27 |
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