JPH0618392A - Method for testing thermal shock resistance of chip-type electronic part - Google Patents
Method for testing thermal shock resistance of chip-type electronic partInfo
- Publication number
- JPH0618392A JPH0618392A JP17306692A JP17306692A JPH0618392A JP H0618392 A JPH0618392 A JP H0618392A JP 17306692 A JP17306692 A JP 17306692A JP 17306692 A JP17306692 A JP 17306692A JP H0618392 A JPH0618392 A JP H0618392A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic capacitor
- thermal shock
- chip
- type electronic
- terminal electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000035939 shock Effects 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title abstract description 9
- 239000000919 ceramic Substances 0.000 claims abstract description 16
- 238000010998 test method Methods 0.000 claims description 25
- 238000007747 plating Methods 0.000 claims description 18
- 239000003985 ceramic capacitor Substances 0.000 abstract description 32
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 18
- 229910000679 solder Inorganic materials 0.000 description 18
- 238000005476 soldering Methods 0.000 description 11
- 230000002950 deficient Effects 0.000 description 9
- 229910052742 iron Inorganic materials 0.000 description 9
- 239000007787 solid Substances 0.000 description 7
- 230000007547 defect Effects 0.000 description 5
- 239000000843 powder Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000005304 joining Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 239000006071 cream Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000010409 ironing Methods 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000010802 sludge Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N33/00—Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
- G01N33/38—Concrete; Lime; Mortar; Gypsum; Bricks; Ceramics; Glass
- G01N33/388—Ceramics
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はチップ型コンデンサ、チ
ップ型抵抗器などのチップ型電子部品の耐熱衝撃試験方
法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal shock test method for chip type electronic parts such as chip type capacitors and chip type resistors.
【０００２】[0002]
【従来の技術】チップ型電子部品であるチップ型積層セ
ラミックコンデンサ１０は、図２に示すように、焼結し
た複数の矩形状のセラミック層１と、該セラミック層１
間に配置された内部電極２ａ、２ｂとが互いに積層さ
れ、さらにこの積層体の対向する端面に端子電極３ａ、
３ｂが形成されている。2. Description of the Related Art As shown in FIG. 2, a chip-type monolithic ceramic capacitor 10 which is a chip-type electronic component has a plurality of sintered rectangular ceramic layers 1 and the ceramic layers 1.
The internal electrodes 2a and 2b arranged between them are laminated on each other, and the terminal electrodes 3a,
3b is formed.
【０００３】内部電極２ａ、２ｂは、セラミック層１よ
りも小さな矩形状を成し、内部電極２ａの一方の端部が
積層体の一方端部から露出しており、この内部電極２ａ
の一方端部が端子電極３ａと接続されている。また、内
部電極２ｂの一方端部が積層体の他方端部から露出して
おり、この内部電極２ｂの他方端部が端子電極３ｂと接
続されている。The internal electrodes 2a and 2b have a rectangular shape smaller than the ceramic layer 1, and one end of the internal electrode 2a is exposed from one end of the laminated body.
One end is connected to the terminal electrode 3a. Further, one end of the internal electrode 2b is exposed from the other end of the laminated body, and the other end of the internal electrode 2b is connected to the terminal electrode 3b.
【０００４】上述の端子電極３ａ、３ｂは、Ａｇの導電
性粉末とガラスフリットを主成分とするＡｇペーストを
塗布し、焼き付けをおこなった厚み５０〜１００μｍの
厚膜下地層３１ａ、３１ｂと、該下地層３１ａ、３１ｂ
の表面を覆う厚み３〜１５μｍのメッキ層から構成され
ている。尚、図では、メッキ層として、Ｎｉメッキ層、
Ｓｎメッキ層の２層（３２ａ、３３ａ及び３２ｂ、３３
ｂ）構造となっている。The above-mentioned terminal electrodes 3a and 3b are thick film underlayers 31a and 31b having a thickness of 50 to 100 .mu.m, which are obtained by applying an Ag conductive powder and Ag paste containing glass frit as main components and baking them. Underlayer 31a, 31b
Is formed of a plating layer having a thickness of 3 to 15 μm that covers the surface of. In the figure, as the plating layer, a Ni plating layer,
Two Sn plating layers (32a, 33a and 32b, 33)
b) It has a structure.
【０００５】また、図示していないが、チップ型抵抗器
は、矩形状のセラミック基板の両端部の表面、端面、裏
面に夫々端子電極の厚膜下地層が形成されており、この
両単部の表面端子電極の下地層間に厚膜抵抗体膜が形成
され、さらに抵抗体膜状に絶縁保護膜が形成され、最後
に、端子電極の厚膜下地層上にメッキ層が形成されてい
る。Although not shown, the chip-type resistor has a thick-film underlayer of a terminal electrode formed on the front surface, the end surface, and the back surface of both ends of a rectangular ceramic substrate, respectively. A thick film resistor film is formed between the underlayers of the surface terminal electrodes, an insulating protective film is further formed in the form of a resistor film, and finally, a plating layer is formed on the thick film underlayer of the terminal electrodes.
【０００６】従来、このようなチップ型電子部品の耐熱
衝撃試験として、特開平１−２１４７７５、特開平２−
１８７６４５、特開平２−２４９９４６に示すように、
加熱状態の電子部品を急冷したり、加熱、冷却手段で、
加熱−冷却−加熱などの温度サイクルをしていた。何れ
も従来の加熱、冷却の勾配が緩やかであり、実際のラッ
プ型電子部品の回路基板実装方法に適した耐熱衝撃試験
方法ではなかった。[0006] Conventionally, as a thermal shock test for such a chip type electronic component, Japanese Patent Application Laid-Open No. 1-214775 and Japanese Patent Application Laid-Open No. 2-214775.
187645, as shown in JP-A-2-249946,
By rapidly cooling the electronic parts that are in a heated state, or by heating and cooling means,
A temperature cycle of heating-cooling-heating was performed. In both cases, the conventional heating and cooling gradients were gentle, and they were not thermal shock test methods suitable for actual circuit board mounting methods for lap-type electronic components.
【０００７】チップ型電子部品の回路基板実装方法とし
ては、回路基板に形成した配線パッド上にクリーム半田
を塗布して、このクリーム半田上にチップ型電子部品を
載置・保持し、約２６０℃のリフロー炉でクリーム半田
を溶融させ、常温に戻して接合するリフロー方法や回路
基板に形成した配線パッド上にチップ型電子部品を載置
し、糸半田を半田ゴテで溶融させ、半田接合するコテ付
け方法があった。As a method for mounting a chip-type electronic component on a circuit board, a cream solder is applied to a wiring pad formed on the circuit board, and the chip-type electronic component is placed and held on the cream solder at about 260 ° C. Reflow method to melt the cream solder in the reflow oven, then return to room temperature for bonding, or place the chip type electronic component on the wiring pad formed on the circuit board, melt the solder wire with the soldering iron, and solder There was a way to put it.
【０００８】このため、実際の半田接合に対応する耐熱
衝撃試験として、例えば、セラミックを、１ロットあた
り、所定割合で抜き取り、抜き取った積層セラミックコ
ンデンサ１０の端子電極３ａ、３ｂ部分を、３００℃前
後の半田溶融した半田槽内に、１秒間浸漬して、その
後、静電容量、絶縁抵抗等を測定し、その抜き取ったロ
ットの積層セラミックコンデンサ１０の全品の良・不良
を判断していた。Therefore, as a thermal shock test corresponding to actual solder joining, for example, ceramics are extracted at a predetermined rate per lot, and the extracted terminal electrodes 3a and 3b of the laminated ceramic capacitor 10 are heated to about 300.degree. It was immersed in the solder-melted solder bath for 1 second for 1 second, and then the electrostatic capacity, the insulation resistance, etc. were measured, and the good or bad of all the multilayer ceramic capacitors 10 of the extracted lot was judged.
【０００９】ここで、上述の試験で不良となる原因は、
下地層３１ａ、３１ｂの導体成分とガラス成分との間に
空孔が形成され、この空孔にメッキ液などの水分が含浸
した状態で、表面にメッキ層３２ａ、３２ｂ、３３ａ、
３３ｂを覆われることがある。この時、２８０℃前後の
熱によって、前記水分が膨張して、端子電極３ａ、３ｂ
の下地層３１ａ、３１ｂとメッキ層３２ａ、３２ｂとの
間の剥離が発生してしまうことがその原因であった。Here, the cause of failure in the above test is
Voids are formed between the conductor component and the glass component of the underlayers 31a and 31b, and the surfaces of the plating layers 32a, 32b and 33a are impregnated with water such as a plating solution.
33b may be covered. At this time, the moisture expands due to the heat of about 280 ° C., and the terminal electrodes 3a, 3b
The reason for this is that peeling occurs between the underlying layers 31a and 31b and the plated layers 32a and 32b.
【００１０】しかし、上述の３００℃前後の半田槽内に
浸漬させて耐熱衝撃試験で良品と判断された積層セラミ
ックコンデンサ１０において、上述のコテ付け方法によ
って回路基板上に半田接合した場合、直接、半田ゴテの
熱が端子電極３ａ、３ｂに印加され、その熱によって、
端子電極３ａ、３ｂ内の水分が突沸して、端子電極３
ａ、３ｂの破損（端子電極３ａ、３ｂの厚膜下地層３１
ａ、３１ｂとメッキ層３２ａ、３２ｂとの界面での剥
離、セラミック層１と厚膜下地層３１ａ、３１ｂとメッ
キ層３２ａ、３２ｂとの界面での剥離、端子電極３ａ、
３ｂの亀裂）が発生しまうことがあった。However, when the monolithic ceramic capacitor 10 which is judged to be a good product by the thermal shock test by immersing it in a solder bath at about 300 ° C. is soldered on the circuit board by the above-mentioned ironing method, it is directly The heat of the soldering iron is applied to the terminal electrodes 3a and 3b, and by the heat,
Moisture in the terminal electrodes 3a, 3b is bumped to cause the terminal electrodes 3
a, 3b damage (thick film base layer 31 of the terminal electrodes 3a, 3b)
a, 31b at the interface between the plated layers 32a, 32b, at the interface between the ceramic layer 1 and the thick film base layers 31a, 31b and the plated layers 32a, 32b, at the terminal electrode 3a,
3b).
【００１１】さらに最悪の場合には、端子電極３ａ、３
ｂに半田ゴテをあてて、糸半田を溶融している最中に、
端子電極３ａ、３ｂ内に含浸した水分が突沸して、メッ
キ層３２ａ、３２ｂ、３３ａ、３３ｂを勢いよく破壊
し、溶融した半田を２０〜３０ｃｍも跳ね上がらせるこ
とがあり、作業者にとって危険な作業となることがあっ
た。In the worst case, the terminal electrodes 3a, 3
While applying the soldering iron to b and melting the solder wire,
Moisture impregnated in the terminal electrodes 3a, 3b may suddenly boil and violently destroy the plated layers 32a, 32b, 33a, 33b, causing molten solder to bounce up to 20 to 30 cm, which is a dangerous work for workers. Was sometimes.
【００１２】これは、上述の耐熱衝撃試験においては、
約３００℃の温度条件では、良品とされていたものの、
半田ゴテの先端温度が４００℃前後にまで達してしま
い、この急激な熱によって端子電極３ａ、３ｂ内に存在
する水分が突沸するものと考えられる。In the above thermal shock test,
Although it was regarded as a good product under the temperature condition of about 300 ° C,
It is considered that the tip temperature of the soldering iron reaches around 400 ° C., and the water present in the terminal electrodes 3a and 3b bumps due to this abrupt heat.
【００１３】本発明は上述の問題点に鑑みて案出された
ものであり、その目的は、信頼性のより高く、簡単なチ
ップ型電子部品の耐熱試験方法を提供することである。The present invention has been devised in view of the above-mentioned problems, and an object thereof is to provide a highly reliable and simple heat resistance test method for a chip-type electronic component.
【００１４】[0014]
【課題を解決するための手段】上記課題に鑑みて、本発
明は単板又は積層セラミック体の端部に、導電性厚膜下
地層、表面メッキ層からなる端子電極を形成したチップ
型電子部品の耐熱衝撃試験方法であって、前記チップ型
電子部品を、４００〜５００℃で加熱したホットプレー
トに載置した後、各種特性を検査するすることを特徴す
るチップ型電子部品の耐熱衝撃試験方法である。In view of the above problems, the present invention provides a chip type electronic component in which a terminal electrode composed of a conductive thick film underlayer and a surface plating layer is formed at the end of a single plate or a laminated ceramic body. The thermal shock test method for chip type electronic parts, comprising: mounting the chip type electronic part on a hot plate heated at 400 to 500 ° C., and then inspecting various characteristics. Is.
【００１５】[0015]
【作用】上述の試験方法により、４００〜５００℃で加
熱されたホットプレートに載置した後、各種特性が測定
される。即ち、チップ型電子部品の端子電極が急激に加
熱されるため、半田ゴテによるコテ付け方法などの厳し
い条件下で、半田接合しても、端子電極の破損や特性の
劣化がない耐熱衝撃性が向上したチップ型電子部品の良
・不良が簡単に判別できる。According to the above-mentioned test method, various characteristics are measured after mounting on a hot plate heated at 400 to 500 ° C. That is, since the terminal electrodes of the chip-type electronic component are rapidly heated, even under soldering under severe conditions such as the soldering iron method, the terminal electrodes will not be damaged or their characteristics will not deteriorate even if they are soldered. It is possible to easily determine whether the improved chip-type electronic component is good or bad.
【００１６】[0016]
【実施例】以下、本発明を図面に基づいて説明する。図
１は本発明の耐熱衝撃試験方法の実施状態を示す概略図
である。尚、実施例では、チップ型電子部品としては図
２に示す積層セラミックコンデンサで説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a schematic view showing an implementation state of the thermal shock test method of the present invention. In the examples, the multilayer ceramic capacitor shown in FIG. 2 will be described as the chip type electronic component.
【００１７】積層セラミックコンデンサ１０は、複数の
焼結された矩形状の誘電体セラミック層１と複数の内部
電極２ａ、２ｂを積層されている。また、誘電体セラミ
ック層１と内部電極２ａ、２ｂとの積層体の両端部に端
子電極３ａ、３ｂが形成され、構成されている。The monolithic ceramic capacitor 10 is formed by laminating a plurality of sintered rectangular dielectric ceramic layers 1 and a plurality of internal electrodes 2a, 2b. Further, terminal electrodes 3a and 3b are formed and configured at both ends of the laminated body of the dielectric ceramic layer 1 and the internal electrodes 2a and 2b.
【００１８】概略的な製造方法は図２に示すように、ま
ず、誘電体セラミック層１となるシートを成型する。具
体的に、ＢａＴｉＯ3 などの主成分となる粉体、所定の
添加物とを秤量、混合し、仮焼を行う。さらに、仮焼体
を粉砕して、バインダーを混合して、泥漿状態のセラミ
ック材料を生成し、さらに、ドクターブレード法など
で、厚み２０〜１５０μｍのシートを成型する。As shown in FIG. 2, the schematic manufacturing method first forms a sheet to be the dielectric ceramic layer 1. Specifically, powders as a main component such as BaTiO 3 and predetermined additives are weighed and mixed, and calcined. Further, the calcined body is crushed and mixed with a binder to produce a ceramic material in a sludge state, and further, a sheet having a thickness of 20 to 150 μm is formed by a doctor blade method or the like.
【００１９】次に、上述のシート上に、内部電極２ａ、
２ｂとなるパターンを印刷する。Next, on the above-mentioned sheet, the internal electrodes 2a,
2b is printed.
【００２０】具体的にはＡｇ−Ｐｄ又はＰｄの導体粉末
と有機ビヒクルからなる導電性ペーストをスクリーン印
刷によって形成する。Specifically, a conductive paste composed of Ag-Pd or Pd conductor powder and an organic vehicle is formed by screen printing.
【００２１】次に、内部電極２ａ、２ｂのパターンを形
成したシートを積層する。具体的には静電容量特性に応
じて所定枚数のシートを、内部電極２ａ、２ｂのパター
ンの一端が、後述の切断時に、夫々異なる端部になるよ
うに積層して、所定圧力を印加する。Next, sheets having the patterns of the internal electrodes 2a and 2b are laminated. Specifically, a predetermined number of sheets are laminated so that one ends of the patterns of the internal electrodes 2a and 2b become different end portions when cutting, which will be described later, according to the capacitance characteristics, and a predetermined pressure is applied. .
【００２２】次に、上述したシート積層体を、個々のチ
ップ形状に裁断する。Next, the above-mentioned sheet laminated body is cut into individual chip shapes.
【００２３】次に、チップ形状の積層体を脱バインダー
した後、焼結を行う。これにより、シートは焼結反応に
より、セラミック層１となり、内部電極２ａ、２ｂのパ
ターンが焼結され、内部電極２ａ、２ｂとなる。Next, the chip-shaped laminate is debindered and then sintered. As a result, the sheet becomes the ceramic layer 1 by the sintering reaction, and the patterns of the internal electrodes 2a and 2b are sintered to become the internal electrodes 2a and 2b.
【００２４】次に、焼結されたチップ状の焼結体の端部
に端子電極３ａ、３ｂを形成する。Next, the terminal electrodes 3a and 3b are formed on the ends of the sintered chip-shaped sintered body.
【００２５】具体的には、Ａｇ、又はＡｇ−Ｐｄの導体
粉末、ガラスフリット、有機ビヒクルからなる導電性ペ
ーストを、積層体の端部に転写、印刷などによって塗布
する。Specifically, a conductive paste composed of Ag or Ag-Pd conductor powder, glass frit, and organic vehicle is applied to the end of the laminate by transfer, printing, or the like.
【００２６】その後、脱バインダーを行った後、５５０
〜９００℃で焼きつけを行う。これにより、厚み５０〜
１５０μｍの端子電極の下地層３１ａ、３１ｂが形成さ
れる。After debinding, 550
Bake at ~ 900 ° C. With this, a thickness of 50 to
Underlayers 31a and 31b of the terminal electrode having a thickness of 150 μm are formed.
【００２７】さらに、下地層３１ａ、３１ｂ上に、電解
メッキ法によって、Ｎｉメッキ層３２ａ、３２ｂ、Ｓｎ
メッキ層３３ａ、３３ｂを形成する。尚、両メッキ層３
２ａ、３２ｂ、３３ａ、３３ｂの厚みは、３〜１５μｍ
となる。Further, Ni plating layers 32a, 32b, Sn are formed on the base layers 31a, 31b by electrolytic plating.
The plated layers 33a and 33b are formed. Both plating layers 3
The thickness of 2a, 32b, 33a, 33b is 3 to 15 μm.
Becomes
【００２８】その後、耐熱衝撃試験など各種試験を行
い、特性検査を行い、積層セラミックコンデンサ１０が
完成する。After that, various tests such as a thermal shock test and a characteristic test are conducted to complete the monolithic ceramic capacitor 10.
【００２９】特性検査の１つである本発明の耐熱試験法
は、図１に示すように、４００〜５００℃に加熱された
ホットプレート１１を用いて行われる。The heat resistance test method of the present invention, which is one of the characteristic tests, is carried out using a hot plate 11 heated to 400 to 500 ° C., as shown in FIG.
【００３０】具体的には、ホットプレート１１を、ヒー
タなどの手段で４００〜５００℃に加熱する。具体的に
は、ホットプレート１１をセラミック基板で構成し、こ
のセラミック基板内にシーズヒータを埋設されている。Specifically, the hot plate 11 is heated to 400 to 500 ° C. by a means such as a heater. Specifically, the hot plate 11 is made of a ceramic substrate, and a sheath heater is embedded in the ceramic substrate.
【００３１】次に、１ロットで製造された積層セラミッ
クコンデンサ１０を、例えば１／１０００の割合で抜き
取り、ホットプレート１１上に互いに重ならないように
積層セラミックコンデンサ１０を載置し、約５秒間放置
した後に、外観検査及び静電容量を検査する。Next, the monolithic ceramic capacitors 10 manufactured in one lot are extracted at a ratio of 1/1000, for example, and the monolithic ceramic capacitors 10 are placed on the hot plate 11 so as not to overlap each other, and left for about 5 seconds. After that, the appearance and the capacitance are inspected.
【００３２】この時、４００〜５００℃の熱によって、
端子電極３ａ、３ｂが含浸されたメッキ溶液などの水分
が突騰して、端子電極の下地層３１ａ、３１ｂとＮｉメ
ッキ層３２ａ、３２ｂとの界面、また下地層３１ａ、３
１ｂと積層体との界面に亀裂や剥離などの外観の変化が
発生するものに関しては不良となる。また、外観上の変
化はなくとも、ホットプレートから離した後に、静電容
量を検査した結果、容量の異常低下（以下、容量不良と
記す）が発生する。このように、ホットプレート１１上
に、積層セラミックコンデンサ１０を載置するだけで、
激しく突騰したものにおいては、２０〜３０ｃｍも跳ね
上がり、ホットプレート１１の外部に弾け飛ぶものさえ
発生する。At this time, the heat of 400 to 500 ° C.
Moisture such as the plating solution impregnated in the terminal electrodes 3a and 3b jumps, and the interfaces between the base layers 31a and 31b of the terminal electrodes and the Ni plated layers 32a and 32b, and the base layers 31a and 3b.
Those having a change in appearance such as cracks or peeling at the interface between 1b and the laminate are defective. In addition, even if there is no change in appearance, as a result of inspecting the electrostatic capacity after separating from the hot plate, an abnormal decrease in capacity (hereinafter referred to as capacity failure) occurs. In this way, simply by placing the monolithic ceramic capacitor 10 on the hot plate 11,
In the case of a violent upheaval, it jumps up by 20 to 30 cm, and even a thing jumping out of the hot plate 11 is generated.
【００３３】このように、４００〜５００℃のホットプ
レート１１の載置による耐熱衝撃試験方法は、従来、２
８０℃の半田浴に浸漬していた耐熱衝撃試験方法に比べ
て、大変厳しいものとなる。As described above, the thermal shock test method by placing the hot plate 11 at 400 to 500 ° C.
Compared to the thermal shock test method in which it was immersed in a solder bath at 80 ° C, it becomes much more severe.
【００３４】従って、従来のように回路基板の配線パッ
ドに積層セラミックコンデンサ１０を載置して、半田ゴ
テを用いて半田接合するコテ付け法で発生していた端子
電極３ａ、３ｂの破損や容量不良が起こらず、信頼性の
高い半田接合が達成できる。Therefore, the damage or capacitance of the terminal electrodes 3a and 3b, which has been caused by the conventional soldering method of placing the laminated ceramic capacitor 10 on the wiring pad of the circuit board and solder-joining with the soldering iron as in the prior art. Defects do not occur, and highly reliable solder bonding can be achieved.
【００３５】本発明者は、従来の約２８０℃の半田浴に
浸漬した耐熱試験法による良否判定と、本発明による耐
熱試験による良否判定を比較した。その結果を表１に記
載する。The inventor of the present invention compared the quality judgment by the conventional heat resistance test method immersed in a solder bath at about 280 ° C. with the quality judgment by the heat resistance test according to the present invention. The results are shown in Table 1.
【００３６】[0036]
【表１】 [Table 1]
【００３７】試料に用いた積層セラミックコンデンサ１
０は、端子電極３ａ、３ｂの形成幅（Ｄｉｐ幅）を２種
類（０．６ｍｍ、０．３ｍｍ）、端子電極３ａ、３ｂの
下地層３１ａ、３１ｂの導電性ペーストを３種類（全ペ
ースト中のＡｇ粉末とガラスフリットとの固形成分の重
量比率が、７０．０％、７０．８％、７１．９％）、さ
らに下地層３１ａ、３１ｂの焼きつけ温度を４種類（５
６０℃、６００℃、６４０℃、６８０℃）の夫々の組み
合わせ、２４種類の積層セラミックコンデンサ１０につ
いて調べた。 夫々の積層セラミックコンデンサ１０を
同一製造ロットで２００個形成し、各々の試験方法に１
００個づつ用いた。Multilayer ceramic capacitor 1 used as a sample
0 is two kinds of forming widths (Dip widths) of the terminal electrodes 3a and 3b (0.6 mm and 0.3 mm), and three kinds of conductive pastes of the base layers 31a and 31b of the terminal electrodes 3a and 3b (of all the pastes). Of Ag powder and glass frit are 70.0%, 70.8%, 71.9%), and four different baking temperatures of the underlayers 31a, 31b (5).
Each combination of 60 ° C., 600 ° C., 640 ° C. and 680 ° C.) and 24 types of laminated ceramic capacitors 10 were examined. 200 of each monolithic ceramic capacitor 10 are formed in the same manufacturing lot, and 1 is applied to each test method.
00 pieces were used.
【００３８】尚、Ｎｉメッキ層３２ａ、３２ｂは、通電
条件１０００Ａ・ｍｉｎ、Ｓｎメッキ層３３ａ、３３ｂ
は、通電条件９００Ａ・ｍｉｎで一定とした。The Ni plating layers 32a and 32b are the energization conditions of 1000 A.min and the Sn plating layers 33a and 33b.
Was constant under energization conditions of 900 A · min.
【００３９】試験方法の比較の結果、従来のように、約
２８０℃の半田浴に浸漬した後の静電容量チェックおい
て、Ｄｉｐ幅が０．３ｍｍ、ペーストの固形成分が７
０．８％、焼き付け温度が５６０℃の積層セラミックコ
ンデンサ１０で、また、Ｄｉｐ幅が０．３ｍｍ、ペース
トの固形成分が７１．９％、焼き付け温度が５６０℃の
積層セラミックコンデンサ１０で、夫々１個の容量不良
が発生した。As a result of the comparison of the test methods, the Dip width was 0.3 mm and the solid component of the paste was 7 in the conventional capacitance check after immersion in a solder bath at about 280 ° C.
The multilayer ceramic capacitor 10 has a 0.8% baking temperature of 560 ° C., and a dip width of 0.3 mm, a solid component of the paste of 71.9%, and a baking temperature of 560 ° C. A defective capacity has occurred.
【００４０】これに対して、本発明の試験方法では、Ｄ
ｉｐ幅が０．３ｍｍ、ペーストの固形成分が７０．０
％、焼き付け温度が５６０℃の積層セラミックコンデン
サ１０で４個の、Ｄｉｐ幅が０．３ｍｍ、ペーストの固
形成分が７０．８％、焼き付け温度が５６０℃の積層セ
ラミックコンデンサ１０で６個の、またＤｉｐ幅が０．
３ｍｍ、ペーストの固形成分が７１．９％、焼き付け温
度が５６０℃の積層セラミックコンデンサ１０で５個の
容量不良が発生した。On the other hand, in the test method of the present invention, D
ip width 0.3mm, solid component of paste 70.0
%, 4 in the monolithic ceramic capacitor 10 having a baking temperature of 560 ° C., a Dip width of 0.3 mm, a solid component of the paste of 70.8%, and 6 in the monolithic ceramic capacitor 10 having a baking temperature of 560 ° C. The Dip width is 0.
In the multilayer ceramic capacitor 10 having a thickness of 3 mm, a solid content of the paste of 71.9%, and a baking temperature of 560 ° C., five defective capacitors occurred.
【００４１】以上の比較から、Ｄｉｐ幅が０．３ｍｍ、
ペーストの固形成分が７０．０％、焼き付け温度が５６
０℃の積層セラミックコンデンサ１０で全数良品に対し
て、本発明の試験方法では４個の容量不良が検出でき
た。また、同７０．８％、同７１．９％の積層セラミッ
クコンデンサ１０で１個の不良に対して、６個、５個の
容量不良を新たに検出できた。From the above comparison, the Dip width is 0.3 mm,
The solid component of the paste is 70.0%, the baking temperature is 56
With respect to all non-defective products in the laminated ceramic capacitor 10 at 0 ° C., four defective capacitors could be detected by the test method of the present invention. Further, with respect to one defect in the laminated ceramic capacitors 10 of 70.8% and 71.9%, 6 and 5 defective capacitors were newly detected.
【００４２】即ち、Ｄｉｐ幅が０．３ｍｍと比較的に小
さく、端子電極３ａ、３ｂの下地層３１ａ、３１ｂの焼
き付け温度が比較的に低い場合に、下地層３１ａ、３１
ｂが緻密化されず、微小な空孔が発生して、この空孔内
にメッキ溶液などの水分が含浸しやすく状態となり、半
田ごてなどによって端子電極３ａ、３ｂに直接４００℃
前後の熱が印加されると、容量不良が発生してしまうと
考えられる。That is, when the Dip width is comparatively small at 0.3 mm and the baking temperature of the underlayers 31a and 31b of the terminal electrodes 3a and 3b is relatively low, the underlayers 31a and 31b.
b is not densified and minute pores are generated, and it becomes easy for water such as plating solution to be impregnated in the pores.
It is considered that when the heat before and after is applied, the capacity defect occurs.
【００４３】したがって、従来の試験では良品と判断さ
れたものであって、本発明の試験方法で不良のもの、例
えば、表１のＤｉｐ幅が０．３ｍｍ、ペーストの固形成
分が７０．０％、焼き付け温度が５６０℃の積層セラミ
ックコンデンサ１０などが、回路基板の配線パターンに
半田ごてにより半田接合された場合には、回路動作上に
致命的な欠陥をもたらすものとなる。Therefore, it was judged as a non-defective product in the conventional test, and was defective by the test method of the present invention, for example, the Dip width in Table 1 was 0.3 mm, and the solid component of the paste was 70.0%. When the laminated ceramic capacitor 10 having a baking temperature of 560 ° C. is soldered to the wiring pattern of the circuit board with a soldering iron, it causes a fatal defect in the circuit operation.
【００４４】また、本試験方法では、従来は良品と判断
された積層セラミックコンデンサ１０を、半田こてによ
る半田接合によって生じる容量不良などを予め検出でき
るという作用・効果の他に、積層セラミックコンデンサ
１０を単にホットプレート１１に載置、放置するという
ことから、試験後の外観チェックが極めて容易に行える
という作用・効果を有する。即ち、従来の試験方法であ
った２８０℃の半田浴に浸漬すると、端子電極３ａ、３
ｂの表面に半田が付着するので、細かな剥離や亀裂など
を目視によって発見することができないのである。In addition, in the present test method, in addition to the function and effect of previously detecting a non-defective monolithic ceramic capacitor 10 such as a capacity defect caused by solder joining with a soldering iron, the monolithic ceramic capacitor 10 is also available. Since it is simply placed on the hot plate 11 and left to stand, there is an effect that the appearance check after the test can be performed very easily. That is, when immersed in a solder bath at 280 ° C., which is a conventional test method, the terminal electrodes 3a, 3
Since the solder adheres to the surface of b, it is impossible to visually detect fine peeling or cracks.
【００４５】上述の試験方法では、積層セラミックコン
デンサを用いて説明したが、端子電極として厚膜下地
層、メッキ被覆層を形成した電子部品、例えばチップ型
抵抗器、積層バリスタなど種々の電子部品にも広く適用
できる。In the above-described test method, the multilayer ceramic capacitor is used for explanation, but various electronic components such as a chip type resistor and a multilayer varistor having a thick film underlayer and a plating layer as terminal electrodes are used. Is also widely applicable.
【００４６】[0046]
【発明の効果】以上のように、本発明の耐熱衝撃試験方
法によれば、積層セラミックコンデンサを半田ごてによ
る半田接合による端子電極の破損による容量不良などに
対して、極めて有効な試験方法となり、また、試験方法
後の外観チェックが容易となり、さらに、設備なども安
価で、確実な試験方法となる。As described above, according to the thermal shock test method of the present invention, it is an extremely effective test method for the capacity failure due to the damage of the terminal electrode due to the solder joining of the laminated ceramic capacitor by the soldering iron. Moreover, the appearance check after the test method becomes easy, and the equipment is inexpensive and the test method is reliable.
【図１】本発明の耐熱衝撃試験方法の実施状態の概略図
である。FIG. 1 is a schematic view of an implementation state of a thermal shock test method of the present invention.
【図２】典型的の積層セラミックコンデンサの端面構造
図である。FIG. 2 is an end face structure diagram of a typical monolithic ceramic capacitor.
【図３】積層セラミックコンデンサの製造工程を示すフ
ロー図である。FIG. 3 is a flowchart showing a manufacturing process of a monolithic ceramic capacitor.
１０・・・・・積層セラミックコンデンサ １・・・・・・・誘電体セラミック層 ２ａ、２ｂ・・・内部電極 ３ａ、３ｂ・・・端子電極 ３１ａ、３１ｂ・・・下地層 ３２ａ、３２ｂ・・・Ｎｉメッキ層 ３３ａ、３３ｂ・・・Ｓｎメッキ層 １１・・・・・・ホットプレート 10 ... Multilayer ceramic capacitor 1 ... Dielectric ceramic layer 2a, 2b ... Internal electrode 3a, 3b ... Terminal electrode 31a, 31b ... Underlayer 32a, 32b ...・ Ni plating layer 33a, 33b ... Sn plating layer 11 ... Hot plate
Claims (1)
電性厚膜下地層、表面メッキ層からなる端子電極を形成
したチップ型電子部品の耐熱衝撃試験方法であって、 前記チップ型電子部品を、４００〜５００℃で加熱した
ホットプレートに載置した後、耐熱衝撃検査を行うこと
を特徴するチップ型電子部品の耐熱衝撃試験方法。1. A thermal shock test method for a chip type electronic component, wherein a terminal electrode composed of a conductive thick film underlayer and a surface plating layer is formed at an end of a single plate or a laminated ceramic body. A thermal shock test method for a chip-type electronic component, wherein the thermal shock test is performed after the component is placed on a hot plate heated at 400 to 500 ° C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17306692A JPH0618392A (en) | 1992-06-30 | 1992-06-30 | Method for testing thermal shock resistance of chip-type electronic part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17306692A JPH0618392A (en) | 1992-06-30 | 1992-06-30 | Method for testing thermal shock resistance of chip-type electronic part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0618392A true JPH0618392A (en) | 1994-01-25 |
Family
ID=15953581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17306692A Pending JPH0618392A (en) | 1992-06-30 | 1992-06-30 | Method for testing thermal shock resistance of chip-type electronic part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0618392A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9018060B2 (en) | 2010-06-15 | 2015-04-28 | 3M Innovative Properties Company | Variable capacitance sensors and methods of making the same |
-
1992
- 1992-06-30 JP JP17306692A patent/JPH0618392A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9018060B2 (en) | 2010-06-15 | 2015-04-28 | 3M Innovative Properties Company | Variable capacitance sensors and methods of making the same |
| EP2583090B1 (en) * | 2010-06-15 | 2016-04-06 | 3M Innovative Properties Company | Variable capacitance sensors and methods of making the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100277382B1 (en) | Multilayer electronic components | |
| US6577486B1 (en) | Stacked-type electronic device having film electrode for breaking abnormal current | |
| US10964478B2 (en) | Multilayer ceramic electronic component including organic layers having different coverage rates and mount structure therefor | |
| JPH0341710A (en) | Laminated ceramic capacitor | |
| JPH09180957A (en) | Multilayered ceramic capacitor | |
| JPH03250603A (en) | Thermistor | |
| JP2000100653A (en) | Chip-type stacked electronic component | |
| US7199590B2 (en) | Screening method for laminated ceramic capacitors | |
| JPH0618392A (en) | Method for testing thermal shock resistance of chip-type electronic part | |
| JPH11354370A (en) | Layered ceramic electronic parts | |
| CN210182176U (en) | Sn-Ni-Ag composite electrode thermistor chip | |
| JPH0729773A (en) | Terminal electrode forming method of chip type electronic part | |
| JPH04154104A (en) | Laminated ceramic capacitor | |
| JPH0595071U (en) | Thick film circuit board | |
| JP4757695B2 (en) | Chip-type electronic component for inspection and mounting state inspection method | |
| JPH05243074A (en) | Chip-like electronic parts and method for forming terminal electrode thereof | |
| JPH09307205A (en) | Low-temperature-burned ceramic board | |
| JP2816742B2 (en) | Circuit board | |
| JPH04329616A (en) | Laminated type electronic component | |
| JPH08111349A (en) | Chip component | |
| JPH09120932A (en) | Laminated electronic component | |
| JPH08203773A (en) | Manufacture of chip-type multilayer ceramic capacitor | |
| JPH08288173A (en) | Ceramic electronic component | |
| JP2931910B2 (en) | Circuit board | |
| JP3498833B2 (en) | Manufacturing method of ceramic electronic components |