JPH06181315A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06181315A JPH06181315A JP43A JP33310092A JPH06181315A JP H06181315 A JPH06181315 A JP H06181315A JP 43 A JP43 A JP 43A JP 33310092 A JP33310092 A JP 33310092A JP H06181315 A JPH06181315 A JP H06181315A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- resistance
- region
- electrode
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 238000001771 vacuum deposition Methods 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0886—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、オン抵抗が低い特性を
有する半導体素子、特に縦型ＭＯＳＦＥＴの改良に関す
るもので、パワー用に適する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a semiconductor device having a characteristic of low on-resistance, especially a vertical MOSFET, and is suitable for power.
【０００２】[0002]
【従来の技術】図２は、Ｎチャネル縦型パワーＭＯＳＦ
ＥＴの一例の略断面図である。2. Description of the Related Art FIG. 2 shows an N-channel vertical power MOSF.
It is a schematic sectional drawing of an example of ET.
【０００３】第１の導電型たとえばＮ型の低比抵抗シリ
コン単結晶であるドレイン基板１上にエピタキシャル成
長されたＮ型の高比抵抗ドレイン領域２が形成されてお
り、このドレイン領域２にチャネルを形成する第２の導
電型、たとえばＰ型のウェル領域３が多数設けられ、さ
らにこのウェル領域３にはそれぞれＮ型の低抵抗のソー
ス領域４が形成されている。ここで各ウェル領域３は、
所定間隔おきに配置されソース領域４およびウェル領域
３に対するソース電極７のコンタクトホール部分を除
き、シリコン酸化膜６が表面に被覆されていて、このシ
リコン酸化膜６上には隣接するウェル領域３相互にわた
ってポリシリコンのゲート電極５が配置されている。そ
してこのゲート電極５はＰＳＧ（リンガラス）等の層間
絶縁膜８で覆われている。An N type high specific resistance drain region 2 epitaxially grown is formed on a drain substrate 1 which is a first conductivity type, for example, N type low specific resistance silicon single crystal, and a channel is formed in this drain region 2. A large number of well regions 3 of the second conductivity type, for example, P type, to be formed are provided, and each well region 3 is formed with an N type low resistance source region 4. Here, each well region 3 is
Except for the contact hole portion of the source electrode 7 for the source region 4 and the well region 3, which are arranged at a predetermined interval, the surface thereof is covered with a silicon oxide film 6, and on the silicon oxide film 6, adjacent well regions 3 are separated from each other. A gate electrode 5 made of polysilicon is arranged over the entire area. The gate electrode 5 is covered with an interlayer insulating film 8 such as PSG (phosphorus glass).
【０００４】なお、ソース電極７はこの層間絶縁膜８を
覆う形でこれらの上にスパッタリング蒸着等により形成
され、ソース領域４とウェル領域３とにコンタクトして
いる。The source electrode 7 is formed on the interlayer insulating film 8 by sputtering deposition or the like so as to cover the interlayer insulating film 8 and is in contact with the source region 4 and the well region 3.
【０００５】また、ドレイン基板１の裏面側には金属製
のドレイン電極９が真空蒸着等の技術により形成され、
ドレイン基板１を覆っている。A drain electrode 9 made of metal is formed on the back surface of the drain substrate 1 by a technique such as vacuum deposition.
It covers the drain substrate 1.
【０００６】ゲート電極５に所定の電圧を印加すると、
ゲート電極５の下部に位置するウェル領域３の部分にチ
ャネル層が形成され、ソース電極７に対してドレイン電
極９に電圧をかけると、電流がドレイン電極９からドレ
イン基板１およびドレイン領域２を通りチャネル領域１
０を経てソース領域４，ソース電極８へと流れる。When a predetermined voltage is applied to the gate electrode 5,
A channel layer is formed in a portion of the well region 3 located below the gate electrode 5, and when a voltage is applied to the drain electrode 9 with respect to the source electrode 7, a current flows from the drain electrode 9 through the drain substrate 1 and the drain region 2. Channel region 1
It flows to the source region 4 and the source electrode 8 via 0.
【０００７】このような構成の縦型ＭＯＳＦＥＴは、同
一表面上にソース電極，ドレイン電極が配列される横型
ＭＯＳＦＥＴに比べて、電流の取出し面積が広くとれる
ため、大電流素子として最適である。The vertical MOSFET having such a structure is suitable as a large-current element because it has a larger current extraction area than a lateral MOSFET in which a source electrode and a drain electrode are arranged on the same surface.
【０００８】[0008]
【発明が解決しようとする課題】前述の縦型パワーＭＯ
ＳＦＥＴにあっては、図２のウェル領域３に挟まれた高
比抵抗のドレイン領域２を電流が流れるため、ソースド
レイン間の導通時における抵抗値（オン抵抗）を下げる
には限界がある。すなわち高比抵抗のドレイン領域２の
比抵抗を下げると、ウェル領域３との接合部に大きな電
界がかかり、ソース・ドレイン間の耐圧が低下してしま
うことになる。The above-mentioned vertical power MO
In the SFET, a current flows through the drain region 2 having a high specific resistance sandwiched between the well regions 3 in FIG. 2, so that there is a limit to lowering the resistance value (ON resistance) during conduction between the source and the drain. That is, if the specific resistance of the drain region 2 having a high specific resistance is lowered, a large electric field is applied to the junction with the well region 3 and the breakdown voltage between the source and drain is lowered.
【０００９】そのため、このドレイン領域２の比抵抗を
ある程度までしか低くできないという欠点がある。Therefore, there is a drawback that the specific resistance of the drain region 2 can be lowered only to some extent.
【００１０】また、オン抵抗を下げるために単位セル数
を増大させることは、チップ面積の増大につながりコス
ト増、実装上の問題などが生じてくる。Further, increasing the number of unit cells in order to reduce the on-resistance leads to an increase in chip area, which leads to an increase in cost and problems in mounting.
【００１１】オン抵抗は、前述のウェル領域３，３に挟
まれたドレイン領域２とチャネル領域１０を電流が流れ
るときの抵抗成分とドレイン基板１の抵抗成分と、コン
タクト抵抗（ソースコンタクトとドレインコンタクト）
成分に大別される。しかし、上述した理由により半導体
基板内部のオン抵抗には限界がある。The on-resistance is the resistance component when a current flows through the drain region 2 and the channel region 10 sandwiched between the well regions 3 and 3 and the resistance component of the drain substrate 1, and the contact resistance (source contact and drain contact). )
The ingredients are roughly classified. However, there is a limit to the on-resistance inside the semiconductor substrate for the reasons described above.
【００１２】本発明の目的は、ドレイン電極を設ける部
分の抵抗を低減し、トータルとしてのオン抵抗を低減さ
せることにある。An object of the present invention is to reduce the resistance of the portion where the drain electrode is provided and to reduce the total on-resistance.
【００１３】[0013]
【課題を解決するための手段】本発明においては、ドレ
イン電極を形成する面に多数の凹凸を設け、さらにこの
凹凸部全面にわたりその部分と同じ導電型の不純物をイ
オン注入するようにした。In the present invention, a large number of irregularities are provided on the surface on which the drain electrode is formed, and the entire surface of the irregularities is ion-implanted with an impurity of the same conductivity type as that portion.
【００１４】[0014]
【作用】本発明によれば、ドレイン電極を形成する部分
の面に多数の凹凸を設けるから、ドレイン電極部のコン
タクト面積が大きくなりコンタクト抵抗をより小さくす
ることができ、またこの部分に同じ導電型の不純物を注
入することで、裏面の不純物濃度が高くなりコンタクト
抵抗をより小さくすることができる。According to the present invention, since a large number of irregularities are formed on the surface of the portion where the drain electrode is formed, the contact area of the drain electrode portion can be increased and the contact resistance can be further reduced. By implanting the type impurities, the impurity concentration on the back surface is increased and the contact resistance can be further reduced.
【００１５】[0015]
【実施例】図１は、本発明の一実施例であるＮチャネル
縦型パワー用ＭＯＳＦＥＴの略断面図である。1 is a schematic sectional view of an N-channel vertical power MOSFET according to an embodiment of the present invention.
【００１６】このＭＯＳＦＥＴは以下のようにして作成
される。まず、たとえばＮ型の単結晶シリコンである低
比抵抗ドレイン基板（通常比抵抗０．０１Ωcm程度、ウ
ェーハ厚さ５２５μm 程度）１上に通常のエピタキシャ
ル成長により高比抵抗Ｎ型のドレイン領域２を所定の厚
さ（通常数μm 〜数十μm ）まで成長させる。次にゲー
ト酸化膜としてシリコン酸化膜６を熱酸化により５００
Å〜１０００Å程度に形成し、その上にポリシリコンを
ＬＰＣＶＤ（減圧気相成長装置）によって４０００Å〜
６０００Å程度形成する。This MOSFET is manufactured as follows. First, a predetermined high-resistivity N-type drain region 2 is formed on a low-resistivity drain substrate (usually having a specific resistance of about 0.01 Ωcm and a wafer thickness of about 525 μm) 1 made of N-type single crystal silicon by ordinary epitaxial growth. Grow to a thickness (usually several μm to several tens of μm). Next, the silicon oxide film 6 as a gate oxide film is thermally oxidized to 500
Å ~ 1000 Å formed, and polysilicon on it by LPCVD (Low Pressure Vapor Deposition Equipment) 4000 Å ~
Form about 6000Å.
【００１７】その後フォトレジストを用いたマスクによ
るドライエッチング（通常ＲＩＥ：Reactive Ion Etchi
ng）により、ゲート電極５となるポリシリコンと下地の
ゲート酸化膜６をパターニングする。そして、そのポリ
シリコンによるゲート電極５をマスクとして、Ｐ型のウ
ェル領域３とその表面にＮ型のソース領域４を、たとえ
ばボロン（Ｂ）および砒素（Ａｓ）のイオン注入により
形成する。次に層間絶縁膜８として、たとえばＰＳＧ
（リンガラス）をＣＶＤにより６０００Å〜１００００
Å程度形成し、１０００℃程度の熱処理により形状を滑
らかにした後、ソースコンタクトホールを形成するため
層間絶縁膜８をエッチングする。そしてソース電極７お
よびゲート配線のためＡｌ−Ｓｉをスパッタ蒸着により
形成し、４４０℃程度のＨ2 シンターにより、上面側の
通常のＭＯＳＦＥＴ部の形成は完了する。After that, dry etching (usually RIE: Reactive Ion Etchi) with a mask using a photoresist is performed.
ng), the polysilicon to be the gate electrode 5 and the underlying gate oxide film 6 are patterned. Then, using the gate electrode 5 made of polysilicon as a mask, a P-type well region 3 and an N-type source region 4 are formed on the surface thereof by ion implantation of, for example, boron (B) and arsenic (As). Next, as the interlayer insulating film 8, for example, PSG
(Phosphorus glass) by CVD from 6000Å to 10000
After forming about Å and smoothing the shape by heat treatment at about 1000 ° C., the interlayer insulating film 8 is etched to form a source contact hole. Then, Al-Si for the source electrode 7 and the gate wiring is formed by sputter deposition, and the normal MOSFET portion on the upper surface side is completed by H 2 sintering at about 440 ° C.
【００１８】その後、ＭＯＳＦＥＴを通る電流による熱
抵抗を下げるという実装上の問題のため、裏面の低抵抗
のドレイン基板１をウェハ厚さ２００μm 前後まで研摩
し、ＫＯＨなどの異方性エッチング液でドレイン基板１
裏面に多数の凹凸をつける。ただし、異方性エッチング
の際、表面のゲートソース側はレジストで覆い保護して
おく。この凹凸溝の大きさは、ドレイン電極に使用する
金属の種類，厚みや固着するフレームとの接着剤の種類
により、ある程度制限されるので一様には最適値を決定
できない。After that, because of the mounting problem of lowering the thermal resistance due to the current passing through the MOSFET, the low-resistance drain substrate 1 on the back surface was polished to a wafer thickness of about 200 μm and drained with an anisotropic etching solution such as KOH. Board 1
Make many irregularities on the back. However, during anisotropic etching, the gate source side of the surface is covered with a resist for protection. The size of the concave-convex groove is limited to some extent depending on the type of metal used for the drain electrode, the thickness, and the type of adhesive with the frame to be fixed, and therefore the optimum value cannot be uniformly determined.
【００１９】その後、凹凸を設けたドレイン基板１の面
に、ドレイン基板１と同じ導電型のたとえばリン（Ｐ）
を１×１０18ion/cm2 程度イオン注入で打込み、ドレイ
ン電極９となる電極金属を真空蒸着等により形成後、４
４０℃程度の熱処理を施し工程を完了する。After that, on the surface of the drain substrate 1 provided with irregularities, for example, phosphorus (P) having the same conductivity type as that of the drain substrate 1 is formed.
Is implanted by about 1 × 10 18 ion / cm 2 by ion implantation, and an electrode metal to be the drain electrode 9 is formed by vacuum deposition or the like, and then 4
Heat treatment at about 40 ° C. is performed to complete the process.
【００２０】なお、本実施例ではＮチャネル縦型パワー
ＭＯＳＦＥＴについて説明したが、本発明はＰチャネル
縦型パワーＭＯＳＦＥＴにも適用できることは明らかで
ある。またバイポーラ型ＭＯＳＦＥＴ（通称ＩＧＢＴ：
Insulated Gate Bipolar Mode Transistor）にも、ドレ
イン電極を設ける基板の極性が異なるだけであるから、
適用できる。Although the N-channel vertical power MOSFET has been described in this embodiment, it is obvious that the present invention can be applied to the P-channel vertical power MOSFET. In addition, a bipolar MOSFET (commonly called IGBT:
Insulated Gate Bipolar Mode Transistor), the polarity of the substrate on which the drain electrode is installed is different,
Applicable.
【００２１】[0021]
【発明の効果】以上のように、本発明によれば裏面の基
板に凹凸を付けることと、その凹凸を付けた部分の基板
に同じ導電型のイオンを注入することで、ドレイン電極
のコンタクト抵抗を低減することができ、全体としての
半導体素子のオン抵抗を低減させることになる。また、
これは他の電気特性等を劣化させることなく達成され
る。As described above, according to the present invention, the contact resistance of the drain electrode can be obtained by making the substrate on the back surface uneven and by implanting ions of the same conductivity type into the substrate in the uneven portion. Can be reduced, and the on-resistance of the semiconductor element as a whole can be reduced. Also,
This is achieved without degrading other electrical properties and the like.
【図１】本発明の一実施例の略断面図である。FIG. 1 is a schematic sectional view of an embodiment of the present invention.
【図２】従来の一例の略断面図である。FIG. 2 is a schematic sectional view of a conventional example.
１ ドレイン基板 ２ ドレイン領域 ３ ウェル領域 ４ ソース領域 ５ ゲート電極 ６ シリコン酸化膜 ７ ソース電極 ８ 層間絶縁膜 ９ ドレイン電極 １０ チャネル領域 1 Drain Substrate 2 Drain Region 3 Well Region 4 Source Region 5 Gate Electrode 6 Silicon Oxide Film 7 Source Electrode 8 Interlayer Insulation Film 9 Drain Electrode 10 Channel Region
Claims (2)
イン領域と、該半導体基板表面の一部に形成された第２
の導電型の不純物拡散領域よりなるウェル領域と、この
ウェル領域の表面の一部に形成された第１の導電型の不
純物拡散領域よりなるソース領域と、ソース・ドレイン
間の第２の導電型の表面領域をチャネル部としてこの上
に絶縁膜を介して形成されたゲート電極と、半導体基板
の表面に形成したソース電極と、裏面に形成したドレイ
ン電極とよりなり、ドレイン電極を形成する半導体基板
の面に複数の凹凸を設けたことを特徴とする半導体素
子。1. A drain region made of a semiconductor substrate of a first conductivity type and a second region formed on a part of the surface of the semiconductor substrate.
Region formed of a first conductivity type impurity diffusion region formed in a part of the surface of the well region, and a second conductivity type between the source and the drain. A semiconductor substrate including a gate electrode formed on the surface region of which is a channel portion via an insulating film, a source electrode formed on the front surface of the semiconductor substrate, and a drain electrode formed on the back surface to form the drain electrode. A semiconductor element having a plurality of irregularities on its surface.
設けた層と同じ導電型の不純物イオンを注入したことを
特徴とする請求項１記載の半導体素子。2. The semiconductor element according to claim 1, wherein impurity ions of the same conductivity type as that of the layer provided with the irregularities are implanted into the surface of the semiconductor substrate provided with the irregularities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP43A JPH06181315A (en) | 1992-12-14 | 1992-12-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP43A JPH06181315A (en) | 1992-12-14 | 1992-12-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06181315A true JPH06181315A (en) | 1994-06-28 |
Family
ID=18262283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP43A Pending JPH06181315A (en) | 1992-12-14 | 1992-12-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06181315A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009522802A (en) * | 2006-01-09 | 2009-06-11 | テクニオン リサーチ アンド ディベロップメント ファウンデーション リミティド | Transistor structure and manufacturing method thereof |
-
1992
- 1992-12-14 JP JP43A patent/JPH06181315A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009522802A (en) * | 2006-01-09 | 2009-06-11 | テクニオン リサーチ アンド ディベロップメント ファウンデーション リミティド | Transistor structure and manufacturing method thereof |
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