JPH06177381A - Matrix of thin film transistor and its manufacture - Google Patents
Matrix of thin film transistor and its manufactureInfo
- Publication number
- JPH06177381A JPH06177381A JP32351092A JP32351092A JPH06177381A JP H06177381 A JPH06177381 A JP H06177381A JP 32351092 A JP32351092 A JP 32351092A JP 32351092 A JP32351092 A JP 32351092A JP H06177381 A JPH06177381 A JP H06177381A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate
- substrate
- insulating film
- tft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- Liquid Crystal (AREA)
- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はアクティブマトリクス駆
動方式による液晶パネル等に構成される薄膜トランジス
タ(TFT) マトリクスおよびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) matrix formed in a liquid crystal panel or the like by an active matrix driving method and a manufacturing method thereof.
【０００２】上記のTFT マトリクスにおいては，静電気
による表示不良や表示画素欠陥を低減できるような構造
が要求されている。In the above TFT matrix, a structure capable of reducing display defects and display pixel defects due to static electricity is required.
【０００３】[0003]
【従来の技術】アクティブマトリクス駆動方式による液
晶パネルはドット表示を行う個々の画素に対応してマト
リクス状にTFT を配置し，各画素にメモリ機能を持たせ
コントラスト良く多ラインの表示を可能としている。2. Description of the Related Art A liquid crystal panel based on an active matrix driving system has TFTs arranged in a matrix corresponding to individual pixels for dot display, and each pixel has a memory function to enable multi-line display with good contrast. .
【０００４】このような液晶パネルは, 例えばＸ，Ｙ方
向に交差してマトリクス状に配置された多数のゲートバ
スラインとドレインバスラインに駆動電圧を印加して，
両バスライン交差部に接続されたTFT を選択駆動するこ
とにより, 対応する所望の画素をドット表示するように
構成されている。このような従来のTFT マトリクスの構
造は, 例えば透明絶縁性のガラス基板上にチタン(Ti)−
アルミニウム(Al)からなる多数のゲートバスラインとド
レインバスラインとが窒化シリコン(SiN) 等からなる層
間絶縁膜を介してＸ，Ｙ方向に交差した形に配置され,
両バスラインの交差部にTFT が接続されている。In such a liquid crystal panel, for example, a driving voltage is applied to a large number of gate bus lines and drain bus lines arranged in a matrix so as to intersect in the X and Y directions,
By selectively driving the TFTs connected to the intersections of both bus lines, the corresponding desired pixels are displayed in dots. The structure of such a conventional TFT matrix is, for example, titanium (Ti) -on a transparent insulating glass substrate.
A large number of gate bus lines and drain bus lines made of aluminum (Al) are arranged so as to intersect in the X and Y directions via an interlayer insulating film made of silicon nitride (SiN) or the like.
A TFT is connected at the intersection of both bus lines.
【０００５】動作半導体層にアモルファスシリコン(a-S
i)層を用いる場合には，ゲート絶縁膜にプラズマ気相成
長(P-CVD) 法による窒化シリコン膜あるいは窒化シリコ
ンオキシナイトライド膜が用いられていた。Amorphous silicon (aS
When the i) layer is used, a silicon nitride film or a silicon oxynitride film formed by plasma vapor deposition (P-CVD) is used as the gate insulating film.
【０００６】この場合は, ゲート絶縁膜や動作半導体層
を同一真空槽内で連続的に成膜できるので製造工程は簡
単であるが, 下地の電極段差の被覆が十分でない。その
ためゲート絶縁膜にクラックが生じやすく, 十分な絶縁
耐圧あるいは絶縁抵抗を得ることは困難な場合が多かっ
た。In this case, since the gate insulating film and the operating semiconductor layer can be continuously formed in the same vacuum chamber, the manufacturing process is simple, but the underlying electrode step is not sufficiently covered. Therefore, cracks are likely to occur in the gate insulating film, and it is often difficult to obtain sufficient withstand voltage or insulation resistance.
【０００７】また，P-CVD 法の代わりに, アルコラート
を原料ガスとした原子層エピタキシ(ALEあるいはALD)法
によるアルミナまたは酸化タンタルのゲート絶縁膜を用
いたTFT の製造方法も知られている（特開平 1-179423
参照) 。Further, a method of manufacturing a TFT using a gate insulating film of alumina or tantalum oxide by an atomic layer epitaxy (ALE or ALD) method using an alcoholate as a source gas instead of the P-CVD method is also known ( Japanese Patent Laid-Open No. 1-179423
See).
【０００８】図４は従来例によるTFT の断面図である。
図において， 1は透明絶縁性基板, 2はゲート, 3は下
層ゲート絶縁膜でアルミナ膜, 4は上層ゲート絶縁膜で
窒化シリコン膜, 5は動作半導体層でa-Si膜,6は保護膜
で窒化シリコン膜, 7, 8はソース, ドレイン電極であ
る。FIG. 4 is a sectional view of a conventional TFT.
In the figure, 1 is a transparent insulating substrate, 2 is a gate, 3 is a lower gate insulating film and an alumina film, 4 is an upper gate insulating film and a silicon nitride film, 5 is an operating semiconductor layer and an a-Si film, and 6 is a protective film. Then, silicon nitride film, 7 and 8 are source and drain electrodes.
【０００９】この場合, 通常のプロセスでは，ゲート断
面は図示のようにテーパ状に形成され断面形状の上縁の
角度は90°以上である。In this case, in a normal process, the gate cross section is formed in a tapered shape as shown in the drawing, and the angle of the upper edge of the cross section is 90 ° or more.
【００１０】[0010]
【発明が解決しようとする課題】TFT マトリクスにおい
て, 補助容量（蓄積容量）を特に付加しないで液晶セル
の寄生容量の影響を避けるためには，電極の重なりしろ
を小さくすることにより良好な表示を得ている。このよ
うな構造では，ゲート絶縁膜の機械的強度が劣る下地段
差被覆部に上部電極端部が重なり，ゲート絶縁膜に応力
を受けやすく重なり部の機械的弱点部が絶縁破壊により
短絡する。In the TFT matrix, in order to avoid the influence of the parasitic capacitance of the liquid crystal cell without adding an auxiliary capacitance (storage capacitance), a good display can be obtained by reducing the overlap area of the electrodes. It has gained. In such a structure, the upper electrode end portion overlaps with the underlying step covering portion where the mechanical strength of the gate insulating film is inferior, and the gate insulating film is easily stressed, and the mechanical weak point of the overlapping portion is short-circuited due to dielectric breakdown.
【００１１】この結果，表示セルの動作不良による点画
素欠陥となるだけでなく，配線ライン間の信号の干渉に
より表示上致命的なライン欠陥を生ずる。また，短絡ま
でにいたらなくても，静電気等により動作半導体槽とゲ
ート絶縁膜の界面に高電圧がかかり，TFT の動作特性が
変化する。As a result, not only point pixel defects due to defective operation of the display cell but also line defects fatal to the display occur due to signal interference between wiring lines. Even if the short circuit does not occur, a high voltage is applied to the interface between the operating semiconductor tank and the gate insulating film due to static electricity, etc., and the operating characteristics of the TFT change.
【００１２】本発明はTFT の静電気による破壊や特性変
化を抑制し，表示不良をなくすることを目的とする。An object of the present invention is to prevent the TFT from being broken or the characteristics thereof to be changed due to static electricity to eliminate display defects.
【００１３】[0013]
【課題を解決するための手段】上記課題の解決は，１）
基板上に形成され且つ断面形状の上縁が鋭角であるゲー
トと，該基板上に該ゲートを覆って被着されたゲート絶
縁膜と，該ゲート上に該絶縁膜を介して形成された動作
半導体層と，該動作半導体層の両側にそれぞれ接続する
ソース電極とドレイン電極とを有する薄膜トランジスタ
マトリクス，あるいは２）請求項１記載の前記ゲートを
作製する際に，基板上に複数の金属膜を成膜し，それぞ
れの金属膜を異なるエッチャントによりエッチングして
形成する薄膜トランジスタマトリクスの製造方法により
達成される。[Means for Solving the Problems] 1)
A gate formed on a substrate and having an acute upper edge in cross section, a gate insulating film deposited on the substrate to cover the gate, and an operation formed on the gate via the insulating film 2. A thin film transistor matrix having a semiconductor layer and a source electrode and a drain electrode respectively connected to both sides of the operating semiconductor layer, or 2) when forming the gate according to claim 1, forming a plurality of metal films on a substrate. This is achieved by a method of manufacturing a thin film transistor matrix, which is formed by forming a film and etching each metal film with a different etchant.
【００１４】[0014]
【作用】図１は本発明の原理説明図である。図におい
て， 1は透明絶縁性基板, 2は逆テーパ状エッジ構造の
ゲート, 3は下層ゲート絶縁膜でアルミナ膜, 4は上層
ゲート絶縁膜で窒化シリコン膜, 5は動作半導体層でa-
Si膜, 6は保護膜で窒化シリコン膜, 7, 8はソース, ド
レイン電極である。FIG. 1 is a diagram for explaining the principle of the present invention. In the figure, 1 is a transparent insulating substrate, 2 is a gate having an inverse tapered edge structure, 3 is a lower gate insulating film and an alumina film, 4 is an upper gate insulating film and a silicon nitride film, and 5 is an operating semiconductor layer a-.
Si film, 6 is a protective film and a silicon nitride film, and 7, 8 are source and drain electrodes.
【００１５】本発明は以下の性質を利用している。 (A) 逆テーパ状エッジ構造のゲート電極上に被覆性が良
好で緻密なALD 法によりアルミナ膜を成膜し，ゲートの
逆テーパ先端部とソースまたはドレイン電極間の電界強
度が大きくなる。 (B) ALD アルミナ膜は電界強度が図３に示されるように
約 2 MV/cmからリーク電流が急激に増大する。The present invention utilizes the following properties. (A) An alumina film is formed on the gate electrode with an inverse taper edge structure by a dense ALD method with good coverage, and the electric field strength between the inverse taper tip of the gate and the source or drain electrode increases. (B) In the ALD alumina film, the electric field strength is about 2 MV / cm, as shown in Fig. 3, and the leakage current sharply increases.
【００１６】図３はゲート絶縁膜の耐圧特性を示す図で
ある。図において，窒化シリコン膜は或る電圧で急激に
ブレークダウンするが，ALDアルミナ膜は或る電圧を過
ぎると指数関数的に電流が増加するが矢印で示されるよ
うに電流−電圧特性は可逆性があり破壊しない。FIG. 3 is a diagram showing the withstand voltage characteristics of the gate insulating film. In the figure, the silicon nitride film breaks down rapidly at a certain voltage, while the ALD alumina film exponentially increases the current after a certain voltage, but the current-voltage characteristics are reversible as indicated by the arrow. There is no destruction.
【００１７】この結果, 静電気等による高電圧はこの電
流リークによりゲートのエッジ部でサージされてゲート
と動作半導体層間に高電圧がかからず，高電圧によるTF
T の特性変化や破壊が発生しない。As a result, the high voltage due to static electricity is surged at the edge of the gate due to this current leak, and the high voltage is not applied between the gate and the operating semiconductor layer.
No change in T characteristics or destruction.
【００１８】[0018]
【実施例】図２は本発明の実施例の断面図である。図に
おいて，透明絶縁性基板として例えばNA40ガラス基板 1
上に設けたゲート電極2A, 2Bおよびゲートバスライン上
に，ALD 法で形成したアルミナ膜 3とP-CVD 法で形成し
た窒化シリコン膜 4からなる２層構造のゲート絶縁膜を
形成する。以下にこの形成方法を詳細に述べる。FIG. 2 is a sectional view of an embodiment of the present invention. In the figure, a transparent insulating substrate such as NA40 glass substrate 1
On the gate electrodes 2A and 2B and the gate bus line provided above, a two-layer structure gate insulating film consisting of an alumina film 3 formed by the ALD method and a silicon nitride film 4 formed by the P-CVD method is formed. This forming method will be described in detail below.
【００１９】NA40ガラス基板 1上にスパッタリングによ
り厚さ1000ÅのAl膜 3と厚さ1000ÅのCr膜 4を連続して
成膜し，フォトリソグラフィによりレジスト膜をパター
ニングした後, レジスト膜をマスクにして硝酸第二セリ
ウムアンモン＋過塩素酸系のエッチャントでCr膜をエッ
チングする。次いで同じレジスト膜をマスクにして燐酸
を主成分とするエッチャントによりAl膜をエッチャント
する。この結果, くの字型断面を持つ逆テーパ状のゲー
トエッジ断面を形成できる。An Al film 3 having a thickness of 1000Å and a Cr film 4 having a thickness of 1000Å are continuously formed on the NA40 glass substrate 1 by sputtering, and the resist film is patterned by photolithography. Then, the resist film is used as a mask. Etch the Cr film with an etchant of ceric ammonium nitrate + perchloric acid. Then, using the same resist film as a mask, the Al film is etched by an etchant containing phosphoric acid as a main component. As a result, an inverse tapered gate edge cross section having a V-shaped cross section can be formed.
【００２０】次いで, レジスト膜を剥離し，ALD 装置に
基板を入れる。ALD 装置は, 例えば先に本発明者が特許
出願したものを用いる。この装置は扇状の反応管の中央
部にアルゴンバリアガスの出口が設けられ, この中心か
ら対称な左右の位置に一組づつ原料ガス出口と, 扇の要
の部分に排気用ターボ分子ポンプに接続する排気口が設
けられている。基板は扇形の左右を移動できる機構上に
載せられる。Next, the resist film is peeled off, and the substrate is put in the ALD device. As the ALD device, for example, the one previously applied for a patent by the present inventor is used. This device has an outlet for argon barrier gas at the center of a fan-shaped reaction tube.One set of raw material gas outlets is provided at symmetrical left and right positions from this center, and a turbo molecular pump for exhaust is connected to the main part of the fan. An exhaust port is provided for The substrate is mounted on a fan-shaped mechanism that can move left and right.
【００２１】まず, 薄膜形成領域の中央に置かれた基板
を 300℃に加熱し，ターボ分子ポンプにより反応管内を
5×10-7 Torr まで排気する。次いで，反応管内にArガ
スを500 SCCM 流し, ガス圧が0.01 Torr になるように
排気口のオリフィス弁を絞って調節する。First, the substrate placed in the center of the thin film formation region is heated to 300 ° C., and the inside of the reaction tube is moved by a turbo molecular pump.
Exhaust to 5 × 10 -7 Torr. Next, 500 SCCM of Ar gas is flown into the reaction tube, and the orifice valve at the exhaust port is throttled to adjust the gas pressure to 0.01 Torr.
【００２２】このようにして Ar の定常流を流してバリ
アを形成した後, バリアガスの片側に塩化アルミニウム
容器を 110℃に加熱し，塩化アルミニウム蒸気を発生
し，次いで, バリアガスの他の側に水蒸気を流す。この
場合, Arガスの定常流によって作られたバリアガス流に
より原料ガスの塩化アルミニウム蒸気と水蒸気は混合し
ない。この時の反応管内の圧力は0.01 Torr が維持され
ている。After forming a barrier by flowing a steady flow of Ar in this way, the aluminum chloride container is heated to 110 ° C. on one side of the barrier gas to generate aluminum chloride vapor, and then steam is generated on the other side of the barrier gas. Shed. In this case, the aluminum chloride vapor and the steam of the source gas are not mixed by the barrier gas flow created by the steady flow of Ar gas. At this time, the pressure inside the reaction tube was maintained at 0.01 Torr.
【００２３】このようにしてつくられたバリアガスの定
常流を乱さないような速度 (例えば往復 3秒の周期)
で, 移動機構上に載せられている基板を塩化アルミニウ
ム蒸気雰囲気と水蒸気雰囲気の間で移動させる。この往
復を3500回繰り返すことによって厚さ4000Åのアルミナ
多結晶薄膜 3を形成した。A velocity that does not disturb the steady flow of the barrier gas created in this way (for example, a three-round cycle)
Then, the substrate placed on the moving mechanism is moved between the aluminum chloride vapor atmosphere and the water vapor atmosphere. By repeating this reciprocation 3500 times, a 4000 Å-thick alumina polycrystalline thin film 3 was formed.
【００２４】次いで，P-CVD 法により, アルミナ多結晶
薄膜の上に厚さ 200Åの窒化シリコン多結晶薄膜 4を形
成した。以上で，窒化シリコン／アルミナ膜からなるゲ
ート絶縁膜を形成した。Then, a 200-Å-thick silicon nitride polycrystalline thin film 4 was formed on the alumina polycrystalline thin film by the P-CVD method. As described above, the gate insulating film made of the silicon nitride / alumina film was formed.
【００２５】この後，P-CVD 法等を用い, 動作半導体層
としてa-Si膜 5, 保護膜として窒化シリコン膜 6, コン
タクト層として n+ 型a-Si膜 9を形成し, ソース, ドレ
イン電極 7, 8,ドレインバスラインを形成し，TFT マト
リクスとした。After that, using an P-CVD method or the like, an a-Si film 5 as an operating semiconductor layer 5, a silicon nitride film 6 as a protective film 6, an n + type a-Si film 9 as a contact layer are formed, and a source and a drain are formed. Electrodes 7, 8 and drain bus lines were formed to form a TFT matrix.
【００２６】[0026]
【発明の効果】本発明によれば, ゲート絶縁膜の耐圧特
性を向上してTFT の静電気による破壊や特性変化を抑制
でき，表示不良を低減することができた。According to the present invention, the breakdown voltage characteristic of the gate insulating film can be improved to prevent the TFT from being damaged or changed due to static electricity, and display defects can be reduced.
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 本発明の実施例の断面図FIG. 2 is a sectional view of an embodiment of the present invention.
【図３】 ゲート絶縁膜の耐圧特性を示す図FIG. 3 is a diagram showing breakdown voltage characteristics of a gate insulating film.
【図４】 従来例によるTFT の断面図FIG. 4 Cross-sectional view of a conventional TFT
1 透明絶縁性基板 2 逆テーパ状エッジ構造のゲート 3 下層ゲート絶縁膜でアルミナ膜 4 上層ゲート絶縁膜でSiN 膜 5 動作半導体層でa-Si膜 6 保護膜でSiN 膜 7,8 ソース, ドレイン電極 1 Transparent insulating substrate 2 Gate with reverse tapered edge structure 3 Alumina film as lower gate insulating film 4 SiN film as upper gate insulating film 5 a-Si film as operating semiconductor layer 6 SiN film as protective film 7,8 Source, drain electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/318 Ｂ 7352−4Ｍ // Ｈ０１Ｌ 21/3205 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 21/318 B 7352-4M // H01L 21/3205
Claims (2)
鋭角であるゲートと，該基板上に該ゲートを覆って被着
されたゲート絶縁膜と，該ゲート上に該絶縁膜を介して
形成された動作半導体層と，該動作半導体層の両側にそ
れぞれ接続するソース電極とドレイン電極とを有するこ
とを特徴とする薄膜トランジスタマトリクス。1. A gate formed on a substrate and having an acute upper edge in cross section, a gate insulating film deposited on the substrate so as to cover the gate, and an insulating film provided on the gate via the insulating film. And a source electrode and a drain electrode connected to both sides of the operating semiconductor layer, respectively.
に，基板上に複数の金属膜を成膜し，それぞれの金属膜
を異なるエッチャントによりエッチングして形成するこ
とを特徴とする薄膜トランジスタマトリクスの製造方
法。2. A thin film transistor matrix, characterized in that, when forming the gate according to claim 1, a plurality of metal films are formed on a substrate and each metal film is etched by different etchants. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32351092A JPH06177381A (en) | 1992-12-03 | 1992-12-03 | Matrix of thin film transistor and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32351092A JPH06177381A (en) | 1992-12-03 | 1992-12-03 | Matrix of thin film transistor and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06177381A true JPH06177381A (en) | 1994-06-24 |
Family
ID=18155496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32351092A Withdrawn JPH06177381A (en) | 1992-12-03 | 1992-12-03 | Matrix of thin film transistor and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06177381A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH112843A (en) * | 1997-06-12 | 1999-01-06 | Hitachi Ltd | Liquid crystal display device and its manufacture |
| US6392721B1 (en) | 1998-10-02 | 2002-05-21 | Hitachi, Ltd. | Liquid crystal display device having wiring line including first and second layers with second layer having a thickness not greater than 1/2 of a thickness of first layer |
| KR100790416B1 (en) * | 2000-07-07 | 2008-01-02 | 에이에스엠 인터내쇼날 엔.브이. | Method for vapour deposition of a film onto a substrate |
| US7732325B2 (en) | 2002-01-26 | 2010-06-08 | Applied Materials, Inc. | Plasma-enhanced cyclic layer deposition process for barrier layers |
| US7781326B2 (en) | 2001-02-02 | 2010-08-24 | Applied Materials, Inc. | Formation of a tantalum-nitride layer |
| WO2011108050A1 (en) * | 2010-03-02 | 2011-09-09 | シャープ株式会社 | Thin film transistor substrate and process for production thereof |
| US10280509B2 (en) | 2001-07-16 | 2019-05-07 | Applied Materials, Inc. | Lid assembly for a processing system to facilitate sequential deposition techniques |
-
1992
- 1992-12-03 JP JP32351092A patent/JPH06177381A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH112843A (en) * | 1997-06-12 | 1999-01-06 | Hitachi Ltd | Liquid crystal display device and its manufacture |
| US6392721B1 (en) | 1998-10-02 | 2002-05-21 | Hitachi, Ltd. | Liquid crystal display device having wiring line including first and second layers with second layer having a thickness not greater than 1/2 of a thickness of first layer |
| KR100790416B1 (en) * | 2000-07-07 | 2008-01-02 | 에이에스엠 인터내쇼날 엔.브이. | Method for vapour deposition of a film onto a substrate |
| US7781326B2 (en) | 2001-02-02 | 2010-08-24 | Applied Materials, Inc. | Formation of a tantalum-nitride layer |
| US10280509B2 (en) | 2001-07-16 | 2019-05-07 | Applied Materials, Inc. | Lid assembly for a processing system to facilitate sequential deposition techniques |
| US7732325B2 (en) | 2002-01-26 | 2010-06-08 | Applied Materials, Inc. | Plasma-enhanced cyclic layer deposition process for barrier layers |
| WO2011108050A1 (en) * | 2010-03-02 | 2011-09-09 | シャープ株式会社 | Thin film transistor substrate and process for production thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000307 |