JPH06177178A - Structure of semiconductor chip - Google Patents

Structure of semiconductor chip

Info

Publication number
JPH06177178A
JPH06177178A JP43A JP34561892A JPH06177178A JP H06177178 A JPH06177178 A JP H06177178A JP 43 A JP43 A JP 43A JP 34561892 A JP34561892 A JP 34561892A JP H06177178 A JPH06177178 A JP H06177178A
Authority
JP
Japan
Prior art keywords
semiconductor chip
substrate
connection
solder
soldering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP43A
Other languages
Japanese (ja)
Inventor
Yasukazu Iwasaki
靖和 岩崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP43A priority Critical patent/JPH06177178A/en
Publication of JPH06177178A publication Critical patent/JPH06177178A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/26145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/83365—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To generate no cracks on the connection part between semiconductor chips and a substrate without increasing the cost and heat resistance even in the case of large-sized chips. CONSTITUTION:A projection part 12 is formed on the bottom of a semiconductor chip 11 by notching its peripheral part, and a connection strengthening space 13 to thicken soldering at the time of soldering is formed around said projection part 12. The base of this semiconductor chip 11 is connected to the land part 4 of a substrate 1 through a solder connection part 15. After said connection, the connection part between the semiconductor chip 11 and the substrate 1 becomes thick at its peripheral part due to a connection strengthening space 13 while suppressing a degree of shearing stress. On the other hand, the connection part between the semiconductor chip 11 and the substrate 1 becomes thin at its central part due to a projection part 12 so as to suppress the rise of heat resistance.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は、半導体チップの構造
の改良に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in the structure of semiconductor chips.

【０００２】[0002]

【従来の技術】従来、パワー素子あるいはＬＳＩなどの
半導体チップの基板への実装は、半田付けにより行われ
ている。このような従来の実装例としては、例えば図８
で示すものが知られている。これを説明すると、ガラス
エポキシや紙フェノールなどの素材からなる基板１の表
面に銅箔によりランド部４が形成され、このランド部４
上に、半田接続部３を介して半導体チップ２の平坦な底
部全体が固定接続されている。2. Description of the Related Art Conventionally, a semiconductor chip such as a power device or an LSI is mounted on a substrate by soldering. An example of such a conventional implementation is shown in FIG.
The ones shown in are known. To explain this, a land portion 4 is formed of copper foil on the surface of a substrate 1 made of a material such as glass epoxy or paper phenol.
The entire flat bottom portion of the semiconductor chip 2 is fixedly connected to the upper portion via the solder connection portion 3.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、このよ
うな従来の半導体チップ２と基板１との接続構造では、
半導体チップ２自体の発熱や雰囲気温度の変化などに起
因する温度サイクルによりストレスが発生し、そのスト
レスの繰り返しにより、図９で示すように半田接続部３
に半田亀裂５が発生する。この現象は、特に半導体チッ
プ２のサイズが大きくなると顕著である。この亀裂は、
半田接続部３の外周部から内部に向けて進行していき、
熱抵抗の増大、ひいては半導体チップの剥離を引き起こ
す原因となる。However, in such a conventional connection structure between the semiconductor chip 2 and the substrate 1,
Stress is generated by the temperature cycle caused by the heat generation of the semiconductor chip 2 itself, the change of the ambient temperature, and the like, and the repeated stress causes the solder connecting portion 3 to be exposed as shown in FIG.
A solder crack 5 is generated in the. This phenomenon is remarkable especially when the size of the semiconductor chip 2 increases. This crack is
From the outer periphery of the solder connection part 3 to the inside,
This causes an increase in thermal resistance and eventually peeling of the semiconductor chip.

【０００４】Ｅｎｇｅｌｍａｉｅｒ等による実験報告に
よれば、温度変化などのような低サイクルストレスによ
る半田の寿命は次式で与えられる。According to an experimental report by Engelmaier et al., The life of solder due to low cycle stress such as temperature change is given by the following equation.

【数１】 ここで、Ｎｆは半田の平均寿命であり、半田の剪断歪度
Δγは、 Δγ＝ΔＬ／２ｈ・・・・・・（２） ΔＬ＝Δα・ΔＴ・Ｌ・・・・（３） で表される。ただし、 ｈ ：半田の厚み Δα：半導体チップと基板の熱膨張係数差 ΔＴ：環境温度変化幅 Ｌ ：半導体チップサイズ ΔＬ：熱膨脹不整合[Equation 1] Here, Nf is the average life of the solder, and the shear strain degree Δγ of the solder is represented by Δγ = ΔL / 2h ... (2) ΔL = Δα · ΔT · L ... To be done. However, h: Solder thickness Δα: Thermal expansion coefficient difference between semiconductor chip and substrate ΔT: Environmental temperature change width L: Semiconductor chip size ΔL: Thermal expansion mismatch

【０００５】上記の式（１）、（２）、（３）から、次
のような方策をとれば半田の疲労寿命を長くできること
がわかる。 （Ａ）半導体チップのサイズを小さくする。 （Ｂ）基板の熱膨張係数を半導体チップに近ずける。 （Ｃ）半田の厚みを厚くする。 しかし、（Ａ）については、多くの機能要素が組み込ま
れてサイズがますます大きくなる状況の中で、現実的に
実現困難である。また、（Ｂ）の熱膨張係数の調整につ
いては、例えば基板にＳｉＣなどを用いれば、半導体チ
ップＳｉと熱膨張係数を近くすることができるが、コス
ト高となって実用的ではない。さらに、（Ｃ）の半田の
厚みの増大については、半田の表面張力と半導体チップ
の重量との関係からある限度以上に厚くすることができ
ない上に、半田を厚くし過ぎると熱抵抗が大きくなると
いう問題がある。そこで、本発明は、上記の問題点に鑑
み、コストと熱抵抗の上昇を招くことなく、半導体チッ
プのサイズの大きな場合でも、基板との間の接続部に亀
裂を生じさせない半導体チップの構造を提供することを
目的とする。From the above formulas (1), (2), and (3), it is understood that the fatigue life of solder can be extended by taking the following measures. (A) The size of the semiconductor chip is reduced. (B) The thermal expansion coefficient of the substrate is made closer to that of the semiconductor chip. (C) Increase the thickness of the solder. However, with regard to (A), it is practically difficult to realize in a situation where many functional elements are incorporated and the size becomes larger and larger. Regarding the adjustment of the coefficient of thermal expansion in (B), if the substrate is made of SiC or the like, the coefficient of thermal expansion can be made close to that of the semiconductor chip Si, but this is not practical because of high cost. Further, regarding the increase in the thickness of the solder in (C), it cannot be made thicker than a certain limit due to the relationship between the surface tension of the solder and the weight of the semiconductor chip, and if the solder is made too thick, the thermal resistance becomes large. There is a problem. Therefore, in view of the above problems, the present invention provides a structure of a semiconductor chip that does not cause a crack in a connection portion with a substrate even when the size of the semiconductor chip is large without causing an increase in cost and thermal resistance. The purpose is to provide.

【０００６】[0006]

【課題を解決するための手段】このため本発明は、半導
体チップの底面に、その周縁部を切欠して接続強化空間
を形成したことを特徴とする半導体チップの構造とし
た。For this reason, the present invention has a structure of a semiconductor chip characterized in that a connection strengthening space is formed by cutting out a peripheral portion of the bottom surface of the semiconductor chip.

【０００７】[0007]

【作用】このような構成の本発明にかかる半導体チップ
の底部は、基板の配線部に半田などの接着剤を介して接
続する。その接続後は、半導体チップと基板との接続部
は、周縁部では接続強化空間により厚くなり、剪断歪度
が小さく抑えられる。他方、半導体チップと基板との接
続部は、中心部では薄くなり熱抵抗の上昇が抑えられ
る。この部分では剪断歪は元来小さい。The bottom portion of the semiconductor chip according to the present invention having such a structure is connected to the wiring portion of the substrate through an adhesive such as solder. After the connection, the connection portion between the semiconductor chip and the substrate becomes thicker at the peripheral portion due to the connection strengthening space, and the shear strain degree can be suppressed to be small. On the other hand, the connecting portion between the semiconductor chip and the substrate is thin in the central portion, and the increase in thermal resistance is suppressed. The shear strain is originally small in this part.

【０００８】[0008]

【実施例】次に、本発明の第１実施例について、図１お
よび図２を参照して説明する。第１実施例は、Ｓｉなど
の素材からなる半導体チップ１１の底面に、その周縁部
を切欠して突出部１２を形成し、その突出部１２の周囲
に半田付け時に半田の厚さを厚くすべき接続強化空間１
３を形成する。半導体チップ１１の上部には、半導体プ
ロセスによって所定の回路１４を形成する。このような
半導体チップ１１は、半田のような接着剤を介して基板
１のランド部４に接続すると、半田接続部１５を介して
半導体チップ１１が基板１に固定実装される。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. In the first embodiment, a semiconductor chip 11 made of a material such as Si has a bottom surface on which a peripheral edge is cut out to form a protruding portion 12, and the solder is thickened around the protruding portion 12 during soldering. Power connection strengthening space 1
3 is formed. A predetermined circuit 14 is formed on the semiconductor chip 11 by a semiconductor process. When such a semiconductor chip 11 is connected to the land portion 4 of the substrate 1 via an adhesive such as solder, the semiconductor chip 11 is fixedly mounted on the substrate 1 via the solder connection portion 15.

【０００９】ここで、突出部１２は、図２で示すように
半導体チップ１１の底部全体より小さく、またその底面
の周縁部よりも内側に位置すればよく、半導体チップ１
１の外形とほぼ相似の形状とするのが好ましいが、その
形状は限定されない。また、半導体チップ１１と基板１
との接続に用いる接着剤は、上述の半田のみならずエポ
キシ樹脂剤などでもよい。Here, as shown in FIG. 2, the protrusion 12 may be smaller than the entire bottom of the semiconductor chip 11 and may be located inside the peripheral edge of the bottom surface of the semiconductor chip 11.
It is preferable that the shape is substantially similar to the outer shape of No. 1, but the shape is not limited. In addition, the semiconductor chip 11 and the substrate 1
The adhesive used for connection with the above may be not only the above-mentioned solder but also an epoxy resin agent or the like.

【００１０】次に、このように構成する第１実施例の製
造方法について、図３を参照して説明する。まずシリコ
ン基板２１の表面に、公知の半導体プロセスにより所定
の回路１４、およびダイシングライン２２を所定の位置
にそれぞれ形成する（図３の（Ａ）参照）。その結果、
ダイシングライン２２は各回路１４を囲むように縦横に
形成される。次に、シリコン基板２１の裏面には、ダイ
シングライン２２に対応する位置に所定幅の凹溝２３を
形成する（図３の（Ｂ）参照）。この凹溝２３の形成方
法としては、幅の広いダイシングソーによるハーフカッ
ト、ダイヤモンド砥石による研磨、フォトリソグラフィ
およびエッチングによる方法などが挙げられる。Next, the manufacturing method of the first embodiment thus constructed will be described with reference to FIG. First, the predetermined circuit 14 and the dicing line 22 are formed at predetermined positions on the surface of the silicon substrate 21 by a known semiconductor process (see FIG. 3A). as a result,
The dicing line 22 is formed vertically and horizontally so as to surround each circuit 14. Next, a concave groove 23 having a predetermined width is formed on the back surface of the silicon substrate 21 at a position corresponding to the dicing line 22 (see FIG. 3B). Examples of the method of forming the concave groove 23 include a method of half-cutting with a wide dicing saw, polishing with a diamond grindstone, photolithography and etching.

【００１１】次に、シリコン基板２１をダイシングライ
ン２２に沿ってダイシングソーにより分割すると、図３
の（Ｃ）に示すように、突出部１２の周囲に接続強化空
間１３が形成された半導体チップ１１が多数得られる。
引き続き、同図の（Ｄ）のように、この半導体チップ１
１の底部を基板１上のランド部４に半田付けにより接続
すると、半田接続部１５を介して両者は接続される。Next, when the silicon substrate 21 is divided along the dicing line 22 with a dicing saw, FIG.
As shown in (C), a large number of semiconductor chips 11 in which the connection strengthening spaces 13 are formed around the protrusions 12 are obtained.
Next, as shown in (D) of FIG.
When the bottom part of 1 is connected to the land part 4 on the substrate 1 by soldering, the two are connected via the solder connection part 15.

【００１２】第１実施例は以上のように構成するので、
最も剪断歪の大きな半導体チップ１１の接続底部の周縁
部は、接続強化空間１３により半田の厚みが相対的に厚
くなる。このため、前記の式（１）、（２）からわかる
ように、剪断歪度Δγが小さく押さえられ、半田接続部
は長寿命を保持できる。一方、剪断歪の比較的小さな半
導体チップ１１の接続底部の周縁部を除く部分は、突出
部１２により半田の厚さが従来並に薄いため、半導体チ
ップ全体としては熱抵抗の上昇を押さえることができ
る。Since the first embodiment is constructed as described above,
The peripheral portion of the connection bottom of the semiconductor chip 11 having the largest shear strain has a relatively thick solder due to the connection strengthening space 13. Therefore, as can be seen from the above equations (1) and (2), the shear strain Δγ is suppressed to a small value, and the solder connection portion can have a long life. On the other hand, since the solder is as thin as the conventional one due to the protrusions 12 in the portion except the peripheral portion of the connection bottom portion of the semiconductor chip 11 having a relatively small shear strain, it is possible to suppress an increase in thermal resistance of the entire semiconductor chip. it can.

【００１３】次に、本発明の第２実施例について、図４
および図５を参照して説明する。第２実施例の半導体チ
ップ３１は、図４で示すように、その底部の周縁部を内
側にテーパ状に切欠して逆四角錐台状の突出部３２を形
成し、その突出部３２の外周に接続強化空間３３を形成
する。この半導体チップ３１は、半田付けにより基板１
のランド部４に接続すると、半田接続部１５を介して基
板１に固定実装される。Next, the second embodiment of the present invention will be described with reference to FIG.
And it demonstrates with reference to FIG. As shown in FIG. 4, in the semiconductor chip 31 of the second embodiment, the peripheral edge of the bottom is tapered inward to form an inverted quadrangular pyramid-shaped protrusion 32, and the outer periphery of the protrusion 32 is formed. A connection strengthening space 33 is formed in the. This semiconductor chip 31 is soldered onto the substrate 1
When it is connected to the land portion 4 of the above, it is fixedly mounted on the substrate 1 via the solder connection portion 15.

【００１４】このような構成の第２実施例の製造方法に
ついて、図６を参照して説明すると、まず、シリコン基
板２１の表面に所定の回路１４、およびダイシングライ
ン２２をそれぞれ形成する（図６の（Ａ）参照）。その
結果、ダイシングライン２２は各回路１４を囲むように
縦横に形成される。次に、シリコン基板２１の裏面に
は、ダイシングライン２２に対応する位置に所定の大き
さのＶ溝３４を形成する（図６の（Ｂ）参照）。このＶ
溝３４の形成は、ヒドラジン、ＫＯＨで代表されるアル
カリ異方性エッチング液を用いて行う。The manufacturing method of the second embodiment having such a structure will be described with reference to FIG. 6. First, the predetermined circuit 14 and the dicing line 22 are formed on the surface of the silicon substrate 21 (FIG. 6). (A)). As a result, the dicing line 22 is formed vertically and horizontally so as to surround each circuit 14. Next, a V groove 34 having a predetermined size is formed on the back surface of the silicon substrate 21 at a position corresponding to the dicing line 22 (see FIG. 6B). This V
The groove 34 is formed using an alkali anisotropic etching solution represented by hydrazine and KOH.

【００１５】次に、シリコン基板２１をダイシングライ
ン２２に沿って分割すると、図６の（Ｃ）に示すよう
に、突出部３２の周囲に接続強化空間３３が形成された
半導体チップ３１が得られる。引き続き、この半導体チ
ップ３１は、半田接続部１５を介して基板１のランド部
４に固定実装する（図６の（Ｄ）参照）。Next, when the silicon substrate 21 is divided along the dicing line 22, as shown in FIG. 6C, the semiconductor chip 31 in which the connection strengthening space 33 is formed around the protrusion 32 is obtained. . Subsequently, the semiconductor chip 31 is fixedly mounted on the land portion 4 of the substrate 1 via the solder connection portion 15 (see FIG. 6D).

【００１６】次に、本発明の第３実施例について、図７
を参照して説明する。第３実施例は、パワーＩＣで代表
され、半導体チップの裏面に電極を形成する場合、また
は半田と半導体チップとのぬれ性を改善するために、半
導体チップの裏面に金属膜を形成する場合である。この
場合には、図７の（Ｄ）で示すように、半導体チップ５
１は、図１および図２で示した半導体チップ１１と同様
に、接続部の中央に突出部１２を設け、その突出部１２
の周囲には接続強化空間１３を形成する点で同じであ
る。しかし、上述のように、電極の形成またはぬれ性の
改善を図るために、半導体チップ５１の接続底部全体に
金属膜５２を形成する点が異なる。Next, a third embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. The third embodiment is typified by a power IC and is used in the case of forming electrodes on the back surface of a semiconductor chip, or in the case of forming a metal film on the back surface of a semiconductor chip in order to improve the wettability between solder and the semiconductor chip. is there. In this case, as shown in FIG.
1 is similar to the semiconductor chip 11 shown in FIG. 1 and FIG. 2, a protrusion 12 is provided in the center of the connecting portion, and the protrusion 12
It is the same in that a connection strengthening space 13 is formed around the. However, as described above, the difference is that the metal film 52 is formed over the entire connection bottom portion of the semiconductor chip 51 in order to form an electrode or improve wettability.

【００１７】このような構成の第３実施例の製造方法に
ついて、図７を参照して説明すると、まずシリコン基板
２１の表面に所定の回路１４、およびダイシングライン
２２をそれぞれ形成する（図７の（Ａ）参照）。次に、
シリコン基板２１の裏面には、ダイシングライン２２に
対応する位置に所定幅の凹溝２３を形成する（図７の
（Ｂ）参照）。さらに、シリコン基板２１の裏面全体に
は、蒸着やメッキなどにより金属膜５２を形成する（図
７の（Ｃ）参照）。次に、シリコン基板２１をダイシン
グライン２２に沿って分割すると、図７の（Ｄ）に示す
ように半導体チップ５１が得られる。引き続き、同図の
（Ｅ）のように、この半導体チップ５１は、半田接続部
１５を介して基板１のランド部４に固定実装する。The manufacturing method of the third embodiment having such a structure will be described with reference to FIG. 7. First, the predetermined circuit 14 and the dicing line 22 are formed on the surface of the silicon substrate 21 (see FIG. 7). (See (A)). next,
On the back surface of the silicon substrate 21, a groove 23 having a predetermined width is formed at a position corresponding to the dicing line 22 (see FIG. 7B). Further, a metal film 52 is formed on the entire back surface of the silicon substrate 21 by vapor deposition or plating (see FIG. 7C). Next, when the silicon substrate 21 is divided along the dicing line 22, the semiconductor chip 51 is obtained as shown in FIG. Subsequently, as shown in (E) of the figure, the semiconductor chip 51 is fixedly mounted on the land portion 4 of the substrate 1 via the solder connection portion 15.

【００１８】[0018]

【発明の効果】以上のように本発明では、半導体チップ
の底面に、その周縁部を切欠して接続強化空間を形成し
たから、特に高価な材料を基板に用いる必要がなくなっ
て制作費用を抑制でき、しかも熱抵抗の上昇を招くこと
がなく、大きなサイズの半導体チップを実装しても接続
材料の疲労によって寿命低下が生じないという効果が得
られる。As described above, according to the present invention, since the peripheral portion of the semiconductor chip is cut out to form the connection strengthening space on the bottom surface, it is not necessary to use a particularly expensive material for the substrate, and the production cost is suppressed. Further, it is possible to obtain an effect that the thermal resistance is not increased and even if a large-sized semiconductor chip is mounted, the life of the connecting material is not shortened due to fatigue of the connecting material.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the present invention.

【図２】その実施例の平面図である。FIG. 2 is a plan view of the embodiment.

【図３】その実施例の製造方法の一例を示す工程図であ
る。FIG. 3 is a process drawing showing an example of the manufacturing method of the embodiment.

【図４】本発明の第２実施例の断面図である。FIG. 4 is a sectional view of a second embodiment of the present invention.

【図５】その実施例の平面図である。FIG. 5 is a plan view of the embodiment.

【図６】その実施例の製造方法の一例を示す工程図であ
る。FIG. 6 is a process drawing showing an example of the manufacturing method of the embodiment.

【図７】本発明の第３実施例の製造方法の一例を示す工
程図である。FIG. 7 is a process drawing showing an example of the manufacturing method according to the third embodiment of the present invention.

【図８】従来例の断面図である。FIG. 8 is a sectional view of a conventional example.

【図９】従来例における半田疲労を示す説明図である。FIG. 9 is an explanatory diagram showing solder fatigue in a conventional example.

【符号の説明】[Explanation of symbols]

１ 基板 ４ ランド部 １１，３１，５１ 半導体チップ １２，３２ 突出部 １３，３３ 接続強化空間 １５ 半田接続部 ２１ シリコン基板 ２３ 凹溝 ５２ 金属膜 DESCRIPTION OF SYMBOLS 1 substrate 4 land part 11,31,51 semiconductor chip 12,32 protrusion part 13,33 connection strengthening space 15 solder connection part 21 silicon substrate 23 concave groove 52 metal film

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップ実装用基板上に形成した配
線部に、接着剤を介して底面を接続すべき半導体チップ
において、 前記半導体チップの底面に、その周縁部を切欠して接続
強化空間を形成したことを特徴とする半導体チップの構
造。1. A semiconductor chip whose bottom surface is to be connected to a wiring portion formed on a semiconductor chip mounting substrate via an adhesive, in which a peripheral edge portion is cut out to form a connection strengthening space on the bottom surface of the semiconductor chip. A structure of a semiconductor chip characterized by being formed.
JP43A 1992-12-01 1992-12-01 Structure of semiconductor chip Pending JPH06177178A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP43A JPH06177178A (en) 1992-12-01 1992-12-01 Structure of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP43A JPH06177178A (en) 1992-12-01 1992-12-01 Structure of semiconductor chip

Publications (1)

Publication Number Publication Date
JPH06177178A true JPH06177178A (en) 1994-06-24

Family

ID=18377821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP43A Pending JPH06177178A (en) 1992-12-01 1992-12-01 Structure of semiconductor chip

Country Status (1)

Country Link
JP (1) JPH06177178A (en)

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US6798078B2 (en) * 2000-12-14 2004-09-28 Yamaha Hatsudoki Kabushiki Kaisha Power control device with semiconductor chips mounted on a substrate
US7215013B2 (en) 2004-06-09 2007-05-08 Kabushiki Kaisha Toshiba Semiconductor device and semiconductor apparatus
JP2006351950A (en) * 2005-06-17 2006-12-28 Rohm Co Ltd Semiconductor device and method for manufacturing the same
JP2009253025A (en) * 2008-04-07 2009-10-29 Toyota Central R&D Labs Inc Module formed by bonding semiconductor device to substrate by metal layer
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US10249672B2 (en) 2012-05-30 2019-04-02 Olympus Corporation Image pickup apparatus, semiconductor apparatus, and image pickup unit
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