JPH06177148A - Fabrication of insulated gate field-effect transistor - Google Patents

Fabrication of insulated gate field-effect transistor

Info

Publication number
JPH06177148A
JPH06177148A JP32814592A JP32814592A JPH06177148A JP H06177148 A JPH06177148 A JP H06177148A JP 32814592 A JP32814592 A JP 32814592A JP 32814592 A JP32814592 A JP 32814592A JP H06177148 A JPH06177148 A JP H06177148A
Authority
JP
Japan
Prior art keywords
gate electrode
oxide film
gate
source
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32814592A
Other languages
Japanese (ja)
Inventor
Takashi Noguchi
隆 野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP32814592A priority Critical patent/JPH06177148A/en
Publication of JPH06177148A publication Critical patent/JPH06177148A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects

Abstract

PURPOSE:To enhance gate-drain (source) breakdown voltage by oxidizing a gate electrode to form an oxide film, removing the oxide film, implanting impurity ions using the gate electrode as a mask, thereby forming a lightly doped drain region and a source region. CONSTITUTION:A polycrystalline semiconductor gate electrode 3 is formed with a predetermined width on a semiconductor substrate through a gate insulation layer 2 and the surface of the gate electrode 3 is then oxidized to form an oxide film of predetermined thickness. The oxide film 4 is then removed by etching to leave the gate electrode 3 of width L1 which is used as a mask in the implantation of impurity ions thus forming a lightly doped drain and source regions 5, 6 on the semiconductor substrate 1. This method allows formation of an LDDMOS transistor having channel length shorter than that attainable by photolithography for forming the gate electrode 3 while enhancing gate-drain (source) breakdown voltage.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、絶縁ゲート型電界効果
トランジスタ（以下ＭＯＳトランジスタという）の製
法、特にＬＤＤ（Lightly Doped Drain ) すなわち低濃
度ドレインＭＯＳトランジスタの製法に係わる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an insulated gate field effect transistor (hereinafter referred to as a MOS transistor), and more particularly to a method for manufacturing an LDD (Lightly Doped Drain), that is, a low concentration drain MOS transistor.

【０００２】[0002]

【従来の技術】ＬＤＤＭＯＳトランジスタの製法として
は、種々のものが提案されている。例えば特開平４ー１
０４３４号公報、及び本出願人の出願に係る特願平３ー
２６８４６６号「ＭＩＳ型半導体装置の製造方法」等に
おいては、ゲート電極をマスクに低濃度ドレインを形成
するイオン注入工程（実際には、低濃度ドレイン領域と
低濃度ソース領域の形成とが同時に行われるものであ
り、以下このイオン注入工程をＬＤＤ工程という）が採
られ、高濃度すなわち低比抵抗のドレイン領域及びソー
ス領域については、上記ゲート電極を酸化させるとか、
ゲート電極の側壁にサイドウオールを形成して見掛け上
幅広となしてこれをマスクに低比抵抗ドレイン領域及び
ソース領域をゲート部から所要の距離を隔てて、すなわ
ちゲート部との間に低濃度のドレイン領域及びソース領
域が介在するように形成するものである。2. Description of the Related Art Various methods of manufacturing LDDMOS transistors have been proposed. For example, Japanese Patent Laid-Open No. 4-1
In Japanese Patent Application No. 0434 and Japanese Patent Application No. 3-268466 “manufacturing method of MIS type semiconductor device”, which is filed by the present applicant, an ion implantation step of forming a low concentration drain using a gate electrode as a mask (actually, , The low-concentration drain region and the low-concentration source region are formed at the same time, and this ion implantation process is hereinafter referred to as an LDD process), and the high-concentration or low specific resistance drain region and source region are To oxidize the gate electrode,
Sidewalls are formed on the side walls of the gate electrode to make them apparently wide, and this is used as a mask to separate the low specific resistance drain region and source region from the gate portion at a required distance, that is, between the gate portion and a low concentration. It is formed such that the drain region and the source region are interposed.

【０００３】したがって、通常一般のＬＤＤＭＯＳトラ
ンジスタにおいては、そのチャネル長は、実質的に始め
に形成するゲート電極の幅（長さ）によって決定されて
しまう。Therefore, in a general LDDMOS transistor, the channel length thereof is substantially determined by the width (length) of the gate electrode formed at the beginning.

【０００４】このゲート電極のパターン化は、フォトリ
ソグラフィによる選択的エッチングによって形成される
ことから、チャネル長は、フォトリソグラフィでの寸法
的制約すなわちその寸法的下限で決まってしまう。Since the patterning of the gate electrode is formed by selective etching by photolithography, the channel length is determined by the dimensional constraint in photolithography, that is, the dimensional lower limit.

【０００５】通常、フォトリソグラフィ工程でのフォト
レジストに対する露光処理は、ｇー線或いはこれより波
長の短いｉー線が用いられるが、この場合でもその幅し
たがってチャネル長は０．２μｍ程度が限界である。Normally, g-line or i-line having a shorter wavelength is used for the exposure process for the photoresist in the photolithography process, but even in this case, the width thereof and thus the channel length is limited to about 0.2 μm. is there.

【０００６】また、露光光源としてエキシマレーザを用
いた場合でも同様であり、更に電子ビームや、Ｘ線では
縮小投影露光を行うことができず量産性に劣るなどの問
題がある。The same is true when an excimer laser is used as an exposure light source, and there is a problem that mass production is poor because reduction projection exposure cannot be performed with an electron beam or X-ray.

【発明が解決しようとする課題】[Problems to be Solved by the Invention]

【０００７】本発明は、ゲート電極形成のフォトリソグ
ラフィの限界に制約されずに、０．２μｍ以下のチャネ
ル長を有するＬＤＤＭＯＳトランジスタをも製造するこ
とのできる絶縁ゲート型電界効果トランジスタの製法を
提供するものである。The present invention provides a method of manufacturing an insulated gate field effect transistor capable of manufacturing an LDDMOS transistor having a channel length of 0.2 μm or less without being restricted by the limit of photolithography for forming a gate electrode. It is a thing.

【０００８】[0008]

【課題を解決するための手段】本発明は、図１及び図２
にその一例の製造工程を示すように、半導体基体１上
に、ゲート絶縁層２を介して多結晶半導体ゲート電極３
を形成する工程（図１Ａ）と、この多結晶半導体ゲート
電極３の表面を酸化して所要の厚さの酸化膜４を形成す
る工程（図１Ｂ）と、この酸化膜４を除去する工程と、
この酸化膜４が除去された多結晶半導体ゲート電極３を
マスクに半導体基体１に低濃度の少なくともドレイン領
域５、実際上は低濃度ドレイン領域及びソース領域５及
び６を形成する不純物イオン注入工程（図２Ｂ）とを採
って目的とするＬＤＤＭＯＳトランジスタを形成する。The present invention is based on FIG. 1 and FIG.
As shown in the manufacturing process of the example, the polycrystalline semiconductor gate electrode 3 is formed on the semiconductor substrate 1 with the gate insulating layer 2 interposed therebetween.
1A), a step of oxidizing the surface of the polycrystalline semiconductor gate electrode 3 to form an oxide film 4 having a required thickness (FIG. 1B), and a step of removing the oxide film 4. ,
Using the polycrystalline semiconductor gate electrode 3 from which the oxide film 4 has been removed as a mask, an impurity ion implantation step of forming at least a low-concentration drain region 5, and actually a low-concentration drain region and source regions 5 and 6 in the semiconductor substrate 1 ( 2B) is adopted to form the desired LDDMOS transistor.

【作用】上述したように、本発明方法では、図１Ａに示
すように、ゲート電極３を所定の幅Ｌ0 に形成するもの
の、これを酸化するものであり、この酸化はいうまでも
なく多結晶半導体のゲート電極内部に進行することか
ら、この酸化膜４をエッチングすると、ゲート電極３は
図２Ｂで示すように初期の幅Ｌ0 より小なる幅Ｌ1とな
る。As described above, in the method of the present invention, as shown in FIG. 1A, the gate electrode 3 is formed to have a predetermined width L 0, but this is oxidized, and needless to say, this oxidation is large. Since the oxide film 4 is etched into the gate electrode of the crystalline semiconductor, when the oxide film 4 is etched, the gate electrode 3 has a width L 1 smaller than the initial width L 0 as shown in FIG. 2B.

【０００９】したがって、この幅Ｌ1 とされたゲート電
極をマスクとして形成された低濃度ドレイン領域及びソ
ース領域５及び６間の間隔すなわちゲート長は、フォト
リソグラフィによって決まるゲート電極８の幅（長さ）
Ｌ0 より小とすることができる。Therefore, the distance between the low-concentration drain region and the source regions 5 and 6 formed by using the gate electrode having the width L 1 as a mask, that is, the gate length, is determined by photolithography. )
It can be smaller than L 0 .

【００１０】[0010]

【実施例】図１及び図２を参照して本発明の一実施例を
説明する。図１Ａに示すように、半導体基体例えばＳｉ
基板の、素子形成部以外のフィールド部に厚い酸化膜に
よる絶縁層７いわゆるＬＯＣＯＳの形成を行う。そして
ＭＯＳトランジスタの形成部に熱酸化によって薄いＳｉ
Ｏ2 によるゲート絶縁層２を形成する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1A, a semiconductor substrate such as Si
An insulating layer 7 made of a thick oxide film, so-called LOCOS, is formed on a field portion of the substrate other than the element formation portion. Then, thin Si is formed on the formation portion of the MOS transistor by thermal oxidation.
A gate insulating layer 2 made of O 2 is formed.

【００１１】そして、例えばＣＶＤ（化学的気相成長）
法によって全面的に多結晶半導体例えば多結晶Ｓｉ層を
形成し、フォトリソグラフィによる選択的エッチングに
よって所要の幅Ｌ0 のゲート電極３を形成する。Then, for example, CVD (chemical vapor deposition)
A polycrystalline semiconductor, for example, a polycrystalline Si layer is formed on the entire surface by the method, and the gate electrode 3 having a required width L 0 is formed by selective etching by photolithography.

【００１２】その後、図１Ｂに示すように、ゲート電極
３の表面を所要の厚さ（深さ）に熱酸化する。Then, as shown in FIG. 1B, the surface of the gate electrode 3 is thermally oxidized to a required thickness (depth).

【００１３】そして、図２Ａに示すように、この酸化膜
４が形成されたゲート電極３をマスクとしてイオン注入
によって高濃度すなわち低比抵抗のドレイン領域及びソ
ース領域８及び９を形成する。このとき、酸化によって
形成された酸化膜４は実際上その厚さが外側にも膨出す
るので、このときのマスクの幅Ｌ2 は、初期の幅Ｌ0よ
り大となる。したがって、両領域８及び９の間隔はこれ
に応じて大となる。Then, as shown in FIG. 2A, drain regions and source regions 8 and 9 of high concentration, that is, low specific resistance are formed by ion implantation using the gate electrode 3 having the oxide film 4 as a mask. At this time, the thickness of the oxide film 4 formed by oxidation actually bulges outward, and the width L 2 of the mask at this time is larger than the initial width L 0 . Therefore, the distance between the two regions 8 and 9 is correspondingly large.

【００１４】次に、図２Ｂに示すように、酸化膜４をエ
ッチング除去し、これをマスクとしてイオン注入によっ
て低濃度のドレイン領域及びソース領域５及び６を形成
する。すなわちＬＤＤ工程を行う。このようにすると、
ゲート電極３の幅Ｌ1 が初期の幅Ｌ0 に比し小となるこ
とから、低濃度ドレイン領域及びソース領域８及び９間
の間隔は上記幅Ｌ1 に対応して小となる。Next, as shown in FIG. 2B, the oxide film 4 is removed by etching, and with this as a mask, low concentration drain regions and source regions 5 and 6 are formed by ion implantation. That is, the LDD process is performed. This way,
Since the width L 1 of the gate electrode 3 is smaller than the initial width L 0 , the distance between the low-concentration drain region and the source regions 8 and 9 is small corresponding to the width L 1 .

【００１５】上述した例では、多結晶半導体よりなるゲ
ート電極の表面を酸化してこの酸化膜４が形成された状
態で、高濃度のドレイン領域及びソース領域８及び９を
形成して、その後酸化膜４を除去してＬＤＤ工程を採っ
た場合であるが、例えば図２Ａの工程で例えば高濃度の
ドレイン領域及びソース領域８及び９を形成して後に同
様のマスクで斜め方向から回転イオン注入によってＬＤ
Ｄ工程を行うこともできる。In the above-mentioned example, the surface of the gate electrode made of a polycrystalline semiconductor is oxidized to form the oxide film 4, and then the high-concentration drain region and the source region 8 and 9 are formed and then oxidized. This is a case where the film 4 is removed and the LDD process is adopted. For example, in the process of FIG. LD
Step D can also be performed.

【００１６】この場合の一例を図３及び図４を参照して
説明する。An example of this case will be described with reference to FIGS. 3 and 4.

【００１７】この場合においても、図３Ａ及びＢで示す
ように、図１Ａ及びＢで示したと同様の工程を採る。Also in this case, as shown in FIGS. 3A and 3B, steps similar to those shown in FIGS. 1A and 1B are adopted.

【００１８】その後、図４Ａに示すように、酸化膜４を
エッチング除去し、これをマスクとしてイオン注入によ
って低濃度のドレイン領域及びソース領域５及び６を形
成する。すなわちＬＤＤ工程を行う。After that, as shown in FIG. 4A, the oxide film 4 is removed by etching, and using this as a mask, low concentration drain regions and source regions 5 and 6 are formed by ion implantation. That is, the LDD process is performed.

【００１９】そして、図４Ｂに示すように、全面的に例
えばＣＶＤ法によって所要の厚さの例えばＳｉＯ2 より
なる絶縁層１０を形成する。そして、ゲート電極３とそ
の側壁に形成された絶縁層１０を含んでこれをマスクと
して高濃度のドレイン領域及びソース領域８及び９を形
成する。Then, as shown in FIG. 4B, an insulating layer 10 made of, for example, SiO 2 having a required thickness is formed on the entire surface by, eg, CVD method. Then, the drain electrode and the source regions 8 and 9 of high concentration are formed by including the gate electrode 3 and the insulating layer 10 formed on the side wall of the gate electrode 3 as a mask.

【００２０】図３及び図４において、図１及び図２に対
応する部分には同一符号を付して重複説明を省略する。In FIGS. 3 and 4, parts corresponding to those in FIGS. 1 and 2 are designated by the same reference numerals, and duplicate description will be omitted.

【００２１】また、図３及び図４の例では、全面的に絶
縁層１０を形成した状態で高濃度ドレイン領域及びソー
ス領域８及び９の形成を行った場合であるが、図５に示
すように、異方性エッチングによって絶縁層１０の平面
部をエッチング除去してサイドウオール１１の形成を行
ってこのサイドウオール１１とゲート電極３をマスクと
して高濃度ドレイン領域及びソース領域８及び９の形成
を行うこともできる。In the examples of FIGS. 3 and 4, the high-concentration drain region and the source regions 8 and 9 are formed with the insulating layer 10 formed over the entire surface. As shown in FIG. Then, the flat portion of the insulating layer 10 is removed by anisotropic etching to form the side wall 11, and the high concentration drain region and the source regions 8 and 9 are formed using the side wall 11 and the gate electrode 3 as a mask. You can also do it.

【００２２】上述したように、本発明方法では、図１Ａ
や図４Ａに示すように、ゲート電極３を所定の幅Ｌ0 に
形成するものの、これを酸化させ、その後この酸化膜４
をエッチングして、これをマスクにＬＤＤ工程を行うの
で低濃度ドレイン領域及びソース領域５及び６間隔すな
わちゲート長は、図１Ａ及び図４Ａでのゲート電極３を
形成するフォトリソグラフィによって決まる長さより小
とすることができる。As described above, in the method of the present invention, FIG.
As shown in FIG. 4A and FIG. 4A, although the gate electrode 3 is formed to have a predetermined width L 0 , it is oxidized and then the oxide film 4 is formed.
And the LDD process is performed using this as a mask. Therefore, the interval between the low concentration drain region and the source regions 5 and 6, that is, the gate length is smaller than the length determined by the photolithography for forming the gate electrode 3 in FIGS. 1A and 4A. Can be

【００２３】また、ゲート電極３を酸化させる工程を採
ることから、ゲート電極３下のゲート絶縁層２もその縁
部で酸化層の厚さが増加することから、ゲートとドレイ
ン及びソース間の耐圧向上がはかられる。Further, since the step of oxidizing the gate electrode 3 is adopted, the thickness of the oxide layer at the edge portion of the gate insulating layer 2 under the gate electrode 3 also increases, so that the breakdown voltage between the gate, the drain and the source is increased. It can be improved.

【００２４】[0024]

【発明の効果】上述したように、本発明方法では、ゲー
ト電極形成するフォトリソグラフィで可能な幅以下のチ
ャネル長のＬＤＤＭＯＳトランジスタを形成でき、より
このトランジスタの微細化、したがって高速化が図ら
れ、しかもゲート・ドレイン（ソース）間の耐圧の向上
もはかられることから実用上の利益は甚大である。As described above, according to the method of the present invention, it is possible to form an LDDMOS transistor having a channel length equal to or shorter than the width that can be formed by photolithography for forming a gate electrode. Moreover, since the breakdown voltage between the gate and the drain (source) can be improved, the practical advantage is enormous.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明製法の一例の工程図（その１）である。FIG. 1 is a process diagram (1) of an example of the production method of the present invention.

【図２】本発明製法の一例の工程図（その２）である。FIG. 2 is a process diagram (2) of an example of the production method of the present invention.

【図３】本発明製法の他の例の工程図（その１）であ
る。FIG. 3 is a process diagram (1) of another example of the production method of the present invention.

【図４】本発明製法の他の例の工程図（その２）であ
る。FIG. 4 is a process diagram (2) of another example of the production method of the present invention.

【図５】本発明製法の更に他の例の一工程図である。FIG. 5 is a process chart of still another example of the production method of the present invention.

【符号の説明】[Explanation of symbols]

１ 半導体基体 ２ ゲート絶縁層 ３ ゲート電極 ４ 酸化膜 ５ 低濃度ドレイン領域 ６ 低濃度ソース領域 ８ 高濃度ドレイン領域 ９ 高濃度ソース領域 1 semiconductor substrate 2 gate insulating layer 3 gate electrode 4 oxide film 5 low concentration drain region 6 low concentration source region 8 high concentration drain region 9 high concentration source region

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/265 8617−4Ｍ Ｈ０１Ｌ 21/265 Ｖ 8617−4Ｍ Ｌ 7377−4Ｍ 29/78 ３０１ Ｌ ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical display location H01L 21/265 8617-4M H01L 21/265 V 8617-4M L 7377-4M 29/78 301 L

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体基体上に、ゲート絶縁層を介して
多結晶半導体ゲート電極を形成する工程と、 該多結晶半導体ゲート電極の表面を酸化して所要の厚さ
の酸化膜を形成する工程と、 該酸化膜を除去する工程と、 該酸化膜が除去された上記多結晶半導体ゲート電極をマ
スクに上記半導体基体に低濃度ドレイン領域を形成する
不純物イオン注入工程とを採ることを特徴とする絶縁ゲ
ート型電界効果トランジスタの製法。1. A step of forming a polycrystalline semiconductor gate electrode on a semiconductor substrate via a gate insulating layer, and a step of oxidizing the surface of the polycrystalline semiconductor gate electrode to form an oxide film having a required thickness. And a step of removing the oxide film, and an impurity ion implantation step of forming a low-concentration drain region in the semiconductor substrate using the polycrystalline semiconductor gate electrode from which the oxide film has been removed as a mask. Manufacturing method of insulated gate field effect transistor.
JP32814592A 1992-12-08 1992-12-08 Fabrication of insulated gate field-effect transistor Pending JPH06177148A (en)

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Application Number Priority Date Filing Date Title
JP32814592A JPH06177148A (en) 1992-12-08 1992-12-08 Fabrication of insulated gate field-effect transistor

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Application Number Priority Date Filing Date Title
JP32814592A JPH06177148A (en) 1992-12-08 1992-12-08 Fabrication of insulated gate field-effect transistor

Publications (1)

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JPH06177148A true JPH06177148A (en) 1994-06-24

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JP32814592A Pending JPH06177148A (en) 1992-12-08 1992-12-08 Fabrication of insulated gate field-effect transistor

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5476802A (en) * 1991-08-26 1995-12-19 Semiconductor Energy Laboratory Co., Ltd. Method for forming an insulated gate field effect transistor
KR100607731B1 (en) * 2002-09-17 2006-08-01 동부일렉트로닉스 주식회사 Method for forming a semiconductor gate line
JP2007520879A (en) * 2004-01-14 2007-07-26 東京エレクトロン株式会社 Method for trimming gate electrode
JP2007532001A (en) * 2004-03-31 2007-11-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Method for forming sidewall spacer
EP1469525A3 (en) * 2003-04-16 2007-12-05 Electronics and Telecommunications Research Institute MOSFET with Schottky source and drain contacts and method of manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5476802A (en) * 1991-08-26 1995-12-19 Semiconductor Energy Laboratory Co., Ltd. Method for forming an insulated gate field effect transistor
KR100607731B1 (en) * 2002-09-17 2006-08-01 동부일렉트로닉스 주식회사 Method for forming a semiconductor gate line
EP1469525A3 (en) * 2003-04-16 2007-12-05 Electronics and Telecommunications Research Institute MOSFET with Schottky source and drain contacts and method of manufacturing the same
JP2007520879A (en) * 2004-01-14 2007-07-26 東京エレクトロン株式会社 Method for trimming gate electrode
JP2007532001A (en) * 2004-03-31 2007-11-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Method for forming sidewall spacer

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