JPH0616550B2 - Shutter-barrier barrier semiconductor device - Google Patents
Shutter-barrier barrier semiconductor deviceInfo
- Publication number
- JPH0616550B2 JPH0616550B2 JP61046250A JP4625086A JPH0616550B2 JP H0616550 B2 JPH0616550 B2 JP H0616550B2 JP 61046250 A JP61046250 A JP 61046250A JP 4625086 A JP4625086 A JP 4625086A JP H0616550 B2 JPH0616550 B2 JP H0616550B2
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- Prior art keywords
- barrier
- metal layer
- insulating film
- compound semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
【発明の詳細な説明】 産業上の利用分野 本発明は，化合物半導体を使用するシヨツトキバリア半
導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shutter barrier semiconductor device using a compound semiconductor.
従来の技術 現在，金属と半導体との接触部に形成された障壁の整流
作用等を利用したシヨツトキバリア半導体装置は，シリ
コン半導体を使用したものが良好な高速動作特性を有す
る半導体装置として製品化されている。しかし，更に優
れた高速動作特性と高耐圧特性を有するシヨツトキバリ
ア半導体装置が要求された場合や，シリコン半導体を使
用したのではこのような要求に対応することは困難であ
り，高速化および高耐圧化に適する化合物半導体を使用
しなければならない。通常このような化合物半導体とし
ては，III−Ｖ族化合物が使用され，III−Ｖ族化合物の
中でも比較的良質の単結晶基板を製造できるｎ形ガリウ
ムひ素（GaAs）が使用されることが多い。2. Description of the Related Art At present, a shutter barrier semiconductor device utilizing a rectifying action of a barrier formed at a contact portion between a metal and a semiconductor has been commercialized as a semiconductor device having a good high speed operation characteristic using a silicon semiconductor. There is. However, it is difficult to meet such a demand when a shutter barrier semiconductor device having further excellent high-speed operation characteristics and high breakdown voltage characteristics is required, or it is difficult to meet such requirements by using a silicon semiconductor. A compound semiconductor suitable for the above must be used. As such a compound semiconductor, a III-V group compound is usually used, and n-type gallium arsenide (GaAs) that can produce a relatively high-quality single crystal substrate among the III-V group compounds is often used.
発明が解決しようとする問題点 ところで，GaAs半導体上にシヨツトキバリアを形成する
金属（バリア金属）としてアルミニウム（Al）を使用す
ると，製造と特性の両面で良好なシヨツトバリアを形成
することができる。AlをGaAs半導体上に形成した場合，
Alは蒸気圧の大きいAsとしか反応しないので，これらの
接触部分にはAl−As化合物が形成されるだけである。こ
のように，化合物半導体の構成元素の一部のみと化合物
を形成するバリア金属．あるいは構成元素のいずれもほ
とんど化合物を形成しないバリア金属を使用すると，バ
リア金属の化合物半導体への接着強度が小さく，大バリ
ア面積で大電流の半導体素子を製造することが困難であ
つた。Problems to be Solved by the Invention By using aluminum (Al) as a metal (barrier metal) for forming a shutter barrier on a GaAs semiconductor, it is possible to form a favorable shutter barrier in terms of both manufacturing and characteristics. When Al is formed on a GaAs semiconductor,
Since Al reacts only with As, which has a high vapor pressure, only Al-As compounds are formed at these contact points. Thus, a barrier metal that forms a compound with only some of the constituent elements of a compound semiconductor. Alternatively, if a barrier metal that does not form a compound in any of the constituent elements is used, the adhesion strength of the barrier metal to the compound semiconductor is small, and it is difficult to manufacture a semiconductor device having a large barrier area and a large current.
低温で化合物半導体と反応して液相を呈する金属や高融
点金属を使用すれば，上記接着強度の問題を解決させる
ことができる。しかし，このような半導体装置では，耐
熱性や化学的安定性の面で劣つていたり，高温処理によ
つて化合物半導体の結晶性を劣化させてしまうなどの別
の問題を招来することが多い。比較的低温での形成が可
能で，かつ半導体構成元素の全てと安定な化合物を形成
できる金属をバリア金属として使用できれば好都合なの
であるが，良好なシヨツトキバリアを形成できる金属が
見当たらないのが実状である。The use of a metal or a refractory metal that exhibits a liquid phase by reacting with a compound semiconductor at a low temperature can solve the above problem of adhesive strength. However, such a semiconductor device often causes other problems such as poor heat resistance and chemical stability and deterioration of crystallinity of the compound semiconductor due to high temperature treatment. . It would be convenient if a metal capable of forming at a relatively low temperature and capable of forming a stable compound with all of the semiconductor constituent elements could be used as a barrier metal, but the fact is that no metal capable of forming a good shutter barrier has been found. .
そこで本発明は，バリア金属の化合物半導体への接着強
度にかかわりなく，種々のバリア金属を使用することが
でき，かつ化合物半導体からバリア金属が剥離すること
を防止できるシヨツトバリア半導体装置を提供すること
を目的とする。Therefore, the present invention provides a shot barrier semiconductor device which can use various barrier metals regardless of the adhesion strength of the barrier metal to the compound semiconductor and can prevent the barrier metal from peeling from the compound semiconductor. To aim.
問題点を解決するための手段 本発明によるシヨツトキバリア半導体装置は、化合物半
導体領域とその表面に被覆された金属層とを有する。こ
のシヨツトキバリア半導体装置では、化合物半導体領域
の表面の一部が絶縁膜によって被覆され、絶縁膜によっ
て皮膚されていない２ケ所以上の化合物半導体領域の表
面と絶縁膜の３ケ所以上の表面とが交互に位置する部分
を有し、この部分に金属層が連続して被覆され、絶縁膜
によって被覆されていない化合物半導体領域の表面と金
属層との接触部分においてショットキバリアが形成され
る。絶縁膜と金属層との接着強度および絶縁膜と化合物
半導体領域との装着強度は、金属層と化合物半導体領域
との接着強度より大きい。Means for Solving the Problems The Schottky barrier semiconductor device according to the present invention has a compound semiconductor region and a metal layer coated on the surface thereof. In this shutter barrier semiconductor device, a part of the surface of the compound semiconductor region is covered with an insulating film, and the surface of the compound semiconductor region in two or more places not covered by the insulating film and the surface of the insulating film in three or more places alternate. A Schottky barrier is formed at the contact portion between the surface of the compound semiconductor region which is not covered with the insulating film and the metal layer. The adhesive strength between the insulating film and the metal layer and the mounting strength between the insulating film and the compound semiconductor region are higher than the adhesive strength between the metal layer and the compound semiconductor region.
作 用 本発明によれば，金属層−絶縁膜−化合物半導体の３層
構造部分の接着強度を充分に大きくすることが可能であ
る。したがつて，金属層と化合物半導体との接着強度が
弱くても，その周辺における前記３層構造部分の接着力
によつて金属層の剥離を実用上充分に防止することがで
きる。Operation According to the present invention, it is possible to sufficiently increase the adhesive strength of the three-layer structure portion of the metal layer-insulating film-compound semiconductor. Therefore, even if the adhesive strength between the metal layer and the compound semiconductor is weak, the peeling of the metal layer can be sufficiently prevented practically due to the adhesive force of the three-layer structure portion around the metal layer.
実施例 以下，本発明の実施例を図面に基づいて説明する。Embodiment An embodiment of the present invention will be described below with reference to the drawings.
第１図および第２図に示すとおり，本発明によるシヨツ
トキバリア半導体装置は，ｎ+形GaAs領域１の上にｎ形G
aAs領域２がエピタキシヤル成長によつて形成された基
板３を有する。ｎ形GaAs領域２の表面の一部には，シリ
コン窒化膜（Si3N4）から成る絶縁膜４が形成される。
絶縁膜４は，全体の外形としては矩形形状を有し，破線
で示されるように複数の開孔部５がちどり状に形成され
る。したがつて，絶縁膜４は，網目状に形成される。絶
縁膜４は，CVD（Chemical Vapor Deposition,化学的気
相成長）法で作成され，フオトエツチングによつて所定
のパターンに形成される。As shown in FIG. 1 and FIG. 2, the shutter barrier semiconductor device according to the present invention has an n-type G on the n + -type GaAs region 1.
The aAs region 2 has a substrate 3 formed by epitaxial growth. An insulating film 4 made of a silicon nitride film (Si 3 N 4 ) is formed on a part of the surface of the n-type GaAs region 2.
The insulating film 4 has a rectangular outer shape as a whole, and a plurality of openings 5 are formed in a striped shape as shown by a broken line. Therefore, the insulating film 4 is formed in a mesh shape. The insulating film 4 is formed by a CVD (Chemical Vapor Deposition) method and is formed into a predetermined pattern by photo etching.
更に，蒸着によつて上面のほぼ全面に，Alから成る金属
層６が形成される。金属層６は，全面に蒸着後，フオト
エツチングによつて絶縁膜４の全体形状より微かに小さ
い矩形形状に形成される。金属層６の周辺端部は，絶縁
膜４の上に位置させている。金属層６，開孔部５におい
てｎ形GaAs領域２との界面にシヨツトキバリアを形成す
る。なお，金属層６はバリア金属としての役割と外部へ
の接続用電極としての役割を兼ねている。ｎ+形GaAs領
域１の下面には，低抵抗接触した電極７が形成される。
電極７は，金−ゲルマニウム（Au−Ge）合金とニツケル
（Ni）を順次蒸着して形成される。Further, a metal layer 6 made of Al is formed on almost the entire upper surface by vapor deposition. After the metal layer 6 is deposited on the entire surface, it is formed into a rectangular shape slightly smaller than the entire shape of the insulating film 4 by photo etching. The peripheral edge of the metal layer 6 is located on the insulating film 4. A shutter barrier is formed at the interface with the n-type GaAs region 2 in the metal layer 6 and the opening 5. The metal layer 6 serves both as a barrier metal and an electrode for connecting to the outside. An electrode 7 having a low resistance contact is formed on the lower surface of the n + type GaAs region 1.
The electrode 7 is formed by sequentially vapor-depositing a gold-germanium (Au-Ge) alloy and nickel (Ni).
本発明のシヨツトキバリア半導体では，第２図のように
円形の開孔部５内に形成されるシヨツトキバリアのほ
か，種々の形状のシヨツトバリアを形成することができ
る。例えば，第３図(A)(B)に示すように，絶縁膜４は島
状に分離した部分4aとこれらを囲む環状部分4bを有する
ように形成され，開孔部5aとシヨツトバリアは網目状に
形成された構造としてもよい。また，第４図(A)(B)に示
すように，絶縁膜４は複数の帯状部分が並列するように
形成され，シヨツトキバリアも開孔部分5b内に帯状に形
成された構造としてもよい。また，第５図(A)(B)に示す
ように，絶縁膜４は同心状の複数の環状部分に分離して
形成され，シヨツトキバリアも開孔部5c内に同心状で環
状に分離して形成された構造としてもよい。更に，第６
図(A)(B)に示すように，絶縁膜４は螺旋状に形成され，
シヨツトキバリアも螺旋状開孔部5d内に螺旋状に形成さ
れた構造としてもよい。In the shutter barrier semiconductor of the present invention, in addition to the shutter barrier formed in the circular opening portion 5 as shown in FIG. 2, it is possible to form various barrier barrier shapes. For example, as shown in FIGS. 3 (A) and 3 (B), the insulating film 4 is formed so as to have an island-shaped separated portion 4a and an annular portion 4b surrounding the island-shaped portion 4a, and the openings 5a and the shot barrier are mesh-shaped. It may be a structure formed in. Further, as shown in FIGS. 4 (A) and 4 (B), the insulating film 4 may be formed such that a plurality of strip-shaped portions are arranged in parallel, and the shutter barrier may also be formed in a strip-like shape in the opening portion 5b. Further, as shown in FIGS. 5 (A) and 5 (B), the insulating film 4 is formed by being divided into a plurality of concentric annular portions, and the shutter barrier is also divided into concentric annular portions within the opening 5c. It may be a formed structure. Furthermore, the sixth
As shown in FIGS. (A) and (B), the insulating film 4 is formed in a spiral shape,
The shutter barrier may also have a structure formed in a spiral shape within the spiral opening 5d.
本発明のシヨツトキバリア半導体装置では，Al層からな
る金属層６とｎ形GaAs領域２の接着強度は，AlがAsとは
反応してもGaとはほとんど反応しないため，比較的小さ
い。しかし，Si3N4膜から成る絶縁膜４は，ｎ形GaAs領
域２と金属層６の両方に対して比較的大きい接着強度を
示す。すなわち，絶縁膜４と金属層６との接着強度およ
び絶縁膜４とｎ形GaAs領域２との接着強度は，金属層６
とｎ形GaAs領域との接着強度より大である。したがつ
て，金属層６全体としては十分な接着力が確保され，金
属層６が比較的大面積であつても，金属層６の剥離が起
こり難い。なお，金属層６の周辺を絶縁膜４の上に位置
させているのは，金属層６の周辺が起点となつて金属層
６の剥離が進行するのを防止するためである。In the Schottky barrier semiconductor device of the present invention, the adhesion strength between the metal layer 6 made of an Al layer and the n-type GaAs region 2 is relatively small because Al reacts with As and hardly reacts with Ga. However, the insulating film 4 made of the Si 3 N 4 film has a relatively high adhesive strength to both the n-type GaAs region 2 and the metal layer 6. That is, the adhesive strength between the insulating film 4 and the metal layer 6 and the adhesive strength between the insulating film 4 and the n-type GaAs region 2 are
Is larger than the adhesive strength between the n-type GaAs region and the n-type GaAs region. Therefore, a sufficient adhesive force is ensured for the metal layer 6 as a whole, and even if the metal layer 6 has a relatively large area, peeling of the metal layer 6 is unlikely to occur. The reason that the periphery of the metal layer 6 is located on the insulating film 4 is to prevent the peeling of the metal layer 6 from proceeding with the periphery of the metal layer 6 as the starting point.
本発明は，上記実施例に限られるものではなく，同一技
術思想の範囲内で種々の変更が可能である。例えば，金
属層６は，第１図の実施例ではバリア金属と接続用電極
の二機能を有するものであつたが，第７図に示すよう
に，バリア金属6aと接続用電極6bに分けて別の金属で構
成してもよい。具体的には，バリア金属6aをAlまたはAl
合金の蒸着層とし，接続用電極6bを薄い亜鉛(Zn)の置換
メツキ層をはさんでニツケル(Ni)メツキ層で構成すれ
ば，半田付による外部接続が可能な金属層６を形成でき
る。バリア金属6aを開孔部５に限るように形成してもよ
い。ｎ形GaAs領域２の上面を平坦面で形成する例で説明
したが，この上面に溝等を形成することもある。また，
化合物半導体領域をIII−Ｖ族化合物であるGaAsで構成
し，絶縁膜をS3N4膜で構成する例を示したが，本発明
は，これらの物質に限定されないことも理解できよう。
例えば，化合物半導体領域をインジウム燐(InP)とする
こともできるし，絶縁膜としてはシリコン酸化膜（Si
O2）を使用することもできる。The present invention is not limited to the above embodiments, but various modifications can be made within the scope of the same technical idea. For example, although the metal layer 6 has the dual function of the barrier metal and the connecting electrode in the embodiment of FIG. 1, it is divided into the barrier metal 6a and the connecting electrode 6b as shown in FIG. It may be composed of another metal. Specifically, the barrier metal 6a is Al or Al
The metal layer 6 capable of external connection by soldering can be formed by using an alloy vapor deposition layer and forming the connection electrode 6b by a nickel (Ni) plating layer with a thin zinc (Zn) substitution plating layer sandwiched therebetween. The barrier metal 6a may be formed so as to be limited to the opening 5. Although an example in which the upper surface of the n-type GaAs region 2 is formed as a flat surface has been described, a groove or the like may be formed on this upper surface. Also,
Although the example in which the compound semiconductor region is composed of GaAs which is a III-V group compound and the insulating film is composed of an S 3 N 4 film has been shown, it will be understood that the present invention is not limited to these materials.
For example, the compound semiconductor region may be made of indium phosphide (InP), and the insulating film may be made of a silicon oxide film (SiP).
O 2 ) can also be used.
発明の効果 本発明によれば，金属層の化合物半導体領域への接着強
度が弱くても，金属層の剥離を防止することができ，製
造歩留および信頼性の低下を回避できる。また，バリア
金属の選択の範囲が広くなる。これらの結果，化合物半
導体を用いたシヨツトキバリア半導体装置の大面積化，
大電流化に貢献することができる。EFFECTS OF THE INVENTION According to the present invention, even if the adhesion strength of the metal layer to the compound semiconductor region is weak, the peeling of the metal layer can be prevented, and the reduction in manufacturing yield and reliability can be avoided. Moreover, the range of selection of the barrier metal is widened. As a result, the area of the shutter barrier semiconductor device using the compound semiconductor is increased,
It can contribute to a large current.
第１図および第２図は本発明の実施例を示し，第１図は
本発明によるシヨツトバリア半導体装置の断面図（第２
図のII−II線断面），第２図はこの平面図である。第３
図〜第６図は本発明の他の実施例を示し，それぞれ(Ａ)
は(Ｂ)のIII−III，IV−IV，Ｖ−ＶおよびVI−VI線断面
図，(Ｂ)はこれらの平面図である。第７図は，更に他の
実施例を示す部分的断面図である。 １……ｎ+形GaAs領域，２……ｎ形GaAs領域，３……基
板，４……絶縁膜，５……開孔部，６……金属層1 and 2 show an embodiment of the present invention, and FIG. 1 is a sectional view of a short-barrier semiconductor device according to the present invention (second embodiment).
FIG. 2 is a plan view of FIG. 2). Third
6 to 6 show other embodiments of the present invention, each of which (A)
Is a sectional view taken along line III-III, IV-IV, VV and VI-VI of (B), and (B) is a plan view thereof. FIG. 7 is a partial sectional view showing still another embodiment. 1 ... n + type GaAs region, 2 ... n type GaAs region, 3 ... substrate, 4 ... insulating film, 5 ... opening, 6 ... metal layer
───────────────────────────────────────────────────── フロントページの続き (72)発明者 市野沢 秀幸 埼玉県新座市北野３丁目６番３号 サンケ ン電気株式会社内 (72)発明者 島田 悠紀 東京都武蔵野市緑町３丁目９番11号 日本 電信電話株式会社電子機構技術研究所内 (72)発明者 酒井 達郎 東京都武蔵野市緑町３丁目９番11号 日本 電信電話株式会社電子機構技術研究所内 (56)参考文献 特開 昭58−212184（ＪＰ，Ａ) 特開 昭56−2672（ＪＰ，Ａ) 特開 昭55−162273（ＪＰ，Ａ) 特公 昭47−31077（ＪＰ，Ｂ１) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideyuki Ichinozawa 3-6-3 Kitano, Niiza City, Saitama Sanken Electric Co., Ltd. (72) Inventor Yuki Shimada 3-9-11 Midoricho, Musashino City, Tokyo Japan In the Institute of Electronics, Technical Research, Telegraph and Telephone Corporation (72) Tatsuro Sakai, 3-9-11, Midoricho, Musashino-shi, Tokyo In the Institute of Electronics and Technical Research, Nippon Telegraph and Telephone Corporation (56) Reference JP-A-58-212184 (JP , A) JP 56-2672 (JP, A) JP 55-162273 (JP, A) JP 47-31077 (JP, B1)
Claims (1)
金属層とを備え、前記化合物半導体領域の表面の一部が
絶縁膜によって被覆され、該絶縁膜によって被覆されて
いない２ケ所以上の前記化合物半導体領域の表面と前記
絶縁膜の３ケ所以上の表面とが交互に位置する部分を有
し、この部分に前記金属層が連続して被覆され、前記絶
縁膜によって被覆されていない化合物半導体領域の表面
と前記金属層との接触部分においてショットキバリアが
形成されたショットキバリア半導体装置において、 前記絶縁膜と前記金属層との接着強度および前記絶縁膜
と前記化合物半導体領域との装着強度は、前記金属層と
前記化合物半導体領域との接着強度より大きいことを特
徴とするショットキバリア半導体装置。1. A compound semiconductor region and a metal layer coated on the surface of the compound semiconductor region, wherein a part of the surface of the compound semiconductor region is covered with an insulating film, and at two or more locations not covered with the insulating film. The compound semiconductor region has a portion in which the surface of the compound semiconductor region and three or more surfaces of the insulating film are alternately positioned, and the metal layer is continuously coated on this portion, and the compound semiconductor region is not covered by the insulating film. In a Schottky barrier semiconductor device in which a Schottky barrier is formed at the contact portion between the surface of the metal layer and the metal layer, the adhesive strength between the insulating film and the metal layer and the mounting strength between the insulating film and the compound semiconductor region are A Schottky barrier semiconductor device having a bonding strength greater than that of a metal layer and the compound semiconductor region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61046250A JPH0616550B2 (en) | 1986-03-05 | 1986-03-05 | Shutter-barrier barrier semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61046250A JPH0616550B2 (en) | 1986-03-05 | 1986-03-05 | Shutter-barrier barrier semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62204572A JPS62204572A (en) | 1987-09-09 |
| JPH0616550B2 true JPH0616550B2 (en) | 1994-03-02 |
Family
ID=12741914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61046250A Expired - Lifetime JPH0616550B2 (en) | 1986-03-05 | 1986-03-05 | Shutter-barrier barrier semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0616550B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5998169B2 (en) | 2014-03-26 | 2016-09-28 | 株式会社豊田中央研究所 | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55162273A (en) * | 1979-06-04 | 1980-12-17 | Origin Electric Co Ltd | Schottky barrier diode |
| JPS562672A (en) * | 1979-06-20 | 1981-01-12 | Shindengen Electric Mfg Co Ltd | Schottky barrier diode |
| JPS58212184A (en) * | 1982-02-04 | 1983-12-09 | Sanyo Electric Co Ltd | Schottky barrier diode associated in semiconductor integrated circuit |
-
1986
- 1986-03-05 JP JP61046250A patent/JPH0616550B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62204572A (en) | 1987-09-09 |
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