JPH06152401A - Pll circuit - Google Patents
Pll circuitInfo
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- JPH06152401A JPH06152401A JP4302226A JP30222692A JPH06152401A JP H06152401 A JPH06152401 A JP H06152401A JP 4302226 A JP4302226 A JP 4302226A JP 30222692 A JP30222692 A JP 30222692A JP H06152401 A JPH06152401 A JP H06152401A
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- Prior art keywords
- voltage
- gain
- current
- converter
- controlled oscillator
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はPLL回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit.
【0002】[0002]
【従来の技術】図7に従来のPLL回路の構成を示す。
入力信号の位相と電圧制御発振器(以下“VCO”とい
う)103の出力信号の位相とを位相比較器101で比
較し、その位相差に相当する信号がループフィルタ10
2を介して制御信号としてVCO103に入力される。
したがって、VCO103の出力信号bは、入力信号と
位相が一致する方向に制御され、入力信号にロックされ
る。VCO103は、入力信号の電圧値(V)を電流値
(I)に変換するV/I変換器103Aと、このV/I
変換器103Aの出力に応じた周波数の信号を発振し、
出力する電流制御発振器(以下“ICO”という)10
3Bとから構成される。また、ループフィルタ102に
は、PLL回路の安定性の点から、ラグ・リード・フィ
ルタがしばしば用いられる。2. Description of the Related Art FIG. 7 shows the configuration of a conventional PLL circuit.
The phase comparator 101 compares the phase of the input signal with the phase of the output signal of the voltage controlled oscillator (hereinafter referred to as “VCO”) 103, and the signal corresponding to the phase difference is detected by the loop filter 10
It is input to the VCO 103 via 2 as a control signal.
Therefore, the output signal b of the VCO 103 is controlled so as to be in phase with the input signal and locked to the input signal. The VCO 103 includes a V / I converter 103A that converts a voltage value (V) of an input signal into a current value (I), and the V / I converter 103A.
Oscillates a signal with a frequency corresponding to the output of the converter 103A,
Output current controlled oscillator (hereinafter referred to as "ICO") 10
3B and 3B. A lag lead filter is often used as the loop filter 102 from the viewpoint of the stability of the PLL circuit.
【0003】[0003]
【発明が解決しようとする課題】図8にループフィルタ
にラグ・リード・フィルタを用いた従来のPLL回路の
ゲインおよび位相特性を示す。図8から、高い周波数で
は回路の時間遅れ等の影響で急激なゲインの減少および
位相変化が生じることがわかる。FIG. 8 shows gain and phase characteristics of a conventional PLL circuit using a lag lead filter as a loop filter. It can be seen from FIG. 8 that at a high frequency, the gain is rapidly reduced and the phase is changed due to the influence of the time delay of the circuit.
【0004】PLL回路として、高い安定性を得るため
には、十分な位相余裕がある状態でゲインが1となるこ
とが望ましい(図8では周波数aでこの条件が満たされ
ている)。In order to obtain high stability as a PLL circuit, it is desirable that the gain be 1 with a sufficient phase margin (this condition is satisfied at the frequency a in FIG. 8).
【0005】しかしながら、実際にはこのようなPLL
回路のIC化の際のばらつきによって、VCOのゲイン
が変化する。このためPLL回路のゲインが1となる周
波数が例えばaの前後に変化し、位相余裕が減少してし
まう。その結果、PLL回路の位相伝達特性が変化し
(ピーキングが生じる)、最悪の場合には発振状態とな
り、動作しなくなってしまう。すなわち、PLL回路の
位相伝達特性とは、入力信号に一定のジッター(ノイ
ズ)を重複し、これがどれだけ出力に現われるかを表わ
したもの(出力ジッター/入力ジッター)であり、図9
にその例を示す。図9において、ゲインが0dBの箇所
は入力と同じレベルで出力にジッターが現われているこ
とを示しており、bは、PLL回路のゲインが大きくな
り位相余裕が減少したときの特性を示し、cはPLL回
路のゲインが小さくなり位相余裕が減少したときの特性
を示し、dは位相余裕が十分あるときの特性を示してい
る。このように、位相余裕が減少することによって、位
相伝達特性にピーキング(ジッターが増幅されている)
が生じ、同期状態でPLL回路の周波数、位相精度が悪
化してしまう。However, such a PLL is actually used.
The gain of the VCO changes due to variations in the circuit when integrated into an IC. Therefore, the frequency at which the gain of the PLL circuit becomes 1 changes before and after a, for example, and the phase margin decreases. As a result, the phase transfer characteristic of the PLL circuit changes (peaking occurs), and in the worst case, it becomes an oscillating state and stops operating. That is, the phase transfer characteristic of the PLL circuit represents how much a certain jitter (noise) is overlapped with the input signal and appears in the output (output jitter / input jitter).
An example is shown in. In FIG. 9, the portion where the gain is 0 dB shows that the jitter appears in the output at the same level as the input, b shows the characteristic when the gain of the PLL circuit increases and the phase margin decreases, and c Shows the characteristic when the gain of the PLL circuit becomes small and the phase margin decreases, and d shows the characteristic when the phase margin is sufficient. In this way, the phase margin is reduced, and thus the peaking of the phase transfer characteristic (jitter is amplified).
Occurs, the frequency and phase accuracy of the PLL circuit deteriorates in the synchronized state.
【0006】そこで本発明の目的は以上のような問題を
解消したPLL回路を提供することにある。Therefore, an object of the present invention is to provide a PLL circuit which solves the above problems.
【0007】[0007]
【課題を解決するための手段】上記目的を達成するため
本発明は電圧制御発振器と、入力信号の位相と前記電圧
制御発振器の出力信号の位相とを比較する位相比較器
と、該位相比較器の出力信号を入力して前記電圧制御発
振器へ制御電圧を出力するループフィルタとから構成さ
れるPLL回路において、前記電圧制御発振器は、前記
ループフィルタの出力電圧を電流に変換する電圧−電流
変換器と、前記位相比較器に前記出力信号を与える電流
制御発振器と、前記電圧−電流変換器から前記電流制御
発振器に供給する電流を調節するゲイン調節器とを有す
ることを特徴とする。To achieve the above object, the present invention provides a voltage controlled oscillator, a phase comparator for comparing the phase of an input signal with the phase of an output signal of the voltage controlled oscillator, and the phase comparator. Of a loop filter for inputting the output signal of the above and outputting a control voltage to the voltage controlled oscillator, the voltage controlled oscillator is a voltage-current converter for converting the output voltage of the loop filter into a current. And a current control oscillator that gives the output signal to the phase comparator, and a gain adjuster that adjusts the current supplied from the voltage-current converter to the current control oscillator.
【0008】[0008]
【作用】本発明によれば、VCOのゲインを調節するこ
とによって、製造時のばらつきが補償され、ループ帯域
が一定になる。According to the present invention, by adjusting the gain of the VCO, variations in manufacturing are compensated and the loop band becomes constant.
【0009】[0009]
【実施例】以下、図面を参照して本発明の実施例を詳細
に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【0010】図1は本発明の実施例を示す。図1に示す
ように、位相比較器1は入力信号の位相とVCO2の出
力信号の位相とを比較して、その位相差に相当する信号
をループフィルタ3に入力する。4は3入力1出力型の
スイッチであって、ループフィルタ3からの出力信号、
および互いに異なった値の2つの基準電圧(VREF
1,VREF2)を入力し、較正回路5からの制御信号
に基づいて3入力のいずれか1つを選択し出力する。FIG. 1 shows an embodiment of the present invention. As shown in FIG. 1, the phase comparator 1 compares the phase of the input signal with the phase of the output signal of the VCO 2, and inputs a signal corresponding to the phase difference to the loop filter 3. Reference numeral 4 denotes a 3-input 1-output type switch, which is an output signal from the loop filter 3,
And two reference voltages (VREF with different values
1, VREF2) is input, and one of the three inputs is selected and output based on the control signal from the calibration circuit 5.
【0011】VCO2は、V/I変換器2Aと、ICO
2Bと、ゲイン調節器2Cとを有する。V/I変換器2
Aはスイッチ4からの出力信号を入力し、V/I変換し
て、ゲイン調節器2Cに入力する。ゲイン調節器2Cは
較正回路5からの信号(詳細は後述する)に基づいてV
/I変換器2AからICO2Bに流れる電流の値を調節
する。The VCO 2 includes a V / I converter 2A and an ICO.
2B and a gain adjuster 2C. V / I converter 2
A inputs the output signal from the switch 4, V / I converts it, and inputs it to the gain controller 2C. The gain adjuster 2C receives V from the signal from the calibration circuit 5 (details will be described later).
The value of the current flowing from the / I converter 2A to the ICO 2B is adjusted.
【0012】図2はVCO2の詳細を示す。V/I変換
器2Aは演算増幅器6によってスイッチ4からの信号電
圧を電圧に変換して、トランジスタ7,8を介して出力
する。ゲイン調節器2Cは、複数のトランジスタ9〜1
2と各トランジスタ9〜12に直列接続したスイッチ1
3〜16とを並列接続し、各トランジスタ9〜12のゲ
ートにV/I変換器2Aからの出力電流を共通に入力
し、較正回路5からの信号に基づいて各スイッチ13〜
16を閉じ、閉じたスイッチ数が増加する毎にV/I変
換器2AからICO2Bに流れる電流値を増加させる。
例えば閉じたスイッチ数が1つではVCO2のゲインは
最小となり、閉じたスイッチ数が増加する毎にVCO2
のゲインは増加する。ICO2Bは、2つのコンデンサ
17,18を有し、ゲイン調節器2Cからの電流の値に
応じてこれらのコンデンサ17,18への充電時間が変
化し、出力信号の周波数が変化する。すなわち、今、I
CO2Bの出力AがLowからHighに変化した場合
を考えると、フリップフロップ19の出力Bは、Hig
hからLowになり、P MOS FET 20はオン
し、N MOS FET 21はオフになり、両FET
20,21のソース・ドレンの接続点(G)に接続した
コンデンサ18は前記ゲイン調節器2Cからの電流に比
例した速度で充電を始める。この時、2つのFET2
2,23のソース・ドレインの接続点(F)に接続した
コンデンサ17は放電する。FIG. 2 shows details of the VCO2. The V / I converter 2A converts the signal voltage from the switch 4 into a voltage by the operational amplifier 6 and outputs the voltage via the transistors 7 and 8. The gain adjuster 2C includes a plurality of transistors 9 to 1
2 and switch 1 connected in series with each transistor 9-12
3 to 16 are connected in parallel, the output current from the V / I converter 2A is commonly input to the gates of the transistors 9 to 12, and the switches 13 to 13 are connected based on the signal from the calibration circuit 5.
16 is closed, and the current value flowing from the V / I converter 2A to the ICO 2B is increased each time the number of closed switches is increased.
For example, if the number of closed switches is one, the gain of VCO2 becomes the minimum, and as the number of closed switches increases, VCO2
Gain increases. The ICO 2B has two capacitors 17 and 18, the charging time of these capacitors 17 and 18 changes according to the value of the current from the gain adjuster 2C, and the frequency of the output signal changes. That is, now I
Considering the case where the output A of CO2B changes from Low to High, the output B of the flip-flop 19 is High.
From h to Low, P MOS FET 20 turns on, N MOS FET 21 turns off, both FETs
The capacitor 18 connected to the connection point (G) between the source and drain of 20 and 21 starts charging at a rate proportional to the current from the gain adjuster 2C. At this time, two FET2
The capacitor 17 connected to the connection point (F) between the source and drain 2 and 23 is discharged.
【0013】コンデンサ18の充電電圧が基準電位Va
を越えると、コンパレータ24はHighになり、その
出力Eはオアゲート25(出力C)を介してフリップフ
ロップ19のクロック入力端に入力し、その出力Aが反
転しHighからLowになる。このとき、P MOS
FET 20はオフし、N MOS FET 21は
オンし、コンデンサ18は放電され、コンパレータ26
(出力D)の+入力端に接続のコンデンサ17がゲイン
調節器2Cからの電流に比例した速度で充電を開始す
る。The charging voltage of the capacitor 18 is the reference potential Va.
After that, the comparator 24 becomes High, its output E is input to the clock input terminal of the flip-flop 19 via the OR gate 25 (output C), and its output A is inverted and becomes High to Low. At this time, the PMOS
The FET 20 is turned off, the NMOS FET 21 is turned on, the capacitor 18 is discharged, and the comparator 26
The capacitor 17 connected to the + input terminal of (output D) starts charging at a rate proportional to the current from the gain adjuster 2C.
【0014】以上のようにして、ゲイン調節器2Cから
の電流に対応して、コンデンサ17,18の充電時間が
変化してICO2B(VCO2)の出力信号の周波数が
変化する。As described above, the charging time of the capacitors 17 and 18 changes according to the current from the gain adjuster 2C, and the frequency of the output signal of the ICO 2B (VCO2) changes.
【0015】図3は較正回路5の詳細を示す。27,2
8は各々Jビット,Kビットカウンタ、29はLビット
比較器(K>L)、30はNビットカウンタ(Nはゲイ
ン調節器2Cのトランジスタの数と同じ)である。31
は制御回路であって、前記各カウンタ27,28,30
およびLビット比較器29を制御し、かつ、スイッチ4
を制御して、3入力のうちの1つを選択させる。FIG. 3 shows details of the calibration circuit 5. 27,2
Reference numeral 8 is a J-bit / K-bit counter, 29 is an L-bit comparator (K> L), and 30 is an N-bit counter (N is the same as the number of transistors of the gain adjuster 2C). 31
Is a control circuit, and each of the counters 27, 28, 30
And L-bit comparator 29 and switch 4
Control to select one of the three inputs.
【0016】Jビットカウンタ27は任意の周波数のパ
ルス信号faをカウントし、Kビットカウンタ28はI
CO2Bの出力信号をカウントし、Lビット比較器29
はKビットカウンタ28の下位Lビットの値とゲイン設
定値M(M≦L)とを比較し、比較結果を制御回路31
に入力する。Nビットカウンタ230は制御回路31に
よって設定されたビット数だけゲイン調節器2Cのスイ
ッチをオンする。The J-bit counter 27 counts the pulse signal fa having an arbitrary frequency, and the K-bit counter 28 counts I.
The output signal of CO2B is counted, and the L-bit comparator 29
Compares the value of the lower L bits of the K-bit counter 28 with the gain setting value M (M ≦ L), and outputs the comparison result to the control circuit 31.
To enter. The N-bit counter 230 turns on the switch of the gain adjuster 2C by the number of bits set by the control circuit 31.
【0017】以上の構成によるPLL回路の較正動作を
説明する。なお、ここでスイッチ4に入力するVREF
1,VREF2は、VREF1=VREF2+1Vとす
る。A calibration operation of the PLL circuit having the above configuration will be described. In addition, VREF input to the switch 4 here
1 and VREF2 are set to VREF1 = VREF2 + 1V.
【0018】 まず、Nビットカウンタ30をN=1
とする(VCO2のゲインは最小)。First, the N-bit counter 30 is set to N = 1.
(The gain of VCO2 is the minimum).
【0019】 VREF1をV/I変換器2Aに入力
すると共に、J,Kビットカウンタ27,28をリセッ
トする(0にする)。VREF1 is input to the V / I converter 2A, and the J and K bit counters 27 and 28 are reset (set to 0).
【0020】 J,Kビットカウンタ27,28のカ
ウントアップをスタートする。The counting up of the J, K bit counters 27, 28 is started.
【0021】 Jビットカウンタ27のフルカウント
でKビットカウンタ28のカウントをストップする。When the J-bit counter 27 is fully counted, the K-bit counter 28 stops counting.
【0022】 Jビットカウンタ27を0にし、VR
EF2をV/I変換器2Aに入力する。The J-bit counter 27 is set to 0, and VR is set.
The EF2 is input to the V / I converter 2A.
【0023】 Jビットカウンタ27のカウントアッ
プおよびKビットカウンタ28のカウントダウンをスタ
ートする。The count-up of the J-bit counter 27 and the count-down of the K-bit counter 28 are started.
【0024】 Jビットカウンタ27のフルカウント
でKビットカウント28のカウントをストップし、この
ときのKビットカウンタ28のカウント値をQとする。When the J-bit counter 27 is fully counted, the K-bit counter 28 stops counting, and the count value of the K-bit counter 28 at this time is set to Q.
【0025】 Lビット比較器29において、Q<M
であれば、VCO2のゲインが小さいので、Nビットカ
ウンタ30を1増し(VCO2のゲインアップ)、に
戻ってそれ以降の動作をくり返し、一方、Q≧Mであれ
ば、VCO2のゲインが適正であるので、較正を終了
し、スイッチ4によってループフィルタ3の出力を選択
する。In the L-bit comparator 29, Q <M
If so, the gain of VCO2 is small, so the N-bit counter 30 is incremented by 1 (gain increase of VCO2), and the operation is repeated after that. On the other hand, if Q ≧ M, the gain of VCO2 is appropriate. Therefore, the calibration is completed, and the output of the loop filter 3 is selected by the switch 4.
【0026】以上のようにして、VCO2のゲインを調
節できるので、PLL回路の製造時のばらつきを補償し
て、PLL回路のゲインを一定にすることができ、十分
な位相余裕が得られる。さらに、PLLループの帯域
(位相伝達特性において0dBとなる周波数幅)を一定
にすることができ、また、FM復調回路にPLL回路を
用いると、復調ゲイン(入力信号の周波数変化に対して
VCOへの制御電圧が変化する割合)が一定になる。Since the gain of the VCO 2 can be adjusted as described above, the gain of the PLL circuit can be made constant by compensating for variations in manufacturing the PLL circuit, and a sufficient phase margin can be obtained. Furthermore, the band of the PLL loop (the frequency width at which the phase transfer characteristic becomes 0 dB) can be made constant, and if a PLL circuit is used for the FM demodulation circuit, the demodulation gain (to the VCO with respect to the frequency change of the input signal, The rate at which the control voltage changes) is constant.
【0027】図4は本発明の他の実施例を示す。図4に
おいて、図1と同一構成については同一符号を付す。図
4に示すように、32は較正回路であって、図1に示す
較正回路5の構成の他に後述のような構成をさらに有
し、D/A変換器34に後述のようなカウンタのカウン
トデータを入力する。FIG. 4 shows another embodiment of the present invention. 4, the same components as those in FIG. 1 are designated by the same reference numerals. As shown in FIG. 4, reference numeral 32 denotes a calibration circuit, which further has a configuration described below in addition to the configuration of the calibration circuit 5 shown in FIG. 1, and the D / A converter 34 includes a counter circuit described below. Enter the count data.
【0028】33はVCOであって、V/I変換器の部
分の構成が後述のように図1のV/I変換器と異なって
おり、他はVCO2と同様である。Reference numeral 33 is a VCO, which is different from the V / I converter shown in FIG. 1 in the structure of the V / I converter portion, which will be described later, and is otherwise similar to the VCO 2.
【0029】図5はVCO33の詳細を示す。33Aは
V/I変換器であって、スイッチ4からの出力信号電圧
を電流に変換する演算増幅器からなる第1変換部35
と、D/A変換器34からの信号電圧を電流に変換する
演算増幅器からなる第2変換部36と、第1,第2変換
部35,36が出力した電流に比例した電流を出力する
2つの電流ミラー部37,38とを有し、2つの電流ミ
ラー部37,38の合計出力電流をゲイン調節部2Cを
介してICO2Bに入力する。FIG. 5 shows the details of the VCO 33. 33A is a V / I converter, which is a first conversion unit 35 including an operational amplifier that converts the output signal voltage from the switch 4 into a current.
And a second converter 36 including an operational amplifier that converts the signal voltage from the D / A converter 34 into a current, and a current that is proportional to the current output by the first and second converters 35, 36. One current mirror section 37, 38 is provided, and the total output current of the two current mirror sections 37, 38 is input to the ICO 2B via the gain adjusting section 2C.
【0030】図6は較正回路32の詳細を示す。制御回
路39はJビットカウンタ27,Kビットカウンタ2
8,Lビット比較器29,Nビットカウンタ30を制御
し、スイッチ4を制御し、入力切換器40を制御してゲ
イン設定値Mおよび自走周波数設定値M′(L≧M′)
のいずれかをLビット比較器29に入力し、さらに、P
ビットカウンタ41を制御する。D/A変換器34はP
ビットカウンタ41のカウント値に応じたアナログ電圧
をV/I変換器33Aの第2変換部36に入力する。他
の動作は図3と同様である。FIG. 6 shows details of the calibration circuit 32. The control circuit 39 uses the J-bit counter 27 and the K-bit counter 2
8, L bit comparator 29, N bit counter 30 are controlled, switch 4 is controlled, input selector 40 is controlled, and gain setting value M and free running frequency setting value M '(L≥M') are controlled.
Is input to the L-bit comparator 29, and P
The bit counter 41 is controlled. The D / A converter 34 is P
The analog voltage corresponding to the count value of the bit counter 41 is input to the second conversion unit 36 of the V / I converter 33A. Other operations are similar to those in FIG.
【0031】以上の構成による図4に示すPLL回路の
較正動作を説明する。The calibration operation of the PLL circuit shown in FIG. 4 having the above configuration will be described.
【0032】(a) ゲイン設定値Mを入力切換器40
によって選択し、Pビットカウンタ41のカウント値を
中央値とし、前記図3の構成の動作の〜を実施す
る。(A) Input the gain setting value M to the input selector 40
And the count value of the P-bit counter 41 is set to the median value, and the operations 1 to 3 of the configuration of FIG. 3 are performed.
【0033】(b) 自走周波数設定値M′を入力切換
器40によって選択し、VREF1をV/I変換器33
Aの第1変換部35に入力し、Pビットカウンタ41の
カウント値を0にする(これによって、第2変換部36
に入力される電圧は最小となる)。(B) The free-running frequency set value M'is selected by the input switch 40, and VREF1 is set to the V / I converter 33.
It is input to the first conversion unit 35 of A and the count value of the P-bit counter 41 is set to 0 (thus, the second conversion unit 36
The voltage input to is the minimum).
【0034】(c) J,Kビットカウンタ27,28
共に0にする。(C) J, K bit counters 27, 28
Set both to 0.
【0035】(d) J,Kビットカウンタ27,28
のカウントアップをスタートする。(D) J, K bit counters 27, 28
Start counting up.
【0036】(e) Jビットカウンタ27のフルカウ
ントでKビットカウンタ28のカウントをストップし、
このときのKビットカウンタ28の値をQ′とする。(E) When the J-bit counter 27 has full count, the K-bit counter 28 stops counting,
The value of the K-bit counter 28 at this time is Q '.
【0037】(f) Lビット比較器29において、
Q′<M′であればPビットカウンタ41を1増し(こ
れによってVCO33の出力周波数が高くなる)、
(c)に戻ってそれ以降の動作をくり返し、一方、Q′
>M′であれば周波数調整を終了し、スイッチ4によっ
てループフィルタ3の出力を選択する。(F) In the L-bit comparator 29,
If Q '<M', the P-bit counter 41 is incremented by 1 (which increases the output frequency of the VCO 33),
Return to (c) and repeat the subsequent operation, while Q '
If> M ', the frequency adjustment is terminated and the output of the loop filter 3 is selected by the switch 4.
【0038】以上のようにして、VCO33のゲインを
調節でき、さらに自走周波数を調節できるので、前記実
施例で得られる効果に加えて、周波数引込み範囲を狭く
でき、PLL回路の動作を一層安定にすることができ
る。As described above, since the gain of the VCO 33 can be adjusted and the free-running frequency can be adjusted, the frequency pull-in range can be narrowed and the operation of the PLL circuit can be further stabilized, in addition to the effect obtained in the above embodiment. Can be
【0039】[0039]
【発明の効果】以上説明したように本発明によれば、P
LL回路のゲインを容易に調節することができるので、
製造時のばらつきを補償でき、したがってループ帯域を
一定にでき、十分な位相余裕を得ることができる。As described above, according to the present invention, P
Since the gain of the LL circuit can be easily adjusted,
It is possible to compensate for variations during manufacturing, and thus to keep the loop band constant and obtain a sufficient phase margin.
【図1】本発明の実施例のブロック図である。FIG. 1 is a block diagram of an embodiment of the present invention.
【図2】同実施例における電圧制御発振器のブロック図
である。FIG. 2 is a block diagram of a voltage controlled oscillator according to the embodiment.
【図3】同較正回路のブロック図である。FIG. 3 is a block diagram of the calibration circuit.
【図4】本発明の他の実施例のブロック図である。FIG. 4 is a block diagram of another embodiment of the present invention.
【図5】同実施例における電圧制御発振器のブロック図
である。FIG. 5 is a block diagram of a voltage controlled oscillator according to the embodiment.
【図6】同較正回路のブロック図である。FIG. 6 is a block diagram of the calibration circuit.
【図7】従来のPLL回路のブロック図である。FIG. 7 is a block diagram of a conventional PLL circuit.
【図8】同PLL回路のゲイン・位相特性を示す図であ
る。FIG. 8 is a diagram showing a gain / phase characteristic of the PLL circuit.
【図9】PLL回路の位相伝達特性を示す図である。FIG. 9 is a diagram showing a phase transfer characteristic of a PLL circuit.
1 位相比較器 2 電圧制御発振器 3 ループフィルタ 4 スイッチ 5 較正回路 1 phase comparator 2 voltage controlled oscillator 3 loop filter 4 switch 5 calibration circuit
Claims (2)
記電圧制御発振器の出力信号の位相とを比較する位相比
較器と、該位相比較器の出力信号を入力して前記電圧制
御発振器へ制御電圧を出力するループフィルタとから構
成されるPLL回路において、 前記電圧制御発振器は、前記ループフィルタの出力電圧
を電流に変換する電圧−電流変換器と、前記位相比較器
に前記出力信号を与える電流制御発振器と、前記電圧−
電流変換器から前記電流制御発振器に供給する電流を調
節するゲイン調節器とを有することを特徴とするPLL
回路。1. A voltage controlled oscillator, a phase comparator for comparing a phase of an input signal with a phase of an output signal of the voltage controlled oscillator, and an output signal of the phase comparator for inputting control to the voltage controlled oscillator. In a PLL circuit including a loop filter that outputs a voltage, the voltage-controlled oscillator includes a voltage-current converter that converts an output voltage of the loop filter into a current, and a current that gives the output signal to the phase comparator. Controlled oscillator and the voltage-
And a gain adjuster for adjusting the current supplied from the current converter to the current controlled oscillator.
circuit.
2つの基準電圧を選択的に与えるスイッチと、前記2つ
の電圧に基づく前記電圧制御発振器の2つの出力周波数
の差が所定値になるように前記ゲイン調節器を制御する
較正回路とを有することを特徴とする請求項1に記載の
PLL回路。2. A switch for selectively supplying two different reference voltages to the voltage-current converter, and a difference between two output frequencies of the voltage controlled oscillator based on the two voltages is set to a predetermined value. The PLL circuit according to claim 1, further comprising: a calibration circuit that controls the gain adjuster.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30222692A JP3177025B2 (en) | 1992-11-12 | 1992-11-12 | PLL circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30222692A JP3177025B2 (en) | 1992-11-12 | 1992-11-12 | PLL circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06152401A true JPH06152401A (en) | 1994-05-31 |
JP3177025B2 JP3177025B2 (en) | 2001-06-18 |
Family
ID=17906468
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---|---|---|---|
JP30222692A Expired - Lifetime JP3177025B2 (en) | 1992-11-12 | 1992-11-12 | PLL circuit |
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JP (1) | JP3177025B2 (en) |
Cited By (6)
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---|---|---|---|---|
US6150887A (en) * | 1996-09-10 | 2000-11-21 | Nec Corporation | PLL Circuit in which output oscillation signal frequency can be controlled based on bias signal |
US6225868B1 (en) | 1997-12-03 | 2001-05-01 | Nec Corporation | Voltage controlled oscillation circuit with plural voltage controlled current generating circuits |
US7203149B1 (en) | 1999-11-15 | 2007-04-10 | Nec Electronics Corporation | PLL circuit and data read-out circuit |
US7504894B2 (en) | 2005-08-08 | 2009-03-17 | Renesas Technology Corp. | Phase locked loop circuit and semiconductor integrated circuit device using the same |
JP2010288255A (en) * | 2009-05-14 | 2010-12-24 | Nippon Telegr & Teleph Corp <Ntt> | Clock data reproducing circuit |
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-
1992
- 1992-11-12 JP JP30222692A patent/JP3177025B2/en not_active Expired - Lifetime
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6150887A (en) * | 1996-09-10 | 2000-11-21 | Nec Corporation | PLL Circuit in which output oscillation signal frequency can be controlled based on bias signal |
US6225868B1 (en) | 1997-12-03 | 2001-05-01 | Nec Corporation | Voltage controlled oscillation circuit with plural voltage controlled current generating circuits |
US7203149B1 (en) | 1999-11-15 | 2007-04-10 | Nec Electronics Corporation | PLL circuit and data read-out circuit |
US7504894B2 (en) | 2005-08-08 | 2009-03-17 | Renesas Technology Corp. | Phase locked loop circuit and semiconductor integrated circuit device using the same |
US7737792B2 (en) | 2005-08-08 | 2010-06-15 | Renesas Technology Corp. | Phase Locked loop circuit and semiconductor integrated circuit device using the same |
US7876163B2 (en) | 2007-08-06 | 2011-01-25 | Renesas Electronics Corporation | Voltage-controlled oscillator circuit and phase locked loop circuit using the same |
KR101026654B1 (en) * | 2007-08-06 | 2011-04-04 | 르네사스 일렉트로닉스 가부시키가이샤 | Voltage-controlled oscillator circuit and phase locked loop circuit using the same |
JP2010288255A (en) * | 2009-05-14 | 2010-12-24 | Nippon Telegr & Teleph Corp <Ntt> | Clock data reproducing circuit |
JP2010288256A (en) * | 2009-05-14 | 2010-12-24 | Nippon Telegr & Teleph Corp <Ntt> | Clock data reproducing circuit |
JP2010288257A (en) * | 2009-05-14 | 2010-12-24 | Nippon Telegr & Teleph Corp <Ntt> | Clock data reproducing circuit |
JP2013034267A (en) * | 2009-05-14 | 2013-02-14 | Nippon Telegr & Teleph Corp <Ntt> | Clock-data regeneration circuit |
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