JPH06152401A - Pll circuit - Google Patents
Pll circuitInfo
- Publication number
- JPH06152401A JPH06152401A JP4302226A JP30222692A JPH06152401A JP H06152401 A JPH06152401 A JP H06152401A JP 4302226 A JP4302226 A JP 4302226A JP 30222692 A JP30222692 A JP 30222692A JP H06152401 A JPH06152401 A JP H06152401A
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- Prior art keywords
- voltage
- gain
- current
- converter
- controlled oscillator
- Prior art date
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＰＬＬ回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit.
【０００２】[0002]
【従来の技術】図７に従来のＰＬＬ回路の構成を示す。
入力信号の位相と電圧制御発振器（以下“ＶＣＯ”とい
う）１０３の出力信号の位相とを位相比較器１０１で比
較し、その位相差に相当する信号がループフィルタ１０
２を介して制御信号としてＶＣＯ１０３に入力される。
したがって、ＶＣＯ１０３の出力信号ｂは、入力信号と
位相が一致する方向に制御され、入力信号にロックされ
る。ＶＣＯ１０３は、入力信号の電圧値（Ｖ）を電流値
（Ｉ）に変換するＶ／Ｉ変換器１０３Ａと、このＶ／Ｉ
変換器１０３Ａの出力に応じた周波数の信号を発振し、
出力する電流制御発振器（以下“ＩＣＯ”という）１０
３Ｂとから構成される。また、ループフィルタ１０２に
は、ＰＬＬ回路の安定性の点から、ラグ・リード・フィ
ルタがしばしば用いられる。2. Description of the Related Art FIG. 7 shows the configuration of a conventional PLL circuit.
The phase comparator 101 compares the phase of the input signal with the phase of the output signal of the voltage controlled oscillator (hereinafter referred to as “VCO”) 103, and the signal corresponding to the phase difference is detected by the loop filter 10
It is input to the VCO 103 via 2 as a control signal.
Therefore, the output signal b of the VCO 103 is controlled so as to be in phase with the input signal and locked to the input signal. The VCO 103 includes a V / I converter 103A that converts a voltage value (V) of an input signal into a current value (I), and the V / I converter 103A.
Oscillates a signal with a frequency corresponding to the output of the converter 103A,
Output current controlled oscillator (hereinafter referred to as "ICO") 10
3B and 3B. A lag lead filter is often used as the loop filter 102 from the viewpoint of the stability of the PLL circuit.
【０００３】[0003]
【発明が解決しようとする課題】図８にループフィルタ
にラグ・リード・フィルタを用いた従来のＰＬＬ回路の
ゲインおよび位相特性を示す。図８から、高い周波数で
は回路の時間遅れ等の影響で急激なゲインの減少および
位相変化が生じることがわかる。FIG. 8 shows gain and phase characteristics of a conventional PLL circuit using a lag lead filter as a loop filter. It can be seen from FIG. 8 that at a high frequency, the gain is rapidly reduced and the phase is changed due to the influence of the time delay of the circuit.
【０００４】ＰＬＬ回路として、高い安定性を得るため
には、十分な位相余裕がある状態でゲインが１となるこ
とが望ましい（図８では周波数ａでこの条件が満たされ
ている）。In order to obtain high stability as a PLL circuit, it is desirable that the gain be 1 with a sufficient phase margin (this condition is satisfied at the frequency a in FIG. 8).
【０００５】しかしながら、実際にはこのようなＰＬＬ
回路のＩＣ化の際のばらつきによって、ＶＣＯのゲイン
が変化する。このためＰＬＬ回路のゲインが１となる周
波数が例えばａの前後に変化し、位相余裕が減少してし
まう。その結果、ＰＬＬ回路の位相伝達特性が変化し
（ピーキングが生じる）、最悪の場合には発振状態とな
り、動作しなくなってしまう。すなわち、ＰＬＬ回路の
位相伝達特性とは、入力信号に一定のジッター（ノイ
ズ）を重複し、これがどれだけ出力に現われるかを表わ
したもの（出力ジッター／入力ジッター）であり、図９
にその例を示す。図９において、ゲインが０ｄＢの箇所
は入力と同じレベルで出力にジッターが現われているこ
とを示しており、ｂは、ＰＬＬ回路のゲインが大きくな
り位相余裕が減少したときの特性を示し、ｃはＰＬＬ回
路のゲインが小さくなり位相余裕が減少したときの特性
を示し、ｄは位相余裕が十分あるときの特性を示してい
る。このように、位相余裕が減少することによって、位
相伝達特性にピーキング（ジッターが増幅されている）
が生じ、同期状態でＰＬＬ回路の周波数、位相精度が悪
化してしまう。However, such a PLL is actually used.
The gain of the VCO changes due to variations in the circuit when integrated into an IC. Therefore, the frequency at which the gain of the PLL circuit becomes 1 changes before and after a, for example, and the phase margin decreases. As a result, the phase transfer characteristic of the PLL circuit changes (peaking occurs), and in the worst case, it becomes an oscillating state and stops operating. That is, the phase transfer characteristic of the PLL circuit represents how much a certain jitter (noise) is overlapped with the input signal and appears in the output (output jitter / input jitter).
An example is shown in. In FIG. 9, the portion where the gain is 0 dB shows that the jitter appears in the output at the same level as the input, b shows the characteristic when the gain of the PLL circuit increases and the phase margin decreases, and c Shows the characteristic when the gain of the PLL circuit becomes small and the phase margin decreases, and d shows the characteristic when the phase margin is sufficient. In this way, the phase margin is reduced, and thus the peaking of the phase transfer characteristic (jitter is amplified).
Occurs, the frequency and phase accuracy of the PLL circuit deteriorates in the synchronized state.
【０００６】そこで本発明の目的は以上のような問題を
解消したＰＬＬ回路を提供することにある。Therefore, an object of the present invention is to provide a PLL circuit which solves the above problems.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
本発明は電圧制御発振器と、入力信号の位相と前記電圧
制御発振器の出力信号の位相とを比較する位相比較器
と、該位相比較器の出力信号を入力して前記電圧制御発
振器へ制御電圧を出力するループフィルタとから構成さ
れるＰＬＬ回路において、前記電圧制御発振器は、前記
ループフィルタの出力電圧を電流に変換する電圧−電流
変換器と、前記位相比較器に前記出力信号を与える電流
制御発振器と、前記電圧−電流変換器から前記電流制御
発振器に供給する電流を調節するゲイン調節器とを有す
ることを特徴とする。To achieve the above object, the present invention provides a voltage controlled oscillator, a phase comparator for comparing the phase of an input signal with the phase of an output signal of the voltage controlled oscillator, and the phase comparator. Of a loop filter for inputting the output signal of the above and outputting a control voltage to the voltage controlled oscillator, the voltage controlled oscillator is a voltage-current converter for converting the output voltage of the loop filter into a current. And a current control oscillator that gives the output signal to the phase comparator, and a gain adjuster that adjusts the current supplied from the voltage-current converter to the current control oscillator.
【０００８】[0008]
【作用】本発明によれば、ＶＣＯのゲインを調節するこ
とによって、製造時のばらつきが補償され、ループ帯域
が一定になる。According to the present invention, by adjusting the gain of the VCO, variations in manufacturing are compensated and the loop band becomes constant.
【０００９】[0009]
【実施例】以下、図面を参照して本発明の実施例を詳細
に説明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【００１０】図１は本発明の実施例を示す。図１に示す
ように、位相比較器１は入力信号の位相とＶＣＯ２の出
力信号の位相とを比較して、その位相差に相当する信号
をループフィルタ３に入力する。４は３入力１出力型の
スイッチであって、ループフィルタ３からの出力信号、
および互いに異なった値の２つの基準電圧（ＶＲＥＦ
１，ＶＲＥＦ２）を入力し、較正回路５からの制御信号
に基づいて３入力のいずれか１つを選択し出力する。FIG. 1 shows an embodiment of the present invention. As shown in FIG. 1, the phase comparator 1 compares the phase of the input signal with the phase of the output signal of the VCO 2, and inputs a signal corresponding to the phase difference to the loop filter 3. Reference numeral 4 denotes a 3-input 1-output type switch, which is an output signal from the loop filter 3,
And two reference voltages (VREF with different values
1, VREF2) is input, and one of the three inputs is selected and output based on the control signal from the calibration circuit 5.
【００１１】ＶＣＯ２は、Ｖ／Ｉ変換器２Ａと、ＩＣＯ
２Ｂと、ゲイン調節器２Ｃとを有する。Ｖ／Ｉ変換器２
Ａはスイッチ４からの出力信号を入力し、Ｖ／Ｉ変換し
て、ゲイン調節器２Ｃに入力する。ゲイン調節器２Ｃは
較正回路５からの信号（詳細は後述する）に基づいてＶ
／Ｉ変換器２ＡからＩＣＯ２Ｂに流れる電流の値を調節
する。The VCO 2 includes a V / I converter 2A and an ICO.
2B and a gain adjuster 2C. V / I converter 2
A inputs the output signal from the switch 4, V / I converts it, and inputs it to the gain controller 2C. The gain adjuster 2C receives V from the signal from the calibration circuit 5 (details will be described later).
The value of the current flowing from the / I converter 2A to the ICO 2B is adjusted.
【００１２】図２はＶＣＯ２の詳細を示す。Ｖ／Ｉ変換
器２Ａは演算増幅器６によってスイッチ４からの信号電
圧を電圧に変換して、トランジスタ７，８を介して出力
する。ゲイン調節器２Ｃは、複数のトランジスタ９〜１
２と各トランジスタ９〜１２に直列接続したスイッチ１
３〜１６とを並列接続し、各トランジスタ９〜１２のゲ
ートにＶ／Ｉ変換器２Ａからの出力電流を共通に入力
し、較正回路５からの信号に基づいて各スイッチ１３〜
１６を閉じ、閉じたスイッチ数が増加する毎にＶ／Ｉ変
換器２ＡからＩＣＯ２Ｂに流れる電流値を増加させる。
例えば閉じたスイッチ数が１つではＶＣＯ２のゲインは
最小となり、閉じたスイッチ数が増加する毎にＶＣＯ２
のゲインは増加する。ＩＣＯ２Ｂは、２つのコンデンサ
１７，１８を有し、ゲイン調節器２Ｃからの電流の値に
応じてこれらのコンデンサ１７，１８への充電時間が変
化し、出力信号の周波数が変化する。すなわち、今、Ｉ
ＣＯ２Ｂの出力ＡがＬｏｗからＨｉｇｈに変化した場合
を考えると、フリップフロップ１９の出力Ｂは、Ｈｉｇ
ｈからＬｏｗになり、Ｐ ＭＯＳ ＦＥＴ ２０はオン
し、Ｎ ＭＯＳ ＦＥＴ ２１はオフになり、両ＦＥＴ
２０，２１のソース・ドレンの接続点（Ｇ）に接続した
コンデンサ１８は前記ゲイン調節器２Ｃからの電流に比
例した速度で充電を始める。この時、２つのＦＥＴ２
２，２３のソース・ドレインの接続点（Ｆ）に接続した
コンデンサ１７は放電する。FIG. 2 shows details of the VCO2. The V / I converter 2A converts the signal voltage from the switch 4 into a voltage by the operational amplifier 6 and outputs the voltage via the transistors 7 and 8. The gain adjuster 2C includes a plurality of transistors 9 to 1
2 and switch 1 connected in series with each transistor 9-12
3 to 16 are connected in parallel, the output current from the V / I converter 2A is commonly input to the gates of the transistors 9 to 12, and the switches 13 to 13 are connected based on the signal from the calibration circuit 5.
16 is closed, and the current value flowing from the V / I converter 2A to the ICO 2B is increased each time the number of closed switches is increased.
For example, if the number of closed switches is one, the gain of VCO2 becomes the minimum, and as the number of closed switches increases, VCO2
Gain increases. The ICO 2B has two capacitors 17 and 18, the charging time of these capacitors 17 and 18 changes according to the value of the current from the gain adjuster 2C, and the frequency of the output signal changes. That is, now I
Considering the case where the output A of CO2B changes from Low to High, the output B of the flip-flop 19 is High.
From h to Low, P MOS FET 20 turns on, N MOS FET 21 turns off, both FETs
The capacitor 18 connected to the connection point (G) between the source and drain of 20 and 21 starts charging at a rate proportional to the current from the gain adjuster 2C. At this time, two FET2
The capacitor 17 connected to the connection point (F) between the source and drain 2 and 23 is discharged.
【００１３】コンデンサ１８の充電電圧が基準電位Ｖａ
を越えると、コンパレータ２４はＨｉｇｈになり、その
出力Ｅはオアゲート２５（出力Ｃ）を介してフリップフ
ロップ１９のクロック入力端に入力し、その出力Ａが反
転しＨｉｇｈからＬｏｗになる。このとき、Ｐ ＭＯＳ
ＦＥＴ ２０はオフし、Ｎ ＭＯＳ ＦＥＴ ２１は
オンし、コンデンサ１８は放電され、コンパレータ２６
（出力Ｄ）の＋入力端に接続のコンデンサ１７がゲイン
調節器２Ｃからの電流に比例した速度で充電を開始す
る。The charging voltage of the capacitor 18 is the reference potential Va.
After that, the comparator 24 becomes High, its output E is input to the clock input terminal of the flip-flop 19 via the OR gate 25 (output C), and its output A is inverted and becomes High to Low. At this time, the PMOS
The FET 20 is turned off, the NMOS FET 21 is turned on, the capacitor 18 is discharged, and the comparator 26
The capacitor 17 connected to the + input terminal of (output D) starts charging at a rate proportional to the current from the gain adjuster 2C.
【００１４】以上のようにして、ゲイン調節器２Ｃから
の電流に対応して、コンデンサ１７，１８の充電時間が
変化してＩＣＯ２Ｂ（ＶＣＯ２）の出力信号の周波数が
変化する。As described above, the charging time of the capacitors 17 and 18 changes according to the current from the gain adjuster 2C, and the frequency of the output signal of the ICO 2B (VCO2) changes.
【００１５】図３は較正回路５の詳細を示す。２７，２
８は各々Ｊビット，Ｋビットカウンタ、２９はＬビット
比較器（Ｋ＞Ｌ）、３０はＮビットカウンタ（Ｎはゲイ
ン調節器２Ｃのトランジスタの数と同じ）である。３１
は制御回路であって、前記各カウンタ２７，２８，３０
およびＬビット比較器２９を制御し、かつ、スイッチ４
を制御して、３入力のうちの１つを選択させる。FIG. 3 shows details of the calibration circuit 5. 27,2
Reference numeral 8 is a J-bit / K-bit counter, 29 is an L-bit comparator (K> L), and 30 is an N-bit counter (N is the same as the number of transistors of the gain adjuster 2C). 31
Is a control circuit, and each of the counters 27, 28, 30
And L-bit comparator 29 and switch 4
Control to select one of the three inputs.
【００１６】Ｊビットカウンタ２７は任意の周波数のパ
ルス信号ｆａをカウントし、Ｋビットカウンタ２８はＩ
ＣＯ２Ｂの出力信号をカウントし、Ｌビット比較器２９
はＫビットカウンタ２８の下位Ｌビットの値とゲイン設
定値Ｍ（Ｍ≦Ｌ）とを比較し、比較結果を制御回路３１
に入力する。Ｎビットカウンタ２３０は制御回路３１に
よって設定されたビット数だけゲイン調節器２Ｃのスイ
ッチをオンする。The J-bit counter 27 counts the pulse signal fa having an arbitrary frequency, and the K-bit counter 28 counts I.
The output signal of CO2B is counted, and the L-bit comparator 29
Compares the value of the lower L bits of the K-bit counter 28 with the gain setting value M (M ≦ L), and outputs the comparison result to the control circuit 31.
To enter. The N-bit counter 230 turns on the switch of the gain adjuster 2C by the number of bits set by the control circuit 31.
【００１７】以上の構成によるＰＬＬ回路の較正動作を
説明する。なお、ここでスイッチ４に入力するＶＲＥＦ
１，ＶＲＥＦ２は、ＶＲＥＦ１＝ＶＲＥＦ２＋１Ｖとす
る。A calibration operation of the PLL circuit having the above configuration will be described. In addition, VREF input to the switch 4 here
1 and VREF2 are set to VREF1 = VREF2 + 1V.
【００１８】 まず、Ｎビットカウンタ３０をＮ＝１
とする（ＶＣＯ２のゲインは最小）。First, the N-bit counter 30 is set to N = 1.
(The gain of VCO2 is the minimum).
【００１９】 ＶＲＥＦ１をＶ／Ｉ変換器２Ａに入力
すると共に、Ｊ，Ｋビットカウンタ２７，２８をリセッ
トする（０にする）。VREF1 is input to the V / I converter 2A, and the J and K bit counters 27 and 28 are reset (set to 0).
【００２０】 Ｊ，Ｋビットカウンタ２７，２８のカ
ウントアップをスタートする。The counting up of the J, K bit counters 27, 28 is started.
【００２１】 Ｊビットカウンタ２７のフルカウント
でＫビットカウンタ２８のカウントをストップする。When the J-bit counter 27 is fully counted, the K-bit counter 28 stops counting.
【００２２】 Ｊビットカウンタ２７を０にし、ＶＲ
ＥＦ２をＶ／Ｉ変換器２Ａに入力する。The J-bit counter 27 is set to 0, and VR is set.
The EF2 is input to the V / I converter 2A.
【００２３】 Ｊビットカウンタ２７のカウントアッ
プおよびＫビットカウンタ２８のカウントダウンをスタ
ートする。The count-up of the J-bit counter 27 and the count-down of the K-bit counter 28 are started.
【００２４】 Ｊビットカウンタ２７のフルカウント
でＫビットカウント２８のカウントをストップし、この
ときのＫビットカウンタ２８のカウント値をＱとする。When the J-bit counter 27 is fully counted, the K-bit counter 28 stops counting, and the count value of the K-bit counter 28 at this time is set to Q.
【００２５】 Ｌビット比較器２９において、Ｑ＜Ｍ
であれば、ＶＣＯ２のゲインが小さいので、Ｎビットカ
ウンタ３０を１増し（ＶＣＯ２のゲインアップ）、に
戻ってそれ以降の動作をくり返し、一方、Ｑ≧Ｍであれ
ば、ＶＣＯ２のゲインが適正であるので、較正を終了
し、スイッチ４によってループフィルタ３の出力を選択
する。In the L-bit comparator 29, Q <M
If so, the gain of VCO2 is small, so the N-bit counter 30 is incremented by 1 (gain increase of VCO2), and the operation is repeated after that. On the other hand, if Q ≧ M, the gain of VCO2 is appropriate. Therefore, the calibration is completed, and the output of the loop filter 3 is selected by the switch 4.
【００２６】以上のようにして、ＶＣＯ２のゲインを調
節できるので、ＰＬＬ回路の製造時のばらつきを補償し
て、ＰＬＬ回路のゲインを一定にすることができ、十分
な位相余裕が得られる。さらに、ＰＬＬループの帯域
（位相伝達特性において０ｄＢとなる周波数幅）を一定
にすることができ、また、ＦＭ復調回路にＰＬＬ回路を
用いると、復調ゲイン（入力信号の周波数変化に対して
ＶＣＯへの制御電圧が変化する割合）が一定になる。Since the gain of the VCO 2 can be adjusted as described above, the gain of the PLL circuit can be made constant by compensating for variations in manufacturing the PLL circuit, and a sufficient phase margin can be obtained. Furthermore, the band of the PLL loop (the frequency width at which the phase transfer characteristic becomes 0 dB) can be made constant, and if a PLL circuit is used for the FM demodulation circuit, the demodulation gain (to the VCO with respect to the frequency change of the input signal, The rate at which the control voltage changes) is constant.
【００２７】図４は本発明の他の実施例を示す。図４に
おいて、図１と同一構成については同一符号を付す。図
４に示すように、３２は較正回路であって、図１に示す
較正回路５の構成の他に後述のような構成をさらに有
し、Ｄ／Ａ変換器３４に後述のようなカウンタのカウン
トデータを入力する。FIG. 4 shows another embodiment of the present invention. 4, the same components as those in FIG. 1 are designated by the same reference numerals. As shown in FIG. 4, reference numeral 32 denotes a calibration circuit, which further has a configuration described below in addition to the configuration of the calibration circuit 5 shown in FIG. 1, and the D / A converter 34 includes a counter circuit described below. Enter the count data.
【００２８】３３はＶＣＯであって、Ｖ／Ｉ変換器の部
分の構成が後述のように図１のＶ／Ｉ変換器と異なって
おり、他はＶＣＯ２と同様である。Reference numeral 33 is a VCO, which is different from the V / I converter shown in FIG. 1 in the structure of the V / I converter portion, which will be described later, and is otherwise similar to the VCO 2.
【００２９】図５はＶＣＯ３３の詳細を示す。３３Ａは
Ｖ／Ｉ変換器であって、スイッチ４からの出力信号電圧
を電流に変換する演算増幅器からなる第１変換部３５
と、Ｄ／Ａ変換器３４からの信号電圧を電流に変換する
演算増幅器からなる第２変換部３６と、第１，第２変換
部３５，３６が出力した電流に比例した電流を出力する
２つの電流ミラー部３７，３８とを有し、２つの電流ミ
ラー部３７，３８の合計出力電流をゲイン調節部２Ｃを
介してＩＣＯ２Ｂに入力する。FIG. 5 shows the details of the VCO 33. 33A is a V / I converter, which is a first conversion unit 35 including an operational amplifier that converts the output signal voltage from the switch 4 into a current.
And a second converter 36 including an operational amplifier that converts the signal voltage from the D / A converter 34 into a current, and a current that is proportional to the current output by the first and second converters 35, 36. One current mirror section 37, 38 is provided, and the total output current of the two current mirror sections 37, 38 is input to the ICO 2B via the gain adjusting section 2C.
【００３０】図６は較正回路３２の詳細を示す。制御回
路３９はＪビットカウンタ２７，Ｋビットカウンタ２
８，Ｌビット比較器２９，Ｎビットカウンタ３０を制御
し、スイッチ４を制御し、入力切換器４０を制御してゲ
イン設定値Ｍおよび自走周波数設定値Ｍ′（Ｌ≧Ｍ′）
のいずれかをＬビット比較器２９に入力し、さらに、Ｐ
ビットカウンタ４１を制御する。Ｄ／Ａ変換器３４はＰ
ビットカウンタ４１のカウント値に応じたアナログ電圧
をＶ／Ｉ変換器３３Ａの第２変換部３６に入力する。他
の動作は図３と同様である。FIG. 6 shows details of the calibration circuit 32. The control circuit 39 uses the J-bit counter 27 and the K-bit counter 2
8, L bit comparator 29, N bit counter 30 are controlled, switch 4 is controlled, input selector 40 is controlled, and gain setting value M and free running frequency setting value M '(L≥M') are controlled.
Is input to the L-bit comparator 29, and P
The bit counter 41 is controlled. The D / A converter 34 is P
The analog voltage corresponding to the count value of the bit counter 41 is input to the second conversion unit 36 of the V / I converter 33A. Other operations are similar to those in FIG.
【００３１】以上の構成による図４に示すＰＬＬ回路の
較正動作を説明する。The calibration operation of the PLL circuit shown in FIG. 4 having the above configuration will be described.
【００３２】（ａ） ゲイン設定値Ｍを入力切換器４０
によって選択し、Ｐビットカウンタ４１のカウント値を
中央値とし、前記図３の構成の動作の〜を実施す
る。(A) Input the gain setting value M to the input selector 40
And the count value of the P-bit counter 41 is set to the median value, and the operations 1 to 3 of the configuration of FIG. 3 are performed.
【００３３】（ｂ） 自走周波数設定値Ｍ′を入力切換
器４０によって選択し、ＶＲＥＦ１をＶ／Ｉ変換器３３
Ａの第１変換部３５に入力し、Ｐビットカウンタ４１の
カウント値を０にする（これによって、第２変換部３６
に入力される電圧は最小となる）。(B) The free-running frequency set value M'is selected by the input switch 40, and VREF1 is set to the V / I converter 33.
It is input to the first conversion unit 35 of A and the count value of the P-bit counter 41 is set to 0 (thus, the second conversion unit 36
The voltage input to is the minimum).
【００３４】（ｃ） Ｊ，Ｋビットカウンタ２７，２８
共に０にする。(C) J, K bit counters 27, 28
Set both to 0.
【００３５】（ｄ） Ｊ，Ｋビットカウンタ２７，２８
のカウントアップをスタートする。(D) J, K bit counters 27, 28
Start counting up.
【００３６】（ｅ） Ｊビットカウンタ２７のフルカウ
ントでＫビットカウンタ２８のカウントをストップし、
このときのＫビットカウンタ２８の値をＱ′とする。(E) When the J-bit counter 27 has full count, the K-bit counter 28 stops counting,
The value of the K-bit counter 28 at this time is Q '.
【００３７】（ｆ） Ｌビット比較器２９において、
Ｑ′＜Ｍ′であればＰビットカウンタ４１を１増し（こ
れによってＶＣＯ３３の出力周波数が高くなる）、
（ｃ）に戻ってそれ以降の動作をくり返し、一方、Ｑ′
＞Ｍ′であれば周波数調整を終了し、スイッチ４によっ
てループフィルタ３の出力を選択する。(F) In the L-bit comparator 29,
If Q '<M', the P-bit counter 41 is incremented by 1 (which increases the output frequency of the VCO 33),
Return to (c) and repeat the subsequent operation, while Q '
If> M ', the frequency adjustment is terminated and the output of the loop filter 3 is selected by the switch 4.
【００３８】以上のようにして、ＶＣＯ３３のゲインを
調節でき、さらに自走周波数を調節できるので、前記実
施例で得られる効果に加えて、周波数引込み範囲を狭く
でき、ＰＬＬ回路の動作を一層安定にすることができ
る。As described above, since the gain of the VCO 33 can be adjusted and the free-running frequency can be adjusted, the frequency pull-in range can be narrowed and the operation of the PLL circuit can be further stabilized, in addition to the effect obtained in the above embodiment. Can be
【００３９】[0039]
【発明の効果】以上説明したように本発明によれば、Ｐ
ＬＬ回路のゲインを容易に調節することができるので、
製造時のばらつきを補償でき、したがってループ帯域を
一定にでき、十分な位相余裕を得ることができる。As described above, according to the present invention, P
Since the gain of the LL circuit can be easily adjusted,
It is possible to compensate for variations during manufacturing, and thus to keep the loop band constant and obtain a sufficient phase margin.
【図１】本発明の実施例のブロック図である。FIG. 1 is a block diagram of an embodiment of the present invention.
【図２】同実施例における電圧制御発振器のブロック図
である。FIG. 2 is a block diagram of a voltage controlled oscillator according to the embodiment.
【図３】同較正回路のブロック図である。FIG. 3 is a block diagram of the calibration circuit.
【図４】本発明の他の実施例のブロック図である。FIG. 4 is a block diagram of another embodiment of the present invention.
【図５】同実施例における電圧制御発振器のブロック図
である。FIG. 5 is a block diagram of a voltage controlled oscillator according to the embodiment.
【図６】同較正回路のブロック図である。FIG. 6 is a block diagram of the calibration circuit.
【図７】従来のＰＬＬ回路のブロック図である。FIG. 7 is a block diagram of a conventional PLL circuit.
【図８】同ＰＬＬ回路のゲイン・位相特性を示す図であ
る。FIG. 8 is a diagram showing a gain / phase characteristic of the PLL circuit.
【図９】ＰＬＬ回路の位相伝達特性を示す図である。FIG. 9 is a diagram showing a phase transfer characteristic of a PLL circuit.
１ 位相比較器 ２ 電圧制御発振器 ３ ループフィルタ ４ スイッチ ５ 較正回路 1 phase comparator 2 voltage controlled oscillator 3 loop filter 4 switch 5 calibration circuit
Claims (2)
記電圧制御発振器の出力信号の位相とを比較する位相比
較器と、該位相比較器の出力信号を入力して前記電圧制
御発振器へ制御電圧を出力するループフィルタとから構
成されるＰＬＬ回路において、 前記電圧制御発振器は、前記ループフィルタの出力電圧
を電流に変換する電圧−電流変換器と、前記位相比較器
に前記出力信号を与える電流制御発振器と、前記電圧−
電流変換器から前記電流制御発振器に供給する電流を調
節するゲイン調節器とを有することを特徴とするＰＬＬ
回路。1. A voltage controlled oscillator, a phase comparator for comparing a phase of an input signal with a phase of an output signal of the voltage controlled oscillator, and an output signal of the phase comparator for inputting control to the voltage controlled oscillator. In a PLL circuit including a loop filter that outputs a voltage, the voltage-controlled oscillator includes a voltage-current converter that converts an output voltage of the loop filter into a current, and a current that gives the output signal to the phase comparator. Controlled oscillator and the voltage-
And a gain adjuster for adjusting the current supplied from the current converter to the current controlled oscillator.
circuit.
２つの基準電圧を選択的に与えるスイッチと、前記２つ
の電圧に基づく前記電圧制御発振器の２つの出力周波数
の差が所定値になるように前記ゲイン調節器を制御する
較正回路とを有することを特徴とする請求項１に記載の
ＰＬＬ回路。2. A switch for selectively supplying two different reference voltages to the voltage-current converter, and a difference between two output frequencies of the voltage controlled oscillator based on the two voltages is set to a predetermined value. The PLL circuit according to claim 1, further comprising: a calibration circuit that controls the gain adjuster.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30222692A JP3177025B2 (en) | 1992-11-12 | 1992-11-12 | PLL circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30222692A JP3177025B2 (en) | 1992-11-12 | 1992-11-12 | PLL circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06152401A true JPH06152401A (en) | 1994-05-31 |
| JP3177025B2 JP3177025B2 (en) | 2001-06-18 |
Family
ID=17906468
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30222692A Expired - Lifetime JP3177025B2 (en) | 1992-11-12 | 1992-11-12 | PLL circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3177025B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6150887A (en) * | 1996-09-10 | 2000-11-21 | Nec Corporation | PLL Circuit in which output oscillation signal frequency can be controlled based on bias signal |
| US6225868B1 (en) | 1997-12-03 | 2001-05-01 | Nec Corporation | Voltage controlled oscillation circuit with plural voltage controlled current generating circuits |
| US7203149B1 (en) | 1999-11-15 | 2007-04-10 | Nec Electronics Corporation | PLL circuit and data read-out circuit |
| US7504894B2 (en) | 2005-08-08 | 2009-03-17 | Renesas Technology Corp. | Phase locked loop circuit and semiconductor integrated circuit device using the same |
| JP2010288255A (en) * | 2009-05-14 | 2010-12-24 | Nippon Telegr & Teleph Corp <Ntt> | Clock data reproducing circuit |
| US7876163B2 (en) | 2007-08-06 | 2011-01-25 | Renesas Electronics Corporation | Voltage-controlled oscillator circuit and phase locked loop circuit using the same |
-
1992
- 1992-11-12 JP JP30222692A patent/JP3177025B2/en not_active Expired - Lifetime
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6150887A (en) * | 1996-09-10 | 2000-11-21 | Nec Corporation | PLL Circuit in which output oscillation signal frequency can be controlled based on bias signal |
| US6225868B1 (en) | 1997-12-03 | 2001-05-01 | Nec Corporation | Voltage controlled oscillation circuit with plural voltage controlled current generating circuits |
| US7203149B1 (en) | 1999-11-15 | 2007-04-10 | Nec Electronics Corporation | PLL circuit and data read-out circuit |
| US7504894B2 (en) | 2005-08-08 | 2009-03-17 | Renesas Technology Corp. | Phase locked loop circuit and semiconductor integrated circuit device using the same |
| US7737792B2 (en) | 2005-08-08 | 2010-06-15 | Renesas Technology Corp. | Phase Locked loop circuit and semiconductor integrated circuit device using the same |
| US7876163B2 (en) | 2007-08-06 | 2011-01-25 | Renesas Electronics Corporation | Voltage-controlled oscillator circuit and phase locked loop circuit using the same |
| KR101026654B1 (en) * | 2007-08-06 | 2011-04-04 | 르네사스 일렉트로닉스 가부시키가이샤 | Voltage-controlled oscillator circuit and phase locked loop circuit using the same |
| JP2010288255A (en) * | 2009-05-14 | 2010-12-24 | Nippon Telegr & Teleph Corp <Ntt> | Clock data reproducing circuit |
| JP2010288256A (en) * | 2009-05-14 | 2010-12-24 | Nippon Telegr & Teleph Corp <Ntt> | Clock data reproducing circuit |
| JP2010288257A (en) * | 2009-05-14 | 2010-12-24 | Nippon Telegr & Teleph Corp <Ntt> | Clock data reproducing circuit |
| JP2013034267A (en) * | 2009-05-14 | 2013-02-14 | Nippon Telegr & Teleph Corp <Ntt> | Clock-data regeneration circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3177025B2 (en) | 2001-06-18 |
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