JPH06151615A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06151615A JPH06151615A JP4294380A JP29438092A JPH06151615A JP H06151615 A JPH06151615 A JP H06151615A JP 4294380 A JP4294380 A JP 4294380A JP 29438092 A JP29438092 A JP 29438092A JP H06151615 A JPH06151615 A JP H06151615A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- base substrate
- mounting
- peripheral side
- outer peripheral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、ベース基板の主面の周辺領域と、このベース基板の
主面の周辺領域に対向するキャップの周縁面との間が接
合材で接合される半導体装置に適用して有効な技術に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a bonding material between a peripheral region of a main surface of a base substrate and a peripheral surface of a cap facing the peripheral region of the main surface of the base substrate. The present invention relates to a technique effectively applied to a semiconductor device to be joined.
【０００２】[0002]
【従来の技術】高い実装密度が得られる半導体装置とし
て、フェースダウン方式を利用した半導体装置が知られ
ている。この種の半導体装置は、ベース基板の主面（ペ
レット塔載面上）の中央領域上にフェースダウン方式で
半導体ペレットを実装し、この半導体ペレットを封止用
キャップで封止する。半導体ペレットは、ベース基板及
び封止用キャップで形成されるキャビティ内に封止され
る。フェースダウン方式は、半導体ペレットの外部端子
（ボンディングパッド）、ベース基板の電極の夫々をバ
ンプ電極(ＣＣＢ電極又は突起電極)で電気的及び機械的
に接続する方式である。フェースダウン方式は、半導体
ペレットの占有面積内においてベース基板に実装できる
ので、ボンディングワイヤ方式に比べて実装面積並びに
信号伝搬経路を縮小できる。2. Description of the Related Art A semiconductor device using a face-down method is known as a semiconductor device which can obtain a high packaging density. In this type of semiconductor device, a semiconductor pellet is mounted face down on a central region of a main surface (on a pellet mounting surface) of a base substrate, and the semiconductor pellet is sealed with a sealing cap. The semiconductor pellet is sealed in the cavity formed by the base substrate and the sealing cap. The face-down method is a method in which the external terminals (bonding pads) of the semiconductor pellet and the electrodes of the base substrate are electrically and mechanically connected by bump electrodes (CCB electrodes or protruding electrodes). Since the face-down method can be mounted on the base substrate within the area occupied by the semiconductor pellet, the mounting area and the signal propagation path can be reduced as compared with the bonding wire method.
【０００３】本発明者が開発中のフェースダウン方式を
利用する半導体装置は、ベース基板の主面の周辺領域
と、このベース基板の主面の周辺領域に対向する封止用
キャップの周縁面との間を接合材（例えばＰｂ−Ｓｎ系
合金からなる半田）で接合し、ベース基板及び封止用キ
ャップで形成されるキャビティ内に半導体ペレットを封
止する。この半導体装置は、ベース基板の主面に対向す
る封止用キャップの外周囲がベース基板の主面の外周囲
とほぼ同一の大きさで形成される。このように構成され
る半導体装置はフェースダウン方式で実装基板の実装面
上に実装される。つまり、半導体装置はバンプ電極を介
在して実装基板の実装面上に実装される。The semiconductor device utilizing the face-down method, which is being developed by the present inventor, has a peripheral area of the main surface of the base substrate and a peripheral surface of the sealing cap facing the peripheral area of the main surface of the base substrate. The two are bonded with a bonding material (for example, solder made of Pb—Sn alloy), and the semiconductor pellet is sealed in the cavity formed by the base substrate and the sealing cap. In this semiconductor device, the outer periphery of the sealing cap facing the main surface of the base substrate is formed to have substantially the same size as the outer periphery of the main surface of the base substrate. The semiconductor device configured as described above is mounted on the mounting surface of the mounting substrate by a face-down method. That is, the semiconductor device is mounted on the mounting surface of the mounting substrate with the bump electrodes interposed.
【０００４】前記半導体装置は、実装工程において、ハ
ンドリング装置で実装基板の実装面上に搬送され載置さ
れる。半導体装置は、封止用キャップ及びベース基板の
外周側面（半導体装置の外周側面）がバンドリング装置
のバンドリング部材で挾持され、収納治具から実装基板
の実装面上に搬送され載置される。In the mounting process, the semiconductor device is carried and placed on the mounting surface of the mounting substrate by a handling device. In the semiconductor device, the sealing cap and the outer peripheral side surface of the base substrate (outer peripheral side surface of the semiconductor device) are sandwiched by the bundling member of the bundling device, and the semiconductor device is transported from the storage jig to the mounting surface of the mounting substrate and placed. .
【０００５】なお、前記フェーダウン方式を利用する半
導体装置については、例えば特開昭６３−３１０１３９
号公報に記載されている。A semiconductor device using the fade-down method is disclosed in, for example, Japanese Patent Laid-Open No. 63-310139.
It is described in Japanese Patent Publication No.
【０００６】[0006]
【発明が解決しようとする課題】本発明者は、前述のフ
ェースダウン方式を利用する半導体装置について検討し
た結果、以下の問題点を見出した。The present inventor has found the following problems as a result of examining the semiconductor device utilizing the face-down method described above.
【０００７】前記半導体装置において、ベース基板の主
面の周辺領域と封止用キャップの周縁面との間を接合材
(半田)で接合する際、余分な接合材が封止用キャップ及
びベース基板の外周側面から外側に突出し(はみ出し)、
半導体装置の外周側面に突出した接合材が形成される。
このため、半導体装置の実装工程において、半導体装置
の外周側面をハンドリング部材で挾持する際、突出した
接合材の突出量（出っ張り量）に相当する分、ハンドリ
ングの位置精度にバラツキが生じ、半導体装置の実装精
度が低下するという問題があった。In the above semiconductor device, a bonding material is provided between the peripheral area of the main surface of the base substrate and the peripheral surface of the sealing cap.
When joining with (solder), excess joining material protrudes outward from the outer peripheral side surface of the sealing cap and the base substrate (protrusion),
The protruding bonding material is formed on the outer peripheral side surface of the semiconductor device.
Therefore, in the mounting process of the semiconductor device, when the outer peripheral side surface of the semiconductor device is held by the handling member, the positional accuracy of the handling varies due to the protrusion amount (protrusion amount) of the protruding bonding material. There was a problem that the mounting accuracy of was reduced.
【０００８】また、前記突出した接合材は、半導体装置
の外周側面から実装基板の実装面上に落下し、実装基板
の配線間又はバンプ電極間が短絡するという問題があっ
た。Further, there is a problem that the protruding bonding material drops from the outer peripheral side surface of the semiconductor device onto the mounting surface of the mounting substrate, and short-circuits between wirings or bump electrodes of the mounting substrate.
【０００９】本発明の目的は、実装時のハンドリング位
置精度のバラッキを廃止し、半導体装置の実装精度を向
上することが可能な技術を提供することにある。An object of the present invention is to provide a technique capable of improving the mounting accuracy of a semiconductor device by eliminating the variation in handling position accuracy during mounting.
【００１０】本発明の他の目的は、実装基板の配線間又
はバンプ電極間の短絡を防止することが可能な技術を提
供することにある。Another object of the present invention is to provide a technique capable of preventing a short circuit between wirings of a mounting substrate or between bump electrodes.
【００１１】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１２】[0012]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.
【００１３】（１）ベース基板の主面の周辺領域と、こ
のベース基板の主面の周辺領域に対向するキャップの周
縁面との間が接合材で接合される半導体装置において、
前記ベース基板の主面とその外周側面とが交わる第１角
部及び前記キャップの周縁面とその外周側面とが交わる
第２角部に所定の面積を有する面取り部を設ける。(1) In a semiconductor device in which a peripheral area of the main surface of the base substrate and a peripheral edge surface of the cap facing the peripheral area of the main surface of the base substrate are bonded with a bonding material,
A chamfer having a predetermined area is provided at a first corner where the main surface of the base substrate intersects the outer peripheral side surface and a second corner where the peripheral surface of the cap intersects the outer peripheral side surface.
【００１４】（２）ベース基板の主面の周辺領域と、こ
のベース基板の主面の周辺領域に対向するキャップの周
縁面との間が接合材で接合される半導体装置において、
前記ベース基板の主面とその外周側面とが交わる第１角
部若しくは前記キャップの周縁面とその外周側面とが交
わる第２角部に所定の面積を有する面取り部を設ける。(2) In a semiconductor device in which a peripheral area of the main surface of the base substrate and a peripheral surface of the cap facing the peripheral area of the main surface of the base substrate are bonded with a bonding material,
A chamfer having a predetermined area is provided at a first corner where the main surface of the base substrate intersects the outer peripheral side surface thereof or a second corner where the peripheral edge surface of the cap intersects the outer peripheral side surface thereof.
【００１５】[0015]
【作用】上述した手段によれば、ベース基板の主面の周
辺領域と、このベース基板の主面の周辺領域に対向する
キャップの周縁面との間を接合材で接合する際、面取り
部に余分な接合材を溜め込むことができるので、キャッ
プ及びベース基板の外周側面から外側に接合材が突出す
るのを防止できる。According to the above means, when the peripheral area of the main surface of the base substrate and the peripheral surface of the cap facing the peripheral area of the main surface of the base substrate are bonded with the bonding material, the chamfered portion is formed. Since excess bonding material can be stored, it is possible to prevent the bonding material from protruding outward from the outer peripheral side surfaces of the cap and the base substrate.
【００１６】この結果、半導体装置の外周側面をハンド
リング部材で挟持する際、半導体装置の外周側面にハン
ドリング部材が確実に接触するので、ハンドリングの位
置精度のバラツキを廃止でき、半導体装置の実装精度を
向上することができる。As a result, when the outer peripheral side surface of the semiconductor device is sandwiched by the handling members, the outer peripheral side surface of the semiconductor device is surely brought into contact with the outer peripheral side surface of the semiconductor device, so that variations in the positioning accuracy of the handling can be eliminated and the mounting accuracy of the semiconductor device can be improved. Can be improved.
【００１７】また、半導体装置の外周側面に突出した接
合材が形成されないので、この突出した接合材の落下に
よる実装基板の配線間又はバンプ電極間の短絡を防止す
ることができる。Further, since the protruding bonding material is not formed on the outer peripheral side surface of the semiconductor device, it is possible to prevent a short circuit between wirings of the mounting substrate or between bump electrodes due to the dropping of the protruding bonding material.
【００１８】以下、本発明の構成について、フェースダ
ウン方式を利用する半導体装置に本発明を適用した一実
施例とともに説明する。なお、実施例を説明するための
全図において、同一機能を有するものは同一符号を付
け、その繰り返しの説明は省略する。The structure of the present invention will be described below together with an embodiment in which the present invention is applied to a semiconductor device utilizing a face-down method. In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and repeated description thereof will be omitted.
【００１９】[0019]
【実施例】本発明の一実施例であるフェースダウン方式
を利用する半導体装置の概略構成を図１(要部断面図)に
示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A schematic structure of a semiconductor device using a face-down method according to an embodiment of the present invention is shown in FIG. 1 (main part sectional view).
【００２０】図１に示すように、本発明の一実施例であ
るフェースダウン方式を利用する半導体装置は、ベース
基板３の主面(ペレット塔載面)３Ａの中央領域上に半導
体ペレット１を塔載し、この半導体ペレット１を封止用
キャップ６で封止する。As shown in FIG. 1, in a semiconductor device utilizing a face-down method which is an embodiment of the present invention, a semiconductor pellet 1 is placed on a central region of a main surface (pellet tower mounting surface) 3A of a base substrate 3. The semiconductor pellets 1 are mounted on a tower and sealed with a sealing cap 6.
【００２１】前記ベース基板３は、例えばムライトで形
成され、図示していないが多層配線構造で構成される。
ベース基板３の主面３Ａ上には電極４Ａが複数配列さ
れ、その主面と対向する裏面上には電極４Ｂが複数配列
される。この電極４Ａ、電極４Ｂの夫々は、前記ベース
基板３の配線を介して電気的に接続される。The base substrate 3 is formed of, for example, mullite and has a multilayer wiring structure (not shown).
A plurality of electrodes 4A are arranged on the main surface 3A of the base substrate 3, and a plurality of electrodes 4B are arranged on the back surface facing the main surface. The electrodes 4A and 4B are electrically connected to each other via the wiring of the base substrate 3.
【００２２】前記半導体ペレット１は、例えば単結晶珪
素基板で形成され、その素子形成面(図１中下面)に論理
回路システム、記憶回路システム或はそれらの混合シス
テムが塔載される。半導体ペレット１の素子形成側には
複数個の外部端子（ボンディングパッド）２が配列され
る。The semiconductor pellet 1 is formed of, for example, a single crystal silicon substrate, and a logic circuit system, a memory circuit system or a mixed system thereof is mounted on the element formation surface (lower surface in FIG. 1). A plurality of external terminals (bonding pads) 2 are arranged on the element formation side of the semiconductor pellet 1.
【００２３】前記ベース基板３の電極４Ａ、半導体ペレ
ット１の外部端子２の夫々の間にはバンプ電極（ＣＣＢ
電極、突起電極）５が介在される。つまり、ベース基板
３、半導体ペレット１の夫々は、バンプ電極５を介在し
て電気的及び機械的に接続され、フェースダウン方式で
接続される。バンプ電極５は例えばＰｂ−Ｓｎ系合金か
らなる半田材料で形成される。A bump electrode (CCB) is provided between the electrode 4A of the base substrate 3 and the external terminal 2 of the semiconductor pellet 1.
Electrodes, protruding electrodes) 5 are interposed. That is, the base substrate 3 and the semiconductor pellet 1 are electrically and mechanically connected via the bump electrodes 5 and are connected in a face-down manner. The bump electrode 5 is formed of a solder material made of, for example, a Pb-Sn alloy.
【００２４】前記封止用キャップ６は、ベース基板３の
主面３Ａと対向する面側の中央領域に凹部が設けられ、
その周辺領域に周縁面６Ａを有する構造になっている。
つまり、封止用キャップ６は、断面形状がコの字形状で
形成され、ベース基板３とで半導体ペレット１を収納し
かつ封止するキャビティを構成する。また、封止用キャ
ップ６は、周縁面６Ａの外周囲(キャビティ側の外周囲)
がベース基板３の主面３Ａの外周囲とほぼ同一の大きさ
で形成される。つまり、封止用キャップ６の外周側面６
Ｂは、ベース基板３の外周側面３Ｂのほぼ延長線上に位
置する。この封止用キャップ６は、熱伝導性の良好な例
えば窒化アルミニウムで形成される。The sealing cap 6 is provided with a recess in the central region on the side facing the main surface 3A of the base substrate 3.
The peripheral area has a peripheral surface 6A.
That is, the sealing cap 6 has a U-shaped cross section, and together with the base substrate 3, forms a cavity for housing and sealing the semiconductor pellet 1. In addition, the sealing cap 6 has an outer periphery of the peripheral surface 6A (outer periphery of the cavity side).
Are formed with substantially the same size as the outer periphery of the main surface 3A of the base substrate 3. That is, the outer peripheral side surface 6 of the sealing cap 6
B is located substantially on the extension line of the outer peripheral side surface 3B of the base substrate 3. The sealing cap 6 is made of, for example, aluminum nitride having good thermal conductivity.
【００２５】前記封止用キャップ６の凹部の底部内壁に
は、熱伝導用充填材７を介在して半導体ペレット１の素
子形面と対向する裏面が連結される。熱伝導用充填材７
は例えばＰｂ−Ｓｎ系合金からなる半田材料で形成され
る。つまり、封止用キャップ６は、半導体ペレット１に
塔載された回路システムの動作で発生した熱が熱伝導充
填材を介して伝達される。To the inner wall of the bottom of the recess of the sealing cap 6, a back surface facing the element-shaped surface of the semiconductor pellet 1 is connected with a heat-conducting filler 7 interposed. Heat conduction filler 7
Is formed of a solder material made of, for example, a Pb—Sn alloy. That is, the heat generated by the operation of the circuit system mounted on the semiconductor pellet 1 is transferred to the sealing cap 6 via the heat conductive filler.
【００２６】前記封止用キャップ６はベース基板３の主
面３Ａ上に接合材９で接合さる。接合材９は例えばＰｂ
−Ｓｎ系合金からなる半田材料で形成される。この接合
材９は、封止用キャップ６の周縁面６Ａとベース基板３
の主面３Ａの周辺領域との間を接合し、ベース基板３の
主面３Ａ上に封止用キャップ６を固着する。The sealing cap 6 is bonded to the main surface 3A of the base substrate 3 with a bonding material 9. The bonding material 9 is, for example, Pb
-Sn-based alloy is used for the solder material. The bonding material 9 is formed on the peripheral surface 6A of the sealing cap 6 and the base substrate 3
The main surface 3A of the base substrate 3 is joined to the peripheral region thereof, and the sealing cap 6 is fixed onto the main surface 3A of the base substrate 3.
【００２７】前記封止用キャップ６には、周縁面６Ａと
外周側面６Ｂとが交わる角部に面取り加工を施した所定
の面積を有する面取り部６Ｃが設けられる。また、前記
ベース基板３には、主面３Ａと外周側面３Ｂとが交わる
角部に面取り加工を施した所定の面積を有する面取り部
３Ｃが設けられる。この面取り部６Ｃ、面取り部３Ｃの
夫々は、カケ等の損傷を防止する目的としてケース等の
角部に設けられる通常の面取りに比べて大きく面取りさ
れる。面取り部６Ｃ、面取り部３Ｃの夫々は、ベース基
板３の主面３Ａの周辺領域と封止用キャップ６の周縁面
６Ｃとの間を封止材９で接合する際、余分な接合材９を
溜め込むことができ、接合材８がベース基板３の外周側
面３Ｂ及び封止用キャップ６の外周側面６Ｃから外側に
突出するのを防止できる。The sealing cap 6 is provided with a chamfered portion 6C having a predetermined area which is chamfered at the corner where the peripheral surface 6A and the outer peripheral side surface 6B intersect. Further, the base substrate 3 is provided with a chamfered portion 3C having a predetermined area in which a corner portion where the main surface 3A and the outer peripheral side surface 3B intersect is chamfered. Each of the chamfered portion 6C and the chamfered portion 3C is chamfered more than a normal chamfer provided at a corner of a case or the like for the purpose of preventing damage such as chipping. Each of the chamfered portion 6C and the chamfered portion 3C removes the excess bonding material 9 when bonding the peripheral area of the main surface 3A of the base substrate 3 and the peripheral surface 6C of the sealing cap 6 with the sealing material 9. It can be stored, and the bonding material 8 can be prevented from protruding outward from the outer peripheral side surface 3B of the base substrate 3 and the outer peripheral side surface 6C of the sealing cap 6.
【００２８】前記封止用キャップ６の周縁面６Ａ及び面
取り部６Ｃには例えばメタライズ層８が形成される。ま
た、前記ベース基板３の主面３Ａの周辺領域及び面取り
部３Ｃには例えばメタライズ層８が形成される。このメ
タライズ層８は、例えばＴｉ膜、Ｃｕ膜、Ａｌ膜の夫々
を順次蒸着した複合膜で形成され、接合材９の濡れ性を
確保している。つまり、本実施例の半導体装置は、封止
用キャップ６の周縁面６Ａに形成されたメタライズ層９
とベース基板３の主面３Ａの周辺領域に形成されたメタ
ライズ層９とを接合材８で接合している。この場合、面
取り部６Ａと面取り部３Ｃとの間に接合材９が形成さ
れ、接合材９の膜厚が厚くなるので、接合強度を向上す
ることができると共に、気密性を向上することができ
る。A metallized layer 8 is formed on the peripheral surface 6A and the chamfered portion 6C of the sealing cap 6, for example. Further, for example, a metallized layer 8 is formed on the peripheral region of the main surface 3A of the base substrate 3 and the chamfered portion 3C. The metallized layer 8 is formed of, for example, a composite film in which a Ti film, a Cu film, and an Al film are sequentially deposited, and ensures the wettability of the bonding material 9. That is, in the semiconductor device of this embodiment, the metallization layer 9 formed on the peripheral surface 6A of the sealing cap 6 is used.
The metallization layer 9 formed in the peripheral region of the main surface 3A of the base substrate 3 is joined by the joining material 8. In this case, since the bonding material 9 is formed between the chamfered portion 6A and the chamfered portion 3C, and the film thickness of the bonding material 9 is increased, the bonding strength can be improved and the airtightness can be improved. .
【００２９】このように構成される半導体装置は、図１
に示すように、フェースダウン方式で実装基板１０の実
装面上に１個或は複数個実装される。実装基板１０は、
半導体装置のベース基板３と同様に多層配線構造で構成
され、その実装面上には電極１１が複数配列される。つ
まり、半導体装置は、ベース基板３の電極４Ｂがバンプ
電極１２を介在して実装基板３の電極１１に電気的及び
機械的に接続される。The semiconductor device having such a structure is shown in FIG.
As shown in FIG. 1, one or a plurality of components are mounted on the mounting surface of the mounting substrate 10 by the face-down method. The mounting board 10 is
Similar to the base substrate 3 of the semiconductor device, it has a multilayer wiring structure, and a plurality of electrodes 11 are arranged on the mounting surface thereof. That is, in the semiconductor device, the electrode 4B of the base substrate 3 is electrically and mechanically connected to the electrode 11 of the mounting substrate 3 with the bump electrode 12 interposed therebetween.
【００３０】前記半導体装置は、実装工程において、ハ
ンドリング装置で実装基板１０の実装面上に搬送され載
置される。つまり、半導体装置は、ハンドリング装置の
ハンドリング部材で外周側面（封止用キャップ６の外周
側面６Ｃ及びベース基板３の外周側面３Ｃ）を挾持さ
れ、収納治具から実装基板１０の実装面上に搬送され載
置される。この時、半導体装置の外周側面には突出した
接合材が形成されていないので、半導体装置の外周側面
にハンドリング部材が確実に接触し、ハンドリングの位
置精度のバラツキを廃止できる。この結果、半導体装置
の実装精度を向上することができる。In the mounting process, the semiconductor device is carried and placed on the mounting surface of the mounting substrate 10 by a handling device. That is, in the semiconductor device, the outer peripheral side surfaces (the outer peripheral side surface 6C of the sealing cap 6 and the outer peripheral side surface 3C of the base substrate 3) are held by the handling member of the handling device, and the semiconductor device is conveyed from the storage jig onto the mounting surface of the mounting substrate 10. And placed. At this time, since the protruding bonding material is not formed on the outer peripheral side surface of the semiconductor device, the handling member is surely brought into contact with the outer peripheral side surface of the semiconductor device, and variations in the positional accuracy of handling can be eliminated. As a result, the mounting accuracy of the semiconductor device can be improved.
【００３１】また、半導体装置の外周側面に突出した接
合材が形成されないので、この突出した接合材の落下に
よる実装基板１０の実装面上の配線(電極１１)間又はバ
ンプ電極１２間の短絡を防止することができる。Further, since the protruding bonding material is not formed on the outer peripheral side surface of the semiconductor device, a short circuit occurs between the wirings (electrodes 11) or the bump electrodes 12 on the mounting surface of the mounting substrate 10 due to the drop of the protruding bonding material. Can be prevented.
【００３２】このように、ベース基板３の主面３Ａの周
辺領域と、このベース基板３の主面３Ａの周辺領域に対
向する封止用キャップ６の周縁面６Ａとの間が接合材８
で接合される半導体装置において、前記ベース基板３の
主面３Ａとその外周側面３Ｂとが交わる角部に所定の面
積を有する面取り部３Ｃ及び前記封止用キャップ６の周
縁面６Ａとその外周側面６Ｂとが交わる角部に所定の面
積を有する面取り部６Ｃを設ける。この構成により、ベ
ース基板３の主面３Ａの周辺領域と封止用キャップ６の
周縁面６Ａとの間を接合材９で接合する際、面取り部３
Ｃ及び面取り部６Ｃに余分な接合材９を溜め込むことが
できるので、ベース基板３の外周側面３Ｂ及び封止用キ
ャップ６の外周側面６Ｂから外側に接合材９が突出する
のを防止できる。As described above, the bonding material 8 is provided between the peripheral area of the main surface 3A of the base substrate 3 and the peripheral surface 6A of the sealing cap 6 facing the peripheral area of the main surface 3A of the base substrate 3.
In the semiconductor device bonded by the above method, the chamfered portion 3C having a predetermined area at the corner where the main surface 3A of the base substrate 3 and the outer peripheral side surface 3B intersect, and the peripheral surface 6A of the sealing cap 6 and the outer peripheral side surface thereof. A chamfered portion 6C having a predetermined area is provided at a corner where 6B intersects. With this configuration, when the peripheral area of the main surface 3A of the base substrate 3 and the peripheral surface 6A of the sealing cap 6 are bonded with the bonding material 9, the chamfered portion 3 is formed.
Since the excess bonding material 9 can be stored in the C and the chamfered portion 6C, it is possible to prevent the bonding material 9 from protruding outward from the outer peripheral side surface 3B of the base substrate 3 and the outer peripheral side surface 6B of the sealing cap 6.
【００３３】この結果、半導体装置の外周側面（封止用
キャップ６の外周側面６Ｂ及びベース基板３の外周側面
３Ｂ）をハンドリング部材で挾持する際、半導体装置の
外周側面にハンドリング部材が確実に接触するので、ハ
ンドリングの位置精度のバラツキを廃止でき、半導体装
置の実装精度を向上することができる。As a result, when the outer peripheral side surface of the semiconductor device (the outer peripheral side surface 6B of the sealing cap 6 and the outer peripheral side surface 3B of the base substrate 3) is held by the handling member, the outer peripheral side surface of the semiconductor device is surely brought into contact with the handling member. Therefore, it is possible to eliminate variations in the positional accuracy of handling and improve the mounting accuracy of the semiconductor device.
【００３４】また、半導体装置の外周側面に突出した接
合材が形成されないので、この突出した接合材の落下に
よる実装基板の実装面上の配線(電極１１)間又はバンプ
電極１２間の短絡を防止することができる。Further, since the protruding bonding material is not formed on the outer peripheral side surface of the semiconductor device, a short circuit between the wirings (electrodes 11) or the bump electrodes 12 on the mounting surface of the mounting substrate due to the dropping of the protruding bonding material is prevented. can do.
【００３５】なお、本実施例の半導体装置は、ベース基
板３の角部に面取り部３Ｃ、封止用キャップ６の角部に
面取り部６Ｃの夫々を設けた構成になっているが、図２
（要部断面図）に示すように、ベース基板３の角部に面
取り部３Ｃを設けた構成にしてもよいし、図３（要部断
面図）に示すように、封止用キャップ６の角部に面取り
部６Ｃを設けた構成にしてもよい。The semiconductor device of this embodiment has a structure in which the chamfered portion 3C is provided at the corner of the base substrate 3 and the chamfered portion 6C is provided at the corner of the sealing cap 6, as shown in FIG.
As shown in (partial cross-sectional view), a chamfered portion 3C may be provided at a corner of the base substrate 3, or as shown in FIG. The chamfered portions 6C may be provided at the corners.
【００３６】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the inventions made by the present inventor are
Although the specific description has been given based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.
【００３７】[0037]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００３８】実装時のハンドリング精度のバラツキを廃
止し、半導体装置の実装精度を向上することができる。Variations in handling accuracy during mounting can be eliminated and the mounting accuracy of the semiconductor device can be improved.
【００３９】また、余分な接合材の落下による実装基板
間又はバンプ電極間の短絡を防止できる。Further, it is possible to prevent a short circuit between the mounting substrates or between the bump electrodes due to an excessive dropping of the bonding material.
【図１】 本発明の一実施例である半導体装置の概略構
成を示す断面図。FIG. 1 is a sectional view showing a schematic configuration of a semiconductor device that is an embodiment of the present invention.
【図２】 本発明の他の実施例である半導体装置の要部
断面図。FIG. 2 is a sectional view of a main portion of a semiconductor device according to another embodiment of the present invention.
【図３】 本発明の他の実施例である半導体装置の要部
断面図。FIG. 3 is a cross-sectional view of essential parts of a semiconductor device according to another embodiment of the present invention.
１…半導体ペレット、２…外部端子、３…ベース基板、
４Ａ，５Ｂ…電極、５…バンプ電極、６…封止用キャッ
プ、７…熱伝導用充填材、８…メタライズ層、９…接合
材、１０…実装基板、１１…電極、１２…バンプ電極。1 ... Semiconductor pellet, 2 ... External terminal, 3 ... Base substrate,
4A, 5B ... Electrodes, 5 ... Bump electrodes, 6 ... Sealing caps, 7 ... Thermal conductive fillers, 8 ... Metallization layers, 9 ... Bonding materials, 10 ... Mounting substrate, 11 ... Electrodes, 12 ... Bump electrodes.
Claims (2)
ース基板の主面の周辺領域に対向するキャップの周縁面
との間が接合材で接合される半導体装置において、前記
ベース基板の主面とその外周側面とが交わる第１角部及
び前記キャップの周縁面とその外周側面とが交わる第２
角部に所定の面積を有する面取り部が設けられているこ
とを特徴とする半導体装置。1. A semiconductor device in which a peripheral region of a main surface of a base substrate and a peripheral surface of a cap facing the peripheral region of the main surface of the base substrate are bonded with a bonding material. A first corner where the surface and the outer peripheral side surface intersect and a second corner where the peripheral surface of the cap and the outer peripheral side surface intersect
A semiconductor device, wherein a chamfered portion having a predetermined area is provided at a corner portion.
ース基板の主面の周辺領域に対向するキャップの周縁面
との間が接合材で接合される半導体装置において、前記
ベース基板の主面とその外周側面とが交わる第１角部若
しくは前記キャップの周縁面とその外周側面とが交わる
第２角部に所定の面積を有する面取り部が設けられてい
ることを特徴とする半導体装置。2. A semiconductor device in which a peripheral region of a main surface of a base substrate and a peripheral surface of a cap facing the peripheral region of the main surface of the base substrate are bonded with a bonding material. A semiconductor device, wherein a chamfer having a predetermined area is provided at a first corner where a surface and an outer peripheral side surface thereof intersect or a second corner where a peripheral surface of the cap and an outer peripheral side surface thereof intersect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4294380A JPH06151615A (en) | 1992-11-02 | 1992-11-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4294380A JPH06151615A (en) | 1992-11-02 | 1992-11-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06151615A true JPH06151615A (en) | 1994-05-31 |
Family
ID=17806977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4294380A Pending JPH06151615A (en) | 1992-11-02 | 1992-11-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06151615A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6075289A (en) * | 1996-10-24 | 2000-06-13 | Tessera, Inc. | Thermally enhanced packaged semiconductor assemblies |
-
1992
- 1992-11-02 JP JP4294380A patent/JPH06151615A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6075289A (en) * | 1996-10-24 | 2000-06-13 | Tessera, Inc. | Thermally enhanced packaged semiconductor assemblies |
| US6354485B1 (en) | 1996-10-24 | 2002-03-12 | Tessera, Inc. | Thermally enhanced packaged semiconductor assemblies |
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