JPH0612235A - Circuit and method for multiplication over integer - Google Patents
Circuit and method for multiplication over integerInfo
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- JPH0612235A JPH0612235A JP4167082A JP16708292A JPH0612235A JP H0612235 A JPH0612235 A JP H0612235A JP 4167082 A JP4167082 A JP 4167082A JP 16708292 A JP16708292 A JP 16708292A JP H0612235 A JPH0612235 A JP H0612235A
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- bit
- integer
- bits
- full adder
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は整数上の乗算回路に関
し、特に小さな桁数の乗算器を用いて大きな桁数の乗算
を行う回路及びその方法に関するものである。本発明
は、大きな桁数の乗算を必要とするRSA暗号(池野信
一,小山謙二:“現代暗号学”,電子情報通信学会,1
986,6章)のような暗号化技術をはじめとして多く
の整数演算に利用することができる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integer multiplication circuit, and more particularly to a circuit and method for performing multiplication with a large number of digits by using a multiplier with a small number of digits. The present invention is an RSA cipher that requires multiplication of a large number of digits (Shinichi Ikeno, Kenji Koyama: "Modern Cryptography", IEICE, 1
It can be used for many integer operations, including encryption techniques such as 980, 6).
【0002】[0002]
【従来の技術】ゲートアレイの設計や基板設計におい
て、小さな桁数の整数上の乗算器は、セルライブラリや
TTL等が用意されているため手軽に構成することがで
きる。しかし、大きな桁数の乗算回路を実現しようとし
た場合には、セルライブラリ等がないので自分で設計し
なければならない。ところが、大きな桁数の乗算器を自
分で設計する場合、小さな桁数の乗算器の回路構成をそ
のまま拡張したのでは、回路構成が非常に複雑になり実
現が難しい。2. Description of the Related Art In a gate array design or substrate design, a multiplier on an integer having a small number of digits can be easily constructed because a cell library, TTL, etc. are prepared. However, when trying to realize a multiplication circuit with a large number of digits, there is no cell library or the like, so it is necessary to design by yourself. However, in the case of designing a multiplier with a large number of digits by itself, if the circuit configuration of the multiplier with a small number of digits is expanded as it is, the circuit configuration becomes very complicated and difficult to realize.
【0003】また、入力値を所定ビツト毎に分割して複
数クロツクで乗算を行おうとする場合、入力値を多項式
と見なすと、ガロア体(宮川洋,原島博,今井秀樹:
“情報と符号の理論”,岩波講座,1982,6章)の
ような桁上がりのない演算系では、図2のような回路に
よつて乗算が行われることが知られている。図2中、*
Bi はBi (i=0,…,n−1)を乗数としたmビツ
ト*mビツトのガロア体上の乗算器、EXはmビツトの
EXOR、rはmビツトのレジスタである。When an input value is divided into predetermined bits and multiplication is performed by a plurality of clocks, if the input value is regarded as a polynomial, Galois field (Yo Miyakawa, Hiroshi Harajima, Hideki Imai:
It is known that multiplication is performed by a circuit as shown in FIG. 2 in an arithmetic system with no carry such as “Theory of Information and Code”, Iwanami Course, 1982, Chapter 6). In Figure 2, *
B i is a multiplier on the Galois field of m bits * m bits with B i (i = 0, ..., N−1) as a multiplier, EX is an EXOR of m bits, and r is a register of m bits.
【0004】しかし、整数上の乗算では、図2のような
分割演算を行うと分割演算した桁毎に桁上がりが生じる
ため、効率的な乗算器を実現することは難しい。However, in the multiplication on an integer, carrying out a division operation as shown in FIG. 2 causes a carry for each digit of the division operation, so that it is difficult to realize an efficient multiplier.
【0005】[0005]
【発明が解決しようとしている課題】本発明は、上述の
欠点を除去し、乗算回路において大きな桁数の入力値を
分割して演算する場合に、小さな桁数の乗算器を用いて
桁上がりを考慮した効率的な整数上の乗算回路及び乗算
方法を提供することを目的とする。SUMMARY OF THE INVENTION The present invention eliminates the above-mentioned drawbacks, and when a multiplication circuit divides an input value having a large number of digits for arithmetic operation, a carry with a carry having a small number of digits is used. It is an object of the present invention to provide an efficient integer multiplication circuit and multiplication method in consideration.
【0006】[0006]
【課題を解決するための手段】この課題を解決するため
に、本発明の整数上の乗算回路は、h,m,nを正の整
数とする場合に、(n×m)ビツトの整数Aと(h×
m)ビツトの整数Bとの乗算を行う整数上の乗算回路で
あつて、整数Aがmビツト毎にnクロツクに分けて上位
桁から入力され、該整数Aの各mビツトに整数Bの所定
のmビツトを乗算する前記整数Aに対して並列につなが
れるmビツト×mビツトの乗算器と、該乗算器の出力
と、1つ下位桁のキヤリー付き2mビツトフルアダーの
前回のクロツク時の出力の下位2mビツトと、3つ下位
桁の前記キヤリー付き2mビツトフルアダーの前回のク
ロツク時の出力のキヤリービツトとを加算する、前記乗
算器に対応して各1つと最終段に更に1つとの1次元状
に並べられた前記キヤリー付き2mビツトのフルアダー
と、前記キヤリー付き2mビツトフルアダーの2m+1
ビツトの出力を同時に入出力する、前記2つのキヤリー
付き2mビツトフルアダー間につながれるレジスタとを
備え、クロツクに同期して最上位の前記キヤリー付き2
mビツトフルアダーから乗算結果A・Bを上位桁より出
力する。To solve this problem, the integer multiplication circuit of the present invention uses an integer A of (n × m) bits when h, m, and n are positive integers. And (h ×
m) A multiplication circuit on an integer which multiplies the bit B by an integer B. The integer A is divided into n clocks for every m bits and is input from the upper digit, and the integer B is assigned to each m bit of the integer A. Of m bits x m bits connected in parallel to the integer A for multiplying m bits of the output, the output of the multiplier, and the last clock of the 2m bit full adder with one lower digit carrier. The lower 2m bit of the output and the lower 2m bit of the output of the 3m lower 2m bit full adder with the carry at the previous clock are added, one for each of the multipliers and one for the final stage. The 2m bit full adder with the carrier and the 2m bit full adder with the carrier arranged one-dimensionally
It is equipped with a register for inputting and outputting the output of the bit at the same time, which is connected between the two 2m bit full adders with a carrier, and the highest carrier with the carrier 2 synchronized with the clock.
The multiplication results A and B are output from the upper digit from the m bitful adder.
【0007】ここで、整数Bの最下位桁のmビツトを乗
算する前記mビツト×mビツトの乗算器に対応するキヤ
リー付き2mビツトフルアダーが削除される。又、前記
キヤリー付きフルアダーは、複数の2入力フルアダーま
たはハーフアダーによつて実現される。Here, the 2m bit full adder with a carrier corresponding to the m bit × m bit multiplier for multiplying the m bit of the least significant digit of the integer B is deleted. The full adder with a carrier is realized by a plurality of 2-input full adders or half adders.
【0008】又、本発明の整数上の乗算方法は、h,
m,nを正の整数とする場合に、(n×m)ビツトの整
数Aと(h×m)ビツトの整数Bとの乗算を行う整数上
の乗算方法であつて、mビツト×mビツトの乗算器と、
キヤリー付き2mビツトフルアダーと、該フルアダーの
出力を記憶する整数Bの桁に対応してアドレス配置され
る複数領域を有する少なくとも2m+1ビツトのメモリ
とを備え、(A) 整数Aのn分割されたmビツト(Ai )
と整数Bのh分割されたmビツト(Bj )とを前記mビ
ツト×mビツトの乗算器で乗算する行程と、(B) 乗算結
果と前記メモリの所定領域(Rj-1 )の下位2mビツト
と所定領域(Rj-3 )の2m+1ビツト目とを前記フル
アダーで加算する行程と、(C) 加算結果を前記メモリの
所定領域(Ri )に記憶する行程とを備え、前記行程
(A) 〜(C) を各Ai(i=n−1,n−2,…,0の順)
について、B j のjをn−1から0まで変化させて繰り
返し、各Ai についてBn-1 の行程が終了後の前記メモ
リの所定領域(Rn-1 )の下位2m+1ビツトと所定領
域(R n-2 )の2m+1ビツト目と所定領域(Rn-3 )
の2m+1ビツト目とを前記フルアダーで加算した結果
を乗算結果A・Bの上位桁よりの出力する。The integer multiplication method of the present invention uses h,
If m and n are positive integers, the (n × m) bit order
On an integer that multiplies the number A by the (h × m) bit integer B
And a multiplier of m bits × m bits,
2m bit full adder with carrier and the full adder
The address is arranged corresponding to the digit of the integer B that stores the output
At least 2m + 1 bit memory with multiple areas
And (A) an n-divided m bit of the integer A (Ai )
And an integer B divided by m bits (Bj ) And the above
The process of multiplying with a multiplier of m × m bits and (B) Multiplication result
Fruit and a predetermined area of the memory (Rj-1 ) Lower 2m bit
And predetermined area (Rj-3 ) 2m + 1 bit eyes and full above
The process of adding with an adder and (C) The addition result is stored in the memory.
Predetermined area (Ri ) Is stored in the
(A) to (C) for each Ai(i = n-1, n-2, ..., 0 order)
About B j Repeat j from n-1 to 0
Return each Ai About Bn-1 Note after the end of the process
Predetermined area (Rn-1 ) Lower 2m + 1 bits and predetermined area
Area (R n-2 ) 2m + 1 bit and a predetermined area (Rn-3 )
2m + 1 bit and the result of adding with the full adder
Is output from the upper digit of the multiplication result A / B.
【0009】[0009]
【実施例】本実施例ではn・mビツトの整数Aとh・m
ビツトの整数Bとの乗算器を想定するが、簡単のために
h=nとして説明する。この限定により一般性が失われ
ることはない。すなわち、n・mビツトの2つの整数を
A,Bとし、A・B=Cの演算を実行することを考え
る。ここで、mビツトの2つの整数a,bの乗算a・b
=cを実行する乗算器は公知の構成、例えばセルライブ
ラリやTTL等によつて簡単に実現できる。[Embodiment] In this embodiment, an integer A of n · m bits and h · m
A multiplier with a bit integer B is assumed, but for the sake of simplicity, it will be described as h = n. This limitation does not lose generality. That is, it is considered that the two integers of n · m bits are A and B, and the operation of A · B = C is executed. Here, the multiplication a · b of two integers a and b of m bits
The multiplier for executing = c can be easily realized by a known structure such as a cell library or TTL.
【0010】整数A,Bを各々mビツト毎にn分割する
と、次のように表せる。If the integers A and B are each divided into m bits, the result can be expressed as follows.
【0011】A=An-1 ・Xn-1 +An-2 ・Xn-2 +…
+A1 ・X+A0 B=Bn-1 ・Xn-1 +Bn-2 ・Xn-2 +…+B1 ・X+
B0 ここで、X=2m-1 とし、A,Bについてmビツト毎に
上位桁から分割したビツト系列を、各々Ai ,Bi (i
=n−1,…,0)とする。この場合、整数A,Bは多
項式とみなすことができるので、A・Bは次のように表
すことができる。A = A n- 1.X n-1 + A n- 2.X n-2 + ...
+ A 1 · X + A 0 B = B n-1 · X n-1 + B n-2 · X n-2 + ... + B 1 · X +
B 0 Here, assuming that X = 2 m−1 , the bit sequences obtained by dividing the high-order digit by m bits for A and B are A i and B i (i
= N-1, ..., 0). In this case, since the integers A and B can be regarded as polynomials, A · B can be expressed as follows.
【0012】[0012]
【数1】 ここでは、簡略化の為n=4の場合を考えるが、この限
定により一般性が失われることはない。[Equation 1] Here, the case of n = 4 is considered for simplification, but this limitation does not lose generality.
【0013】[0013]
【数2】 A・B=A3 ・(B3 ・X6 +B2 ・X5 +B1 ・X4 +B0 ・X3 ) +A2 ・(B3 ・X5 +B2 ・X4 +B1 ・X3 +B0 ・X2 ) +A1 ・(B3 ・X4 +B2 ・X3 +B1 ・X2 +B0 ・X) +A0 ・(B3 ・X3 +B2 ・X2 +B1 ・X +B0 ) =C6 ・X6 +C5 ・X5 +C4 ・X4 +C3 ・X3 +C2 ・X2 +C1 ・X+C0 これを、図1のような回路で乗算器を構成できる。図1
はmビツト×mビツトの乗算a・b=cを実行する乗算
器4個(×B0 〜×B3 )と、2mビツトのキヤリー付
き加算器(フルアダー)4個(+1 〜+4 )と、(2m
+1)ビツトのレジスタ4個(R0 〜R3 )とから構成
される。[Formula 2] A · B = A 3 · (B 3 · X 6 + B 2 · X 5 + B 1 · X 4 + B 0 · X 3 ) + A 2 · (B 3 · X 5 + B 2 · X 4 + B 1 · X 3 + B 0 · X 2 ) + A 1 · (B 3 · X 4 + B 2 · X 3 + B 1 · X 2 + B 0 · X) + A 0 · (B 3 · X 3 + B 2 · X 2 + B 1 · X + B 0 ) = C 6 · X 6 + C 5 · X 5 + C 4 · X 4 + C 3 · X 3 + C 2 · X 2 + C 1 · X + C 0 This can be constructed by a circuit as shown in FIG. Figure 1
Multiplier 4 which performs multiplication a · b = c of m bits × m bits is (× B 0 ~ × B 3 ) and, 2m bit the carry with adder (full adder) 4 (+ 1 + 4) And (2m
+1) 4 bit registers (R 0 to R 3 ).
【0014】図1において各レジスタの初期状態はオー
ル“0”とする。In FIG. 1, the initial state of each register is all "0".
【0015】最初のクロツクでA3 が入力されると、
式の各項の係数A3 ・Bi (i=3…0)が各乗算器か
ら出力され、各フルアダー(+1 〜+3 )を通して各々
のレジスタ(R0 〜R3 )に格納される。When A 3 is input at the first clock,
Output coefficient A 3 · B i of each term of the formula (i = 3 ... 0) from the multiplier is stored in each register (R 0 to R 3) through each full adder (+ 1 + 3) .
【0016】次のクロツクでA2 が入力されたとき、A
・Bの最上位桁であるX6 の係数C 6 (=A3 ・B3 )
が右端のレジスタR3 からフルアダー+4 を通して出力
される。そのとき、他のフルアダー(+1 〜+3 )で
は、そのフルアダーの左隣にあるレジスタ出力A3 ・B
i-1 (i=3…0)と乗算器からの出力A2 ・Bi (i
=3…0)との和である(A3 ・Bi-1 +A2 ・Bi )
(i=3…0)が演算され、その出力は各々右隣のレジ
スタに入力される。これは上式において式と式のX
5 ,X4 ,X3 の各係数の和を計算することを意味す
る。A at the next clock2 When is input, A
・ X, which is the most significant digit of B6 Coefficient C 6 (= A3 ・ B3 )
Is the rightmost register R3 To full adderFour Output through
To be done. At that time, another full adder (+1 ~ +3 )so
Is the register output A to the left of the full adder.3 ・ B
i-1 (I = 3 ... 0) and the output A from the multiplier2 ・ Bi (I
= 3 ... 0) (A3 ・ Bi-1 + A2 ・ Bi )
(I = 3 ... 0) is calculated, and the output is the register on the right of each.
It is input to the studio. This is the formula and the X of the formula
Five , XFour , X3 Means to compute the sum of each coefficient of
It
【0017】ただし、Bi (i=−1…−n)は常に
“0”とする。ここで、A3 ・Bi-1,A2 ・Bi の各
値は各々2mビツトであるので、フルアダーからの出力
は桁上がりがあれば2m+1ビツトになる。従つて、各
レジスタは2m+1ビツト必要になる。ここで、レジス
タの各ビツトは桁を意味し、1つのレジスタの最上位ビ
ツトは最下位ビツトに対して22m=X2 桁目に当たる。
しかし、各レジスタRiはX桁の演算結果を格納するの
で、各レジスタRi の最上位ビツトは2つ右隣のレジス
タRi+2 の最下位ビツトと同じ桁になる。However, B i (i = -1 ...- n) is always "0". Since each value of A 3 · B i −1 and A 2 · B i is 2 m bits, the output from the full adder is 2 m + 1 bits if there is a carry. Therefore, each register requires 2m + 1 bits. Here, each bit of the register means digit, the most significant bit of one register hits 2 digit 2 2m = X with respect to the least significant bit.
However, since each register R i stores the operation result of X digits, the most significant bit of each register R i has the same digit as the least significant bit of the register R i + 2 on the right of the two.
【0018】次のクロツクでA1 が入力されたとき、図
1の回路の右端のフルアダー(+4)からはX5 の係数
に当たるC5 =(A3 ・B2 +A2 ・B3 )が出力され
る。このとき、C5 の最下位ビツトと同じ桁である2つ
左隣のレジスタR2 の最上位ビツトとC5 のX桁と同じ
桁である左隣のレジスタR3 の最上位ビツトも加算され
て出力される。このとき、他のフルアダー(+1 〜+
3 )は、左隣のレジスタからの2mビツト出力と乗算器
からの2mビツト出力の他に、3つ左隣のレジスタから
の桁上がり出力である最上位ビツトをキヤリーとして加
えることによつて、2m+1ビツトの出力を行う。これ
によつて、上の〜式までの各項の係数を加えたこと
になる。[0018] When A 1 is entered in the next clock, C 5 = (A 3 · B 2 + A 2 · B 3) which corresponds to the coefficient of X 5 from the full adder (+ 4) of the right end of the circuit of Figure 1 Is output. At this time, the most significant bit of the immediate left of the register R 3 is the same order of magnitude as the least significant bit is two left neighboring same order of magnitude as X digit the most significant bit and C 5 of the register R 2 in C 5 is also added Is output. At this time, the other of the full adder (+ 1 to +
3 ) is the addition of the 2m bit output from the register on the left side and the 2m bit output from the multiplier, and the addition of the most significant bit, which is the carry output from the register on the left side, as a carrier. Output 2m + 1 bits. As a result, the coefficients of the respective terms up to the above equation are added.
【0019】次のクロツクで最後の入力A0 が入力され
たとき、同様に右端のフルアダー(+4 )からX4 の係
数であるC4 が出力され、各乗算器では上の式の各項
の係数A0 ・Bi (i=3…0)が出力される。その出
力を受けて、各フルアダーではX3 〜X0 に対する係数
C3 〜C0 が順次出力され、乗算結果の全てが出力され
る。これによつて整数Aの値が分割入力されるときA・
Bの演算が効率的に行われる。[0019] When the next last input A 0 in clock is input, likewise C 4 is the coefficient of X 4 is outputted from the right end of the full adder (+ 4), each term of the above equation in each of the multipliers The coefficient A 0 · B i (i = 3 ... 0) of is output. In response to the output, in each full adder is the coefficient C 3 -C 0 are sequentially output to X 3 to X 0, all of the multiplication result is output. As a result, when the value of the integer A is divided and input,
The calculation of B is efficiently performed.
【0020】以上によつて、入力値がmビツト毎にn分
割されて入力されるとき、mビツト×mビツトの乗算器
を用いてn・mビツトの乗算回路が効率的に実現できる
ことが示せた。h≠nの場合にも、同様の回路で乗算が
実行できることは明かである。また、図1の右端のフル
アダーとレジスタを省いたり、更にフルアダーとレジス
タを付け加えても同様の構成ができることも明かであ
る。また、図1のような同一の演算素子の繰り返しによ
る構成はVLSI等の大規模回路を構成しやすいという
利点もある。From the above, it can be shown that when the input value is divided into n bits every m bits and is input, an n · m bits multiplication circuit can be efficiently realized by using an m bits × m bits multiplier. It was It is clear that the multiplication can be executed by the same circuit even when h ≠ n. It is also apparent that the same configuration can be achieved by omitting the full adder and the register at the right end of FIG. 1 or by adding the full adder and the register. Further, the configuration in which the same arithmetic element is repeated as shown in FIG. 1 has an advantage that a large-scale circuit such as VLSI is easily configured.
【0021】又、図1の乗算器(×B0 )とレジスタR
0 との間にフルアダー(+0 )を設けても等価であり、
本例は乗算器(×Bi )とフルアダー(+i )とレジス
タ(Ri )とを1つのプロセツシング・エレメント(P
E)と考えたパイプライン方式でも実現できる。更に、
乗算器(×Bi )とフルアダー(+i )と複数領域を有
するメモリとから構成して、ソフトウエアによる順次あ
るいは並列処理によつても実現できる。Further, the multiplier (× B 0 ) and the register R shown in FIG.
It is equivalent to provide a full adder (+ 0 ) between 0 and
In this example, a multiplier (× B i ), a full adder (+ i ) and a register (R i ) are combined into one processing element (P).
It can also be realized by the pipeline method considered as E). Furthermore,
It can also be realized by sequential or parallel processing by software, comprising a multiplier (× B i ), a full adder (+ i ) and a memory having a plurality of areas.
【0022】尚、本発明は、複数の機器から構成される
システムに適用しても、1つの機器から成る装置に適用
しても良い。また、本発明はシステム或は装置にプログ
ラムを供給することによつて達成される場合にも適用で
きることは言うまでもない。The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.
【0023】[0023]
【発明の効果】本発明により、乗算回路において大きな
桁数の入力値を分割して演算する場合に、小さな桁数の
乗算器を用いて桁上がりを考慮した効率的な整数上の乗
算回路及び乗算方法を提供できる。According to the present invention, when an input value having a large number of digits is divided and operated in a multiplying circuit, a multiplier having a small number of digits is used, and an efficient integer multiplication circuit considering a carry is provided. A multiplication method can be provided.
【図1】本実施例の整数上の乗算回路を示す図である。FIG. 1 is a diagram showing an integer multiplication circuit according to the present embodiment.
【図2】公知のガロア体上の多項式の乗算回路を示す図
である。FIG. 2 is a diagram illustrating a known polynomial multiplication circuit on a Galois field.
R…2m+1ビツトのレジスタ、+…フルアダー、×B
i …Bi (i=0…n−1)を乗数としたmビツト×m
ビツトの整数上の乗算器、*Bi …Bi (i=0…n−
1)を乗数としたmビツト×mビツトのガロア体上の乗
算器、EX…mビツトのEXOR、r…mビツトのレジ
スタR ... 2m + 1 bit register, + ... Full adder, × B
m bit xm where i ... Bi (i = 0 ... n-1) is a multiplier
Multiplier on bit integer, * B i ... B i (i = 0 ... n-
1) multiplier with m bits x m bits Galois field multiplier, EX ... m bits EXOR, r ... m bits register
Claims (4)
(n×m)ビツトの整数Aと(h×m)ビツトの整数B
との乗算を行う整数上の乗算回路であつて、 整数Aがmビツト毎にnクロツクに分けて上位桁から入
力され、該整数Aの各mビツトに整数Bの所定のmビツ
トを乗算する前記整数Aに対して並列につながれるmビ
ツト×mビツトの乗算器と、 該乗算器の出力と、1つ下位桁のキヤリー付き2mビツ
トフルアダーの前回のクロツク時の出力の下位2mビツ
トと、3つ下位桁の前記キヤリー付き2mビツトフルア
ダーの前回のクロツク時の出力のキヤリービツトとを加
算する、前記乗算器に対応して各1つと最終段に更に1
つとの1次元状に並べられた前記キヤリー付き2mビツ
トのフルアダーと、 前記キヤリー付き2mビツトフルアダーの2m+1ビツ
トの出力を同時に入出力する、前記2つのキヤリー付き
2mビツトフルアダー間につながれるレジスタとを備
え、 クロツクに同期して最上位の前記キヤリー付き2mビツ
トフルアダーから乗算結果A・Bを上位桁より出力する
ことを特徴とする整数上の乗算回路。1. When h, m, and n are positive integers,
(N × m) bit integer A and (h × m) bit integer B
A multiplication circuit on an integer for multiplying with, the integer A is divided into n clocks for every m bits and inputted from the upper digit, and each m bit of the integer A is multiplied by a predetermined m bit of the integer B. An m-bit × m-bit multiplier connected in parallel to the integer A, an output of the multiplier, and a lower-order 2m-bit of the output at the last clock of the 2m-bit full adder with one lower digit carrier. Adds the carry bit of the output from the previous clock of the 2m bit full adder with the carrier of the three lower digits, one for each of the multipliers and one more for the final stage
A register connected between the two 2m bit-full adders with a carrier for simultaneously inputting and outputting the 2m bit-full adder with a carrier and the 2m + 1 bit output of the 2m bit-full adder with a carrier And a multiplication circuit on an integer, which outputs the multiplication results A and B from the upper digit from the highest 2m bit full adder with a carrier in synchronization with the clock.
前記mビツト×mビツトの乗算器に対応するキヤリー付
き2mビツトフルアダーが、削除されることを特徴とす
る請求項1記載の整数上の乗算回路。2. A 2m bit full adder with a carrier corresponding to the m bit × m bit multiplier for multiplying the m bit of the least significant digit of the integer B is deleted. Multiply circuit on integer.
2入力フルアダーまたはハーフアダーによつて実現され
ることを特徴とする請求項1記載の整数上の乗算回路。3. The multiplication circuit on an integer according to claim 1, wherein the carrier-added full adder is realized by a plurality of 2-input full adders or half adders.
(n×m)ビツトの整数Aと(h×m)ビツトの整数B
との乗算を行う整数上の乗算方法であつて、 mビツト×mビツトの乗算器と、キヤリー付き2mビツ
トフルアダーと、該フルアダーの出力を記憶する整数B
の桁に対応してアドレス配置される複数領域を有する少
なくとも2m+1ビツトのメモリとを備え、 (A) 整数Aのn分割されたmビツト(Ai )と整数Bの
h分割されたmビツト(Bj )とを前記mビツト×mビ
ツトの乗算器で乗算する行程と、 (B) 乗算結果と前記メモリの所定領域(Rj-1 )の下位
2mビツトと所定領域(Rj-3 )の2m+1ビツト目と
を前記フルアダーで加算する行程と、 (C) 加算結果を前記メモリの所定領域(Ri )に記憶す
る行程とを備え、 前記行程(A) 〜(C) を各Ai(i=n−1,n−2,…,
0の順)について、B j のjをn−1から0まで変化さ
せて繰り返し、各Ai についてBn-1 の行程が終了後の
前記メモリの所定領域(Rn-1 )の下位2m+1ビツト
と所定領域(R n-2 )の2m+1ビツト目と所定領域
(Rn-3 )の2m+1ビツト目とを前記フルアダーで加
算した結果を乗算結果A・Bの上位桁よりの出力するこ
とを特徴とする整数上の乗算方法。4. When h, m, and n are positive integers,
(N × m) bit integer A and (h × m) bit integer B
An integer multiplication method for multiplying with m bit x m bit multiplier and 2m bit with carrier
Full adder and an integer B that stores the output of the full adder
A small number of areas with addresses arranged corresponding to the digits of
It has at least 2m + 1 bits of memory, and (A) m bits divided by n of integer A (Ai ) And the integer B
h divided m bits (Bj ) And the above m bits x m bits
Step of multiplying by the multiplier of the bridge, (B) multiplication result and a predetermined area (Rj-1 ) Lower
2m bit and predetermined area (Rj-3 ) 2m + 1 bit eyes
With the full adder, and (C) the addition result is stored in a predetermined area (R) of the memory.i )
And the above steps (A) to (C)i(i = n-1, n-2, ...,
0 order), B j Of j is changed from n-1 to 0
Let's repeat, each Ai About Bn-1 After the process of
Predetermined area (Rn-1 ) Lower 2m + 1 bit
And predetermined area (R n-2 ) 2m + 1 bit and predetermined area
(Rn-3 ) 2m + 1 bit eyes with the full adder
The result of the calculation can be output from the upper digit of the multiplication result A / B.
A method of multiplication over integers characterized by and.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4167082A JPH0612235A (en) | 1992-06-25 | 1992-06-25 | Circuit and method for multiplication over integer |
EP93304879A EP0576262B1 (en) | 1992-06-25 | 1993-06-23 | Apparatus for multiplying integers of many figures |
DE69329260T DE69329260T2 (en) | 1992-06-25 | 1993-06-23 | Device for multiplying integers by many digits |
US08/512,620 US5524090A (en) | 1992-06-25 | 1995-08-08 | Apparatus for multiplying long integers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4167082A JPH0612235A (en) | 1992-06-25 | 1992-06-25 | Circuit and method for multiplication over integer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0612235A true JPH0612235A (en) | 1994-01-21 |
Family
ID=15843076
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4167082A Withdrawn JPH0612235A (en) | 1992-06-25 | 1992-06-25 | Circuit and method for multiplication over integer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0612235A (en) |
-
1992
- 1992-06-25 JP JP4167082A patent/JPH0612235A/en not_active Withdrawn
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