JPH06112927A - Time division transmission circuit - Google Patents
Time division transmission circuitInfo
- Publication number
- JPH06112927A JPH06112927A JP26097292A JP26097292A JPH06112927A JP H06112927 A JPH06112927 A JP H06112927A JP 26097292 A JP26097292 A JP 26097292A JP 26097292 A JP26097292 A JP 26097292A JP H06112927 A JPH06112927 A JP H06112927A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- transmission
- slave
- data
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Bidirectional Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は時分割データ伝送回路に
関し、特にデータ伝送回路の等化器回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division data transmission circuit, and more particularly to an equalizer circuit for a data transmission circuit.
【０００２】[0002]
【従来の技術】従来この種の時分割データ伝送回路で
は、データ通信距離（伝送路）が長い場合でも、安定に
データ伝送を行うため主データ送受信回路（以後マスタ
回路という）側に、従データ送受信回路（以後スレーブ
回路という）から到着する従データをコンデンサおよび
抵抗器にて積分し、この出力に応じて、常にスレーブ側
から到着する従データが適正レベルになるよう制御する
等価器回路を用いていた。2. Description of the Related Art Conventionally, in this type of time-division data transmission circuit, even if the data communication distance (transmission path) is long, in order to perform stable data transmission, the main data transmission / reception circuit (hereinafter referred to as the master circuit) has a sub-data transmission side. Uses an equalizer circuit that integrates slave data arriving from the transmitter / receiver circuit (hereinafter referred to as slave circuit) with a capacitor and a resistor, and controls the slave data always arriving from the slave side to an appropriate level according to this output. Was there.
【０００３】[0003]
【発明が解決しようとする課題】この従来の時分割デー
タ伝送回路では、スレーブ回路側から到着する従データ
をコンデンサおよび抵抗器で積分していたため収束する
までの時間が長くなり、同期確立に時間を要し、装置の
立上り時間が長くなるという欠点があった。また、スレ
ーブ回路側から到着する従データが、変化のないデータ
（０，０，０または１，１，１等）の場合、異常動作す
るという欠点があった。In this conventional time-division data transmission circuit, since the slave data arriving from the slave circuit side is integrated by the capacitor and the resistor, it takes a long time to converge and it takes time to establish synchronization. Therefore, there is a drawback that the rise time of the device becomes long. Further, when the slave data arriving from the slave circuit side is data that does not change (0, 0, 0 or 1, 1, 1 etc.), there is a drawback that abnormal operation occurs.
【０００４】本発明の目的は、伝送遅延時間を検出し、
スレーブ回路側からの受信データを一定電圧レベルに保
持し、装置の早期立上げ、安定動作する時分割伝送回路
を提供することにある。An object of the present invention is to detect transmission delay time,
An object of the present invention is to provide a time-division transmission circuit that holds received data from the slave circuit side at a constant voltage level, starts up the device early, and operates stably.
【０００５】[0005]
【課題を解決するための手段】本発明の時分割伝送回路
は、主データ送受信回路と従データ送受信回路との間で
データの送受信を行う時分割伝送回路において、前記主
データ送受信回路側に、前記主データ送信終了後から前
記従データ送受信回路側から前記従データ到着までの時
間を検出する伝送遅延時間検出回路と、この伝送遅延時
間検出回路の出力に応じて前記従データ送受信回路側か
ら到着した前記従データが常に適正な電圧レベルになる
ように制御する等化器回路とを有る。また前記遅延時間
検出回路の出力を通信距離に変換する遅延時間／距離変
換回路と、この変換した通信距離出力を表示する表示回
路とを有する。A time division transmission circuit of the present invention is a time division transmission circuit for transmitting and receiving data between a main data transmission / reception circuit and a slave data transmission / reception circuit, wherein the main data transmission / reception circuit side is provided with: A transmission delay time detection circuit that detects the time from the end of the transmission of the main data until the arrival of the sub data from the sub data transmission / reception circuit side, and an arrival from the sub data transmission / reception circuit side according to the output of the transmission delay time detection circuit. And an equalizer circuit for controlling the slave data so that it always has an appropriate voltage level. Further, it has a delay time / distance conversion circuit for converting the output of the delay time detection circuit into a communication distance and a display circuit for displaying the converted communication distance output.
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の一実施例を示すブロック図である。
本実施例は、主データ送信終了時から従データ到着まで
の時間を検出する伝送遅延時間検出回路１０と、この検
出出力に応じてスレーブ側から受信した従データを適正
レベルに制御する等化器回路と、伝送遅延時間検出回路
の検出出力を通信距離に変換する遅延時間／距離変換回
路１１と、変換した伝送距離を表示する表示回路１２
と、送信回路３、受信回路７を制御して時分割伝送する
タイミング回路９から構成するマスタ回路１を有してい
る。The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
In this embodiment, a transmission delay time detection circuit 10 for detecting the time from the end of main data transmission to the arrival of slave data, and an equalizer for controlling slave data received from the slave side to an appropriate level according to the detection output. Circuit, a delay time / distance conversion circuit 11 for converting the detection output of the transmission delay time detection circuit into a communication distance, and a display circuit 12 for displaying the converted transmission distance.
And a master circuit 1 including a timing circuit 9 that controls the transmission circuit 3 and the reception circuit 7 to perform time division transmission.
【０００７】マスタ回路１の送信データ入力端子２に入
力された送信データは（主データ）、送信回路３，トラ
ンス４，伝送路１３を介してスレーブ回路５に送出され
る。一方スレーブ回路５から送出された従データは、伝
送路１３を介してマスタ回路１に到着し、トランス４，
等価器回路６，受信回路７を介して受信データ出力端子
８に出力される。またタイミング回路９は送信回路３お
よび受信回路７を制御し、時分割伝送を実現する。この
とき、伝送遅延時間検出回路１０は、送信回路３が主デ
ータ送出終了後から、スレーブ回路５から従データが到
着するまでの時間を検出している。この時間が大きい場
合は、伝送路１３の長さが長くしたがって、伝送路１３
の損失も大きくなり、また逆の場合には、損失は小さく
なる。The transmission data (main data) input to the transmission data input terminal 2 of the master circuit 1 is sent to the slave circuit 5 via the transmission circuit 3, the transformer 4 and the transmission line 13. On the other hand, the slave data sent from the slave circuit 5 arrives at the master circuit 1 via the transmission line 13 and is transferred to the transformer 4,
It is output to the reception data output terminal 8 via the equalizer circuit 6 and the reception circuit 7. The timing circuit 9 controls the transmission circuit 3 and the reception circuit 7 to realize time division transmission. At this time, the transmission delay time detection circuit 10 detects the time from the end of the transmission of the main data by the transmission circuit 3 to the arrival of the slave data from the slave circuit 5. When this time is long, the length of the transmission line 13 is long, and therefore the transmission line 13
The loss will also increase, and vice versa.
【０００８】よって等価器回路６は、伝送遅延時間検出
回路１０の出力（時間）が大きい場合は増幅度を増大す
る方向に、また出力（時間）が小さい場合は、増幅度を
減少する方向に動作させることにより、スレーブ回路５
から到着した従データは常に一定の電圧レベルを保つこ
とになる。Therefore, the equalizer circuit 6 tends to increase the amplification degree when the output (time) of the transmission delay time detection circuit 10 is large, and decreases the amplification degree when the output (time) is small. Slave circuit 5 by operating
The slave data arriving from will always maintain a constant voltage level.
【０００９】また伝送遅延時間検出回路１０の出力を、
遅延時間／距離変換回路１１により伝送路の長さに変換
し、この値を表示回路１２に表示することで、伝送路の
長さを知ることが可能となる。The output of the transmission delay time detection circuit 10 is
It is possible to know the length of the transmission line by converting it into the length of the transmission line by the delay time / distance conversion circuit 11 and displaying this value on the display circuit 12.
【００１０】[0010]
【発明の効果】以上説明したように本発明は伝送遅延時
間を検出し、この値で等価器回路を動作させスレーブ回
路からの受信データを一定電圧レベルに保持するため、
収束時間が短かく早期に装置の立上げができる。また、
データの変化が無い場合でも、安定に動作する。更に、
伝送遅延時間を伝送路の長さに変換し、これを表示させ
ることで容易に伝送路の長さを知ることができる。As described above, the present invention detects the transmission delay time, operates the equalizer circuit with this value, and holds the received data from the slave circuit at a constant voltage level.
The convergence time is short and the equipment can be started up quickly. Also,
It operates stably even when there is no change in data. Furthermore,
The length of the transmission line can be easily known by converting the transmission delay time into the length of the transmission line and displaying it.
【図１】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.
【符号の説明】 １ マスタ回路 ２ 送信データ入力端子 ３ 送信回路 ４ トランス ５ スレーブ回路 ６ 等化器回路 ７ 受信回路 ８ 受信データ出力端子 ９ タイミング回路 １０ 伝送遅延検出回路 １１ 遅延時間／距離変換回路 １２ 表示回路 １３ 伝送路[Explanation of Codes] 1 master circuit 2 transmission data input terminal 3 transmission circuit 4 transformer 5 slave circuit 6 equalizer circuit 7 reception circuit 8 reception data output terminal 9 timing circuit 10 transmission delay detection circuit 11 delay time / distance conversion circuit 12 Display circuit 13 Transmission line
Claims (2)
路との間でデータの送受信を行う時分割伝送回路におい
て、前記主データ送受信回路側に、前記主データ送信終
了後から前記従データ送受信回路側から前記従データ到
着までの時間を検出する伝送遅延時間検出回路と、この
伝送遅延時間検出回路の出力に応じて前記従データ送受
信回路側から到着した前記従データが常に適正な電圧レ
ベルになるように制御する等化器回路とを有ることを特
徴とする時分割伝送回路。1. A time-division transmission circuit for transmitting and receiving data between a main data transmission / reception circuit and a slave data transmission / reception circuit, wherein the main data transmission / reception circuit side is provided with the sub data transmission / reception circuit side after completion of the main data transmission. Transmission delay time detecting circuit for detecting the time from the arrival of the slave data to the slave data, and the slave data arriving from the slave data transmitting / receiving circuit side in accordance with the output of the transmission delay time detecting circuit is always at an appropriate voltage level. And an equalizer circuit for controlling the time division transmission circuit.
に変換する遅延時間／距離変換回路と、この変換した通
信距離出力を表示する表示回路とを有することを特徴と
する請求項１記載の時分割伝送回路。2. A delay time / distance conversion circuit for converting the output of the delay time detection circuit into a communication distance, and a display circuit for displaying the converted communication distance output. Time division transmission circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26097292A JPH06112927A (en) | 1992-09-30 | 1992-09-30 | Time division transmission circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26097292A JPH06112927A (en) | 1992-09-30 | 1992-09-30 | Time division transmission circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06112927A true JPH06112927A (en) | 1994-04-22 |
Family
ID=17355313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26097292A Withdrawn JPH06112927A (en) | 1992-09-30 | 1992-09-30 | Time division transmission circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06112927A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011061593A (en) * | 2009-09-11 | 2011-03-24 | Fujitsu Ltd | Transmission line measuring apparatus, measuring method and computer program |
-
1992
- 1992-09-30 JP JP26097292A patent/JPH06112927A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011061593A (en) * | 2009-09-11 | 2011-03-24 | Fujitsu Ltd | Transmission line measuring apparatus, measuring method and computer program |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19991130 |