JPH06112861A - Digital system communication terminal equipment - Google Patents
Digital system communication terminal equipmentInfo
- Publication number
- JPH06112861A JPH06112861A JP4285322A JP28532292A JPH06112861A JP H06112861 A JPH06112861 A JP H06112861A JP 4285322 A JP4285322 A JP 4285322A JP 28532292 A JP28532292 A JP 28532292A JP H06112861 A JPH06112861 A JP H06112861A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- signal
- signal processing
- processing section
- reference oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Transceivers (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、送受信装置即ち高周
波信号処理部とそれに接続するベ−スバンド信号処理装
置とを備えるデジタル方式通信端末に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication terminal equipped with a transmitting / receiving device, that is, a high frequency signal processing section and a base band signal processing apparatus connected thereto.
【０００２】[0002]
【従来の技術】ＴＤＭＡ−ＴＤＤ(Time Division Multi
ple Access-Time Division Duplex)方式の通信システム
で用いられている従来の通信端末は、図２に示すよう
に、大きく分けると高周波信号処理部とベ−スバンド信
号処理部とに分けられる回路構成となっている。この回
路において、受信信号はアンテナ１により検出されて高
周波用帯域フィルタ２、アンテナスイッチ３、受信用低
雑音増幅器４を経て混合回路５に与えられる。混合回路
５は受信用低雑音増幅器４からの受信信号に電圧制御発
振器１２からの信号を混合して上記受信信号の周波数を
変換して受信用帯域フィルタ６に送る。受信用帯域フィ
ルタ６は送られてきた各種周波数の受信信号のうち所定
の周波数のものを選択的に受信用増幅器７に送る。受信
用増幅器７は上記所定周波数の受信信号のみを選択的に
増幅してＡ／Ｄコンバ−タ２１に送る。Ａ／Ｄコンバ−
タ２１に送られた受信信号は、このＡ／Ｄコンバ−タ２
１でデジタル信号に変換されて、ＴＤＭＡ信号処理部２
２で連続デ−タに復元され、音声コ−デック部２３で伸
長され、Ｄ／Ａコンバ−タ２４でアナログ音声信号に戻
されてスピーカ２５へ出力される。一方、マイクロホン
２６に入力された音声入力信号は、Ａ／Ｄコンバ−タ２
７でデジタルデ−タ化され、音声コ−デック部２３で圧
縮処理が施され、ＴＤＭＡ信号処理部２２でバ−スト信
号にされＤ／Ａコンバ−タ２８でアナログ信号化されて
ベ−スバンド信号としてデジタル変調用直交変調器１４
に送出される。上記ベ−スバンド信号は、デジタル変調
用直交変調器１４で直交変調により中間周波数帯の信号
に変換され送信スプリアス抑圧用帯域フィルタ１５を経
て混合回路１６に送られる。そして、混合回路１６で
は、電圧制御発振器１２からの信号が混合されて一定の
高周波の信号に変換され、次の送信用電力増幅器１７で
電力増幅がなされて、アンテナスイッチ３、高周波用帯
域フィルタ２を経てアンテナ１に供給される。また、位
相比較器１０、ル−プフィルタ１１、前記電圧制御発振
器１２及びプログラマブル分周器１３は混合回路５、１
６に局部発振周波数信号を与えるＰＰＬ（Phase Locked
Loop）型シンセサイザ−を構成しており、このＰＰＬ
型シンセサイザ−の位相比較器１０には基準発振器８か
らの周波数ｆ1の信号をプログラマブル分周器９で分周
して周波数をｆrefにした信号が被比較入力信号として
与えられている。そして、ベ−スバンド信号処理部の基
準発振器２９は、このベ−スバンド信号処理部のデジタ
ルデ−タ転送速度に対応した周波数の信号ｆ2を送出す
る。即ち、このようなデジタル方式通信端末では、高周
波信号処理部及びベ−スバンド信号処理部に、それぞれ
１個の基準発振器８及び２９が設けられており、全体と
しては２個の基準発振器が備えられている。2. Description of the Related Art TDMA-TDD (Time Division Multi
As shown in FIG. 2, a conventional communication terminal used in a ple Access-Time Division Duplex) communication system is roughly divided into a high frequency signal processing section and a baseband signal processing section. Has become. In this circuit, the received signal is detected by the antenna 1 and given to the mixing circuit 5 via the high frequency band filter 2, the antenna switch 3, and the receiving low noise amplifier 4. The mixing circuit 5 mixes the reception signal from the reception low noise amplifier 4 with the signal from the voltage controlled oscillator 12 to convert the frequency of the reception signal and sends it to the reception band filter 6. The receiving band-pass filter 6 selectively sends to the receiving amplifier 7 a signal having a predetermined frequency among the received signals having various frequencies. The receiving amplifier 7 selectively amplifies only the received signal of the above-mentioned predetermined frequency and sends it to the A / D converter 21. A / D converter
The received signal sent to the converter 21 is the A / D converter 2
1 is converted into a digital signal, and the TDMA signal processing unit 2
In step 2, the audio data is restored to continuous data, expanded in the audio code section 23, converted into an analog audio signal in the D / A converter 24, and output to the speaker 25. On the other hand, the audio input signal input to the microphone 26 is the A / D converter 2
7, digital data is converted, a voice code section 23 performs compression processing, a TDMA signal processing section 22 converts it to a burst signal, and a D / A converter 28 converts it to an analog signal to generate a base band. Quadrature modulator 14 for digital modulation as a signal
Sent to. The base band signal is converted into a signal in the intermediate frequency band by quadrature modulation by the quadrature modulator 14 for digital modulation, and is sent to the mixing circuit 16 through the band filter 15 for suppressing transmission spurious. Then, in the mixing circuit 16, the signals from the voltage controlled oscillator 12 are mixed and converted into a constant high-frequency signal, and the power is amplified by the next transmission power amplifier 17, and the antenna switch 3 and the high-frequency bandpass filter 2 are supplied. It is supplied to the antenna 1 via. Further, the phase comparator 10, the loop filter 11, the voltage controlled oscillator 12 and the programmable frequency divider 13 are mixed circuits 5 and 1, respectively.
PPL (Phase Locked) that gives a local oscillation frequency signal to 6
Loop) type synthesizer, and this PPL
To the phase comparator 10 of the type synthesizer, a signal having a frequency f 1 from the reference oscillator 8 is frequency-divided by the programmable frequency divider 9 to be f ref , which is given as a compared input signal. Then, the reference oscillator 29 of the baseband signal processing section sends out a signal f 2 having a frequency corresponding to the digital data transfer rate of the baseband signal processing section. That is, in such a digital communication terminal, the high frequency signal processing section and the base band signal processing section are provided with one reference oscillator 8 and 29, respectively, and two reference oscillators are provided as a whole. ing.
【０００３】[0003]
【発明が解決しようとする課題】上述のように、従来の
デジタル方式通信端末には２個の基準発振器が備えられ
ているが、これはデジタル方式通信端末の小型化の阻害
要因となり、また消費電力の増加を招き、更に携帯用の
小型のデジタル方式通信端末における両基準発振器間の
干渉と言った問題を招いている。As described above, the conventional digital communication terminal is provided with two reference oscillators, which is an obstacle to the downsizing of the digital communication terminal and consumes more. This causes an increase in electric power and causes a problem called interference between both reference oscillators in a small portable digital communication terminal.
【０００４】本発明は上述の事情に鑑みてなされたもの
であり、２個の基準発振器が備えられていることによる
小型化の阻害、消費電力の増加、両基準発振器間の干渉
と言った問題を回避できるデジタル方式通信端末の提供
を目的とする。The present invention has been made in view of the above-mentioned circumstances, and problems such as obstruction of miniaturization, increase in power consumption, and interference between both reference oscillators due to the provision of two reference oscillators. It is an object of the present invention to provide a digital communication terminal capable of avoiding the above.
【０００５】[0005]
【課題を解決するための手段】本発明は、上記目的を達
成するために、デジタル方式通信システムのチャネル間
隔周波数或いはその整数分の１の周波数と、デ−タ転送
速度に対応する周波数との公倍数の周波数の信号を発生
する単一の基準発振器を設けて、この基準発振器からの
信号を利用して、高周波信号処理部のＰＬＬ型シンセサ
イザ−に与える被比較入力信号及びベ−スバンド信号処
理部のデ−タ伝送速度に対応した周波数信号を作るよう
にした。In order to achieve the above object, the present invention provides a channel interval frequency of a digital communication system or a frequency of an integer fraction thereof and a frequency corresponding to a data transfer rate. A single reference oscillator for generating a signal having a frequency of a common multiple is provided, and a signal from this reference oscillator is used to provide a compared input signal and a baseband signal processing unit to be given to a PLL synthesizer of a high frequency signal processing unit. The frequency signal corresponding to the data transmission speed of is produced.
【０００６】[0006]
【実施例】以下、図面に示す実施例に基づき本発明を具
体的に説明する。図１は本実施例の回路構成を示すもの
である。なお、同図においては、従来例を示す図２にお
ける回路部と同一のものには、同一の符号を付してい
る。図１から分かるように、本実施例は従来例を示す図
２の回路構成と概ね同様であるが、従来例に設けられて
いた発振周波数ｆ1の基準発振器８と発振周波数ｆ2の基
準発振器２９とが除かれて、換わって発振周波数ｆ0の
基準発振器３０が新たに設けられている。そして、基準
発振器３０が送出する信号の周波数ｆ0は、本実施例が
用いられるデジタル方式通信システムのチャネル間隔周
波数ｆrefと、ベ−スバンド信号処理部のデ−タ転送速
度に対応する周波数ｆ2との最小公倍数の周波数となっ
ている。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the embodiments shown in the drawings. FIG. 1 shows the circuit configuration of this embodiment. In the figure, the same parts as those of the circuit part in FIG. 2 showing the conventional example are designated by the same reference numerals. As can be seen from FIG. 1, this embodiment has substantially the same circuit configuration as that of the conventional example shown in FIG. 2, but the reference oscillator 8 having the oscillation frequency f 1 and the reference oscillator having the oscillation frequency f 2 provided in the conventional example are provided. 29 is removed, and a reference oscillator 30 having an oscillation frequency f 0 is newly provided instead. The frequency f 0 of the signal transmitted by the reference oscillator 30 is the frequency f corresponding to the channel interval frequency f ref of the digital communication system in which this embodiment is used and the data transfer rate of the baseband signal processing section. The frequency is the least common multiple of 2 .
【０００７】以上の如く構成された本実施例では、基準
発振器３０からの周波数ｆ0の信号はプログラマブル分
周器９に与えられて、このプログラマブル分周器９でチ
ャネル間隔周波数ｆrefにまで分周されて位相比較器１
０に被比較入力信号として送出される。これにより電圧
制御発振器１２からはチャネル間隔周波数ｆrefの整数
倍（図示しない制御部からの制御信号に基づくプログラ
マブル分周器１３の分周が周波数を１／Ｎにするもので
あるときにはＮ倍）の信号が混合回路５又は１６に送出
されて、指定されたチャネルでの通信が行えることにな
る。また、基準発振器３０からの周波数ｆ0の信号は、
図示しない分周器により分周されてベ−スバンド信号処
理部のデ−タ転送速度に対応する周波数ｆ2のクロック
信号となり、このベ−スバンド信号処理部の各回路部に
送られる。In the present embodiment configured as described above, the signal of the frequency f 0 from the reference oscillator 30 is given to the programmable frequency divider 9 and divided by this programmable frequency divider 9 to the channel interval frequency f ref. Phase comparator 1
It is sent to 0 as a compared input signal. As a result, the voltage controlled oscillator 12 outputs an integral multiple of the channel interval frequency f ref (N times when the frequency division of the programmable frequency divider 13 based on a control signal from a control unit (not shown) makes the frequency 1 / N). Is sent to the mixing circuit 5 or 16 to enable communication on the designated channel. Further, the signal of frequency f 0 from the reference oscillator 30 is
It is frequency-divided by a frequency divider (not shown) to become a clock signal of frequency f 2 corresponding to the data transfer rate of the baseband signal processing section, and is sent to each circuit section of this baseband signal processing section.
【０００８】なお、本願発明は、上記実施例に限定され
ず、本願発明を逸脱しない範囲において種々変形応用可
能である。例えば、上記実施例では、基準発振器３０が
送出する信号の周波数ｆ0を、チャネル間隔周波数ｆref
とベ−スバンド信号処理部のデ−タ転送速度に対応する
周波数ｆ2との最小公倍数の周波数としたが、これを最
小ではない公倍数の周波数、或いはチャネル間隔周波数
ｆrefの整数分の１と上記周波数ｆ2との公倍数の周波数
とし、その上で、プログラマブル分周器９、１３及びベ
−スバンド信号処理部の前記分周器の分周率を調節し
て、電圧制御発振器１２からはチャネル間隔周波数ｆ
refの整数倍の信号、ベ−スバンド信号処理部の前記分
周器からは周波数ｆ2のクロック信号をそれぞれ送出す
るようにしてもよいことは勿論である。The invention of the present application is not limited to the above-described embodiment, and various modifications and applications are possible without departing from the invention of the present application. For example, in the above embodiment, the frequency f 0 of the signal transmitted by the reference oscillator 30 is set to the channel interval frequency f ref.
The frequency is the least common multiple of the frequency f 2 corresponding to the data transfer rate of the base band signal processing unit. However, this is not the lowest common multiple frequency, or an integer fraction of the channel interval frequency f ref. A frequency that is a common multiple of the frequency f 2 is set, and then the frequency division ratios of the programmable frequency dividers 9 and 13 and the frequency divider of the baseband signal processing unit are adjusted so that the channel from the voltage controlled oscillator 12 is adjusted. Interval frequency f
It goes without saying that a signal of an integral multiple of ref and a clock signal of frequency f 2 may be respectively sent from the frequency divider of the baseband signal processing section.
【発明の効果】以上詳述したように、この発明は、デジ
タル方式通信システムのチャネル間隔周波数或いはその
整数分の１の周波数と、デ−タ転送速度に対応する周波
数との公倍数の周波数の信号を発生する単一の基準発振
器を設けて、この基準発振器からの信号を利用して、高
周波信号処理部のＰＬＬ型シンセサイザ−に与える被比
較入力信号及びベ−スバンド信号処理部のデ−タ伝送速
度に対応した周波数信号を作るようにしたデジタル方式
通信端末に係るものだから、２個の基準発振器が備えら
れている場合の小型化の阻害、消費電力の増加、両基準
発振器間の干渉と言った問題を回避できるデジタル方式
通信端末の提供を可能とする。As described above in detail, the present invention provides a signal having a frequency that is a common multiple of the channel interval frequency of the digital communication system or a frequency of an integer fraction thereof and the frequency corresponding to the data transfer rate. A single reference oscillator for generating a signal is used, and a signal from this reference oscillator is used to transmit a compared input signal to the PLL synthesizer of the high-frequency signal processing section and data transmission of the baseband signal processing section. Since it relates to a digital communication terminal that produces a frequency signal corresponding to the speed, it is called an obstacle to miniaturization when two reference oscillators are provided, an increase in power consumption, and interference between both reference oscillators. It is possible to provide a digital communication terminal capable of avoiding the above problems.
【図１】本願発明の一実施例の回路構成を示す図。FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention.
【図２】従来例を示す図FIG. 2 is a diagram showing a conventional example.
１ アンテナ ２ 高周波用帯域フィルタ ３ アンテナスイッチ ４ 受信用低雑音増幅器 ５ 混合回路 ６ 受信用帯域フィルタ ７ 受信用増幅器 ８ 基準発振器 ９ プログラマブル分周器 １０ 位相比較器 １１ ル−プフィルタ １２ 電圧制御発振器 １３ プログラマブル分周器 １４ デジタル変調用直交変調器 １５ 送信スプリアス抑圧用帯域フィルタ １６ 混合回路 １７ 送信用電力増幅器 ２１ Ａ／Ｄコンバ−タ ２２ ＴＤＭＡ信号処理部 ２３ 音声コ−デック部 ２４ Ｄ／Ａコンバ−タ ２５ スピーカ ２６ マイクロホン ２７ Ａ／Ｄコンバ−タ ２８ Ｄ／Ａコンバ−タ ２９ 基準発振器 ３０ 基準発振器 1 antenna 2 high frequency band filter 3 antenna switch 4 receiving low noise amplifier 5 mixing circuit 6 receiving band filter 7 receiving amplifier 8 reference oscillator 9 programmable frequency divider 10 phase comparator 11 loop filter 12 voltage controlled oscillator 13 programmable Frequency divider 14 Quadrature modulator for digital modulation 15 Band filter for transmission spurious suppression 16 Mixing circuit 17 Power amplifier for transmission 21 A / D converter 22 TDMA signal processing section 23 Voice codec section 24 D / A converter 25 Speaker 26 Microphone 27 A / D Converter 28 D / A Converter 29 Reference Oscillator 30 Reference Oscillator
Claims (2)
置と、これに接続するベ−スバンド信号処理部とを備え
るデジタル方式通信端末において、 デジタル方式通信システムのチャネル間隔周波数と、ベ
−スバンド信号処理部のデ−タ転送速度に対応する周波
数との公倍数の周波数の信号を発生する単一の基準発振
器を設け、 この基準発振器からの信号を利用して、送受信装置のＰ
ＬＬ型シンセサイザ−に与える被比較入力信号及びベ−
スバンド信号処理部のデ−タ伝送速度に対応した周波数
信号を作るようにしたデジタル方式通信端末。1. A digital communication terminal comprising a transmitter / receiver having a PLL synthesizer and a baseband signal processing section connected to the transmitter / receiver, wherein a channel interval frequency of the digital communication system and baseband signal processing are provided. A single reference oscillator that generates a signal having a frequency that is a common multiple of the frequency corresponding to the data transfer speed of the unit is provided, and the signal from this reference oscillator is used to generate the P
An input signal to be compared and a base applied to the LL type synthesizer
A digital communication terminal adapted to generate a frequency signal corresponding to the data transmission speed of a band signal processing unit.
置と、これに接続するベ−スバンド信号処理部とを備え
るデジタル方式通信端末において、 デジタル方式通信システムのチャネル間隔周波数の整数
分の１の周波数と、ベ−スバンド信号処理部のデ−タ転
送速度に対応する周波数との公倍数の周波数の信号を発
生する単一の基準発振器を設け、 この基準発振器からの信号を利用して、送受信装置のＰ
ＬＬ型シンセサイザ−に与える被比較入力信号及びベ−
スバンド信号処理部のデ−タ伝送速度に対応した周波数
信号を作るようにしたデジタル方式通信端末。2. A digital communication terminal comprising a transmitter / receiver having a PLL synthesizer and a baseband signal processing section connected to the transmitter / receiver, wherein a frequency which is an integer fraction of a channel interval frequency of the digital communication system. And a single reference oscillator that generates a signal of a frequency that is a common multiple of the frequency corresponding to the data transfer rate of the baseband signal processing unit is provided, and the signal from this reference oscillator is used to P
An input signal to be compared and a base applied to the LL type synthesizer
A digital communication terminal adapted to generate a frequency signal corresponding to the data transmission speed of a band signal processing unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4285322A JPH06112861A (en) | 1992-09-30 | 1992-09-30 | Digital system communication terminal equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4285322A JPH06112861A (en) | 1992-09-30 | 1992-09-30 | Digital system communication terminal equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06112861A true JPH06112861A (en) | 1994-04-22 |
Family
ID=17690046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4285322A Pending JPH06112861A (en) | 1992-09-30 | 1992-09-30 | Digital system communication terminal equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06112861A (en) |
-
1992
- 1992-09-30 JP JP4285322A patent/JPH06112861A/en active Pending
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