JPH06112237A - Assembly method for semiconductor device - Google Patents
Assembly method for semiconductor deviceInfo
- Publication number
- JPH06112237A JPH06112237A JP25782792A JP25782792A JPH06112237A JP H06112237 A JPH06112237 A JP H06112237A JP 25782792 A JP25782792 A JP 25782792A JP 25782792 A JP25782792 A JP 25782792A JP H06112237 A JPH06112237 A JP H06112237A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- semiconductor chip
- lead frame
- chip
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体チップをリー
ドフレームに半田を用いてボンディングする半導体装置
の組立方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of assembling a semiconductor device in which a semiconductor chip is bonded to a lead frame by using solder.
【０００２】[0002]
【従来の技術】従来の半導体装置（半導体チップ）のボ
ンディングについて、図面を参照しながら説明する。半
導体チップのボンディングについては、２種類の方法が
一般に行われている。図３に半導体チップと相互拡散に
よって低融点の共晶合金を形成するような金属箔を用い
るボンディングの例を示す。図３において、１はリード
フレーム、４は金属箔、３は半導体チップ、５は共晶層
である。この例では、図３（ａ），（ｂ）に示すよう
に、リードフレーム１に金属箔４を重ね、その上に半導
体チップ３を載せて加熱することにより、リードフレー
ム１に共晶層５を介して半導体チップ３をボンディング
する。この場合、金属箔４としてはＡｕ系のものを用
い、Ａｕ−Ｓｉの共晶合金を作りボンディングする。2. Description of the Related Art Conventional bonding of a semiconductor device (semiconductor chip) will be described with reference to the drawings. Two methods are generally used for bonding semiconductor chips. FIG. 3 shows an example of bonding using a metal foil that forms a eutectic alloy with a low melting point by mutual diffusion with a semiconductor chip. In FIG. 3, 1 is a lead frame, 4 is a metal foil, 3 is a semiconductor chip, and 5 is a eutectic layer. In this example, as shown in FIGS. 3A and 3B, the eutectic layer 5 is formed on the lead frame 1 by stacking the metal foil 4 on the lead frame 1 and placing the semiconductor chip 3 thereon and heating it. The semiconductor chip 3 is bonded via the. In this case, an Au-based material is used as the metal foil 4, and an Au-Si eutectic alloy is formed and bonded.
【０００３】以上のようなＡｕ−Ｓｉの共晶合金を作っ
てボンディングすることが、現在最も一般的な方法であ
る。しかし、Ａｕ系の材料を用いる限り、コストの低減
は期待できない。また、Ａｕ系の材料を用いる場合は、
硬質であるので、熱ストレスの影響で接合部にクラック
が発生しやすい。このような共晶合金を利用する方法に
対し、図４にＰｂ系の半田ワイヤを溶融してリードフレ
ーム上に供給し、熱圧着によってボンディングする例を
示す。図４において、６は半田ワイヤ、６′はリードフ
レーム１上に載せられた溶融半田である。この例では、
図４（ａ）に示すように、リードフレーム１の上方から
半田ワイヤ６を垂らしてリードフレーム１に接触させ、
これによって、半田ワイヤ６の先端部を溶融してリード
フレーム１の上に堆積させ、図４（ｂ）に示すように、
裏面に金属電極９を被着した半導体チップ３をリードフ
レーム１の溶融半田６′上に載せることで、半導体チッ
プ３をリードフレーム１にボンディングする。At present, the most general method is to make and bond the Au-Si eutectic alloy as described above. However, cost reduction cannot be expected as long as the Au-based material is used. When using Au-based material,
Since it is hard, cracks easily occur at the joint due to the effect of heat stress. In contrast to the method using such a eutectic alloy, FIG. 4 shows an example in which a Pb-based solder wire is melted, supplied onto a lead frame, and bonded by thermocompression bonding. In FIG. 4, 6 is a solder wire, and 6 ′ is a molten solder placed on the lead frame 1. In this example,
As shown in FIG. 4A, the solder wire 6 is hung from above the lead frame 1 to make contact with the lead frame 1,
As a result, the tip of the solder wire 6 is melted and deposited on the lead frame 1, and as shown in FIG.
The semiconductor chip 3 having the metal electrode 9 adhered on its back surface is placed on the molten solder 6 ′ of the lead frame 1 to bond the semiconductor chip 3 to the lead frame 1.
【０００４】この例では、Ｐｂ系半田は軟質であるの
で、熱により発生する半導体チップ３とリードフレーム
１との間のストレスを吸収でき、クラックが発生しにく
いメリットがある。また、Ｐｂ系半田の価格は非常に安
く、多大なコスト低減が可能である。図５に半田ペレッ
ト（または半田箔）を用いて熱圧着することによってボ
ンディングする例を示す。図５において、７は半田ペレ
ット、７′は溶融半田である。その他は図４と同様であ
る。この例では、図５（ａ），（ｂ）に示すように、リ
ードフレーム１に半田ペレット７を載せて半田ペレット
７を溶融し、溶融半田７′に裏面に金属電極９を有する
半導体チップ３を載せることにより、リードフレーム１
に半導体チップ３をボンディングする。In this example, since the Pb-based solder is soft, there is an advantage that the stress generated between the semiconductor chip 3 and the lead frame 1 can be absorbed and cracks are less likely to occur. Further, the price of Pb-based solder is very low, and a great cost reduction is possible. FIG. 5 shows an example of bonding by thermocompression bonding using a solder pellet (or a solder foil). In FIG. 5, 7 is a solder pellet and 7'is a molten solder. Others are the same as in FIG. In this example, as shown in FIGS. 5A and 5B, the solder pellet 7 is placed on the lead frame 1 to melt the solder pellet 7, and the molten solder 7 ′ has the semiconductor chip 3 having the metal electrode 9 on the back surface. By mounting the lead frame 1
The semiconductor chip 3 is bonded to.
【０００５】[0005]
【発明が解決しようとする課題】しかし、図４の方法の
場合、半田ワイヤ６をリードフレーム１に接触させるこ
とで、リードフレーム１上に溶融半田６′を適当量供給
するので、半田量のばらつきが大きく、微少制御が困難
である。そのため、小チップ半導体には、この工法を用
いることができない。なぜならば、半導体チップ３がボ
ンディング時に傾き、以降の工程に支障をきたすからで
ある。However, in the case of the method shown in FIG. 4, the solder wire 6 is brought into contact with the lead frame 1 to supply an appropriate amount of the molten solder 6 ′ onto the lead frame 1. The variation is large and it is difficult to control minutely. Therefore, this method cannot be used for small chip semiconductors. This is because the semiconductor chip 3 tilts during bonding and interferes with subsequent steps.
【０００６】また、溶融半田６′の中央にチップをのせ
る必要から、ボンディング時の位置精度の問題がある。
これらの問題があるため、チップ面積の大きいパワー品
種で実用化されているだけである。さらに、溶融半田
６′上に半導体チップ３をボンディングする時の時間の
ずれで表面温度低下によって溶融半田６′の表面に薄い
皮膜が発生し、接着不良を起こすため、この皮膜を除去
する装置が必要となる。Further, since it is necessary to place a chip on the center of the molten solder 6 ', there is a problem of positional accuracy during bonding.
Because of these problems, they are only put to practical use in power products with a large chip area. Further, due to the time lag when the semiconductor chip 3 is bonded onto the molten solder 6 ', a thin film is generated on the surface of the molten solder 6'because of the surface temperature drop, and adhesion failure occurs. Will be needed.
【０００７】また、図５に示した方法でも、上記と同様
の問題が残る。したがって、この発明の目的は、半田に
よるボンディングを小チップ品種にも支障なく適用する
ことができる半導体装置の組立方法を提供することであ
る。The method shown in FIG. 5 also has the same problem as described above. Therefore, an object of the present invention is to provide a method of assembling a semiconductor device in which solder bonding can be applied to small chip types without any problem.
【０００８】[0008]
【課題を解決するための手段】この発明の半導体装置の
組立方法は、半導体チップとリードフレームとの間の接
合ロウ材である半田を、カッティング前のウェハ状態で
前記半導体チップの金属電極を有する裏面に真空蒸着法
によって蒸着し、カッティング後熱圧着法によって前記
半導体チップを個別にリードフレームに直接ボンディン
グすることを特徴とする。In the method of assembling a semiconductor device according to the present invention, solder which is a brazing filler metal between a semiconductor chip and a lead frame has a metal electrode of the semiconductor chip in a wafer state before cutting. It is characterized in that the semiconductor chips are individually vapor-deposited on the back surface by a vacuum vapor deposition method, and are directly bonded to the lead frame by a thermocompression bonding method after cutting.
【０００９】[0009]
【作用】この発明の構成によれば、カッティング前のウ
ェハ状態で半導体チップの裏面に半導体チップとリード
フレームとの間の接合ロウ材である半田を真空蒸着法よ
って蒸着するので、蒸着膜厚制御により半田量の微少制
御が可能となり、さらにカッティング後熱圧着法によっ
て半導体チップを個別にリードフレームに直接ボンディ
ングするので、ボンディング時の半田皮膜対策、半田と
チップの位置ずれ対策ができ、半田を用いる組立工法を
小チップ品種にも適用できるようになる。According to the structure of the present invention, since solder, which is a brazing filler metal between the semiconductor chip and the lead frame, is vapor-deposited on the back surface of the semiconductor chip by the vacuum vapor deposition method in a wafer state before cutting, the vapor deposition film thickness control Enables fine control of the amount of solder, and since the semiconductor chips are individually bonded directly to the lead frame by the thermocompression bonding method after cutting, it is possible to take measures against the solder film at the time of bonding and the misalignment between the solder and the chip. The assembly method can be applied to small chip types.
【００１０】[0010]
【実施例】以下、この発明の実施例について、図面を参
照しながら説明する。以下では、半導体チップをリード
フレームにボンディングし、Ｐｂ系半田を用いる場合に
ついて説明する。この半導体装置の組立方法は、半導体
チップとリードフレームとの間の接合ロウ材である半田
を、カッティング前のウェハ状態で前記半導体チップの
金属電極を有する裏面に真空蒸着法によって蒸着し、カ
ッティング後熱圧着法によって半導体チップを個別にリ
ードフレームに直接ボンディングするという方法であ
る。Embodiments of the present invention will be described below with reference to the drawings. Hereinafter, a case where a semiconductor chip is bonded to a lead frame and Pb-based solder is used will be described. This semiconductor device is assembled by soldering solder, which is a joining brazing material between a semiconductor chip and a lead frame, in a wafer state before cutting on the back surface having the metal electrodes of the semiconductor chip by a vacuum deposition method and after cutting. This is a method of directly bonding the semiconductor chips individually to the lead frame by thermocompression bonding.
【００１１】一般に、真空蒸着法には、抵抗加熱蒸着
法，高周波加熱蒸着法，電子ビーム蒸着法およびスパッ
タ蒸着法等がある。Ｐｂ系半田のような二元系または三
元系の合金では、カッティング前のウェハ状態で半導体
チップの裏面に成膜する際、成膜中の組成変動が問題と
なる。つまり、再現性が得られにくい。それは、蒸発温
度が異なるため、均一に蒸発しないことによる。したが
って、できた半田膜は縦方向（厚み方向）に組成が異な
った膜となる。Generally, the vacuum vapor deposition method includes a resistance heating vapor deposition method, a high frequency heating vapor deposition method, an electron beam vapor deposition method and a sputter vapor deposition method. In a binary or ternary alloy such as Pb-based solder, when a film is formed on the back surface of a semiconductor chip in a wafer state before cutting, composition fluctuation during film formation becomes a problem. That is, it is difficult to obtain reproducibility. This is because the evaporation temperatures are different and the evaporation is not uniform. Therefore, the resulting solder film has a different composition in the vertical direction (thickness direction).
【００１２】しかし、蒸発源を飛ばしきる方法をとれ
ば、トータルで見た膜の組成はロット間で一定となり、
再現性が得られる。飛ばしきる方法をとる限りは、イン
ゴットの半田を用いても、半田成分をボートに入れて溶
融混合しながら飛ばしても半田特性に差はない。以上の
理由から、抵抗加熱蒸着法，高周波加熱蒸着法が本発明
の半田成膜には適当である。また、半田膜の縦方向（厚
み方向）に組成が変動していても、ボンディング時に一
度リフローされれば混ざり合い、組成変化の影響はな
い。However, if the evaporation source is blown out completely, the total composition of the film becomes constant from lot to lot.
Reproducibility is obtained. As long as the method of skipping is taken, there is no difference in the solder characteristics even if the solder of the ingot is used or the solder components are put into a boat and melted and mixed and then skipped. From the above reasons, the resistance heating vapor deposition method and the high frequency heating vapor deposition method are suitable for the solder film formation of the present invention. Further, even if the composition changes in the vertical direction (thickness direction) of the solder film, they are mixed once reflowed at the time of bonding, and there is no influence of the composition change.
【００１３】ダイスボンド後の熱サイクル条件によっ
て、目的とする融点になるように決定しなければならな
いが、半田ワイヤ，ペレット状の形成半田と同一組成で
ほぼ同等の耐久性を有する蒸着半田が得られる。例え
ば、Ｐｂ：Ｓｂ：Ａｇ＝９５．５：２：２．５で約３０
０度の融点を有する蒸着半田が得られた。図２に半導体
チップとリードフレームとの間の接合ロウ材である半田
を、ウェハ（カッティングすると半導体チップとなる）
の裏面に真空蒸着により蒸着した後、半田成膜したウェ
ハをマスキングシートに貼り付けてフルカットにした後
の断面図を示す。図２において、２は蒸着半田、８はマ
スキングシート、３は半導体チップ、９は金属電極であ
る。Although it must be determined so as to obtain a desired melting point depending on the heat cycle condition after die bonding, a vapor deposition solder having the same composition as the solder wire or the pelletized forming solder and having substantially the same durability is obtained. To be For example, Pb: Sb: Ag = 95.5: 2: 2.5 is about 30.
A vapor-deposited solder having a melting point of 0 degree was obtained. In FIG. 2, solder, which is a brazing filler metal between the semiconductor chip and the lead frame, is attached to the wafer (it becomes a semiconductor chip when cut).
FIG. 4 is a cross-sectional view after the wafer having the solder film formed thereon is attached to a masking sheet and full-cut after vapor deposition is performed on the back surface of the substrate by vacuum vapor deposition. In FIG. 2, 2 is vapor-deposited solder, 8 is a masking sheet, 3 is a semiconductor chip, and 9 is a metal electrode.
【００１４】蒸着半田２の膜厚は、チップ面積により異
なり、最大１５μｍ程度必要であるが、十分フルカット
が可能である。図１にカッティング後熱圧着法によって
半導体チップを個別にリードフレームに直接ボンディン
グするときの半導体装置の断面図を示す。この実施例で
は、半田２は、半導体チップ３全面に前もって適量形成
されているので、リードフレーム１に半導体チップ３を
載置してボンディングする際に、半導体チップ３が傾く
こともなく、ボンディング位置精度についても注意を払
う必要がなく、半田皮膜が発生することもない。The film thickness of the vapor-deposited solder 2 depends on the chip area and needs to be about 15 μm at the maximum, but a full cut can be sufficiently performed. FIG. 1 shows a cross-sectional view of a semiconductor device when semiconductor chips are individually bonded directly to a lead frame by a thermocompression bonding method after cutting. In this embodiment, since the solder 2 is formed in an appropriate amount on the entire surface of the semiconductor chip 3 in advance, when the semiconductor chip 3 is mounted on the lead frame 1 and bonded, the semiconductor chip 3 does not tilt and the bonding position There is no need to pay attention to accuracy, and no solder film is formed.
【００１５】また、この実施例のように、半導体チップ
３の裏面に半田を蒸着する方法では、組立工程中でロウ
材をいったんリードフレーム上に置く必要がないので、
生産スピードが上がる。以上のことから、小チップ品種
の半導体チップについても、半田によるボンディングを
チップの傾斜等の問題を生じることなく行うことができ
る。Further, in the method of depositing solder on the back surface of the semiconductor chip 3 as in this embodiment, it is not necessary to once place the brazing material on the lead frame during the assembly process.
Increases production speed. From the above, it is possible to perform soldering on semiconductor chips of small chip types without causing problems such as chip inclination.
【００１６】以上の説明では、半田はＰｂ系のものであ
ったが、もちろんそれ以外の成分でも蒸着可能であれ
ば、どれでもよい。例えばＡｕ−Ｓｎ系の半田でもよ
い。In the above description, the solder is Pb-based, but of course any other component may be used as long as it can be vapor-deposited. For example, Au—Sn solder may be used.
【００１７】[0017]
【発明の効果】この発明の半導体装置の組立方法によれ
ば、カッティング前のウェハ状態で半導体チップの裏面
に半導体チップとリードフレームとの間の接合ロウ材で
ある半田を真空蒸着法よって蒸着するので、蒸着膜厚制
御により半田量の微少制御が可能となり、さらにカッテ
ィング後熱圧着法によって半導体チップを個別にリード
フレームに直接ボンディングするので、ボンディング時
の半田皮膜対策、半田とチップの位置ずれ対策ができ、
したがって半田を用いる組立工法を大チップ品種に限ら
ず、一般の小チップ品種にも適用できるようになるとい
う効果を奏する。According to the method of assembling the semiconductor device of the present invention, solder, which is a brazing filler metal between the semiconductor chip and the lead frame, is deposited on the back surface of the semiconductor chip by a vacuum deposition method in a wafer state before cutting. Therefore, it is possible to control the amount of solder minutely by controlling the vapor deposition film thickness, and since the semiconductor chips are individually bonded directly to the lead frame by the thermocompression bonding method after cutting, it is possible to prevent the solder film at the time of bonding and the misalignment between the solder and the chip. Can
Therefore, the assembly method using solder can be applied not only to large chip types but also to general small chip types.
【図１】この発明の半導体装置の組立方法の実施例をを
示す概念図である。FIG. 1 is a conceptual diagram showing an embodiment of a method for assembling a semiconductor device of the present invention.
【図２】この発明の半導体装置の組立方法の実施例にお
けるチップダイシング後の状態を示す断面図である。FIG. 2 is a cross-sectional view showing a state after chip dicing in the embodiment of the method for assembling a semiconductor device of the present invention.
【図３】従来の金属箔を用いるロウ付けを示す断面図で
ある。FIG. 3 is a cross-sectional view showing brazing using a conventional metal foil.
【図４】従来の半田ワイヤによるロウ付けを示す断面図
である。FIG. 4 is a cross-sectional view showing brazing with a conventional solder wire.
【図５】従来の半田ペレットによるロウ付けを示す断面
図である。FIG. 5 is a cross-sectional view showing brazing with a conventional solder pellet.
１ リードフレーム ２ 蒸着半田 ３ 半導体チップ ９ 金属電極 1 lead frame 2 vapor deposition solder 3 semiconductor chip 9 metal electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 山本 茂樹 大阪府門真市大字門真1006番地 松下電子 工業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shigeki Yamamoto 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd.
Claims (1)
接合ロウ材である半田を、カッティング前のウェハ状態
で前記半導体チップの金属電極を有する裏面に真空蒸着
法によって蒸着し、カッティング後熱圧着法によって前
記半導体チップを個別にリードフレームに直接ボンディ
ングすることを特徴とする半導体装置の組立方法。1. A solder, which is a brazing filler metal between a semiconductor chip and a lead frame, is vapor-deposited on the back surface of the semiconductor chip having a metal electrode by a vacuum vapor deposition method in a wafer state before cutting, and a thermocompression bonding method after cutting. A method of assembling a semiconductor device, wherein the semiconductor chips are individually directly bonded to a lead frame by.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25782792A JPH06112237A (en) | 1992-09-28 | 1992-09-28 | Assembly method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25782792A JPH06112237A (en) | 1992-09-28 | 1992-09-28 | Assembly method for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06112237A true JPH06112237A (en) | 1994-04-22 |
Family
ID=17311682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25782792A Pending JPH06112237A (en) | 1992-09-28 | 1992-09-28 | Assembly method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06112237A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001176890A (en) * | 1999-12-21 | 2001-06-29 | Rohm Co Ltd | Semiconductor device and manufacturing method thereof |
-
1992
- 1992-09-28 JP JP25782792A patent/JPH06112237A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001176890A (en) * | 1999-12-21 | 2001-06-29 | Rohm Co Ltd | Semiconductor device and manufacturing method thereof |
| JP4544675B2 (en) * | 1999-12-21 | 2010-09-15 | ローム株式会社 | Manufacturing method of semiconductor device |
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