JPH06101488B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06101488B2 JPH06101488B2 JP27976488A JP27976488A JPH06101488B2 JP H06101488 B2 JPH06101488 B2 JP H06101488B2 JP 27976488 A JP27976488 A JP 27976488A JP 27976488 A JP27976488 A JP 27976488A JP H06101488 B2 JPH06101488 B2 JP H06101488B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- thermoplastic resin
- insulating substrate
- leads
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に樹脂封止型半導体装置
に関する。The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device.
従来、樹脂封止型半導体装置は第４図に示すように、鉄
系又は銅系の合金から成るリードフレーム31に、半導体
素子12を銀ペースト等のろう材により固着し、次いで、
金等のボンディングワイヤー13により半導体素子12の電
極端子とリードフレーム31とを電気的に接続した後、モ
ールド樹脂14により封止し、外部のリードを加工成形し
て製造されていた。Conventionally, as shown in FIG. 4, a resin-sealed semiconductor device has a semiconductor element 12 fixed to a lead frame 31 made of an iron-based or copper-based alloy with a brazing material such as silver paste, and then,
It is manufactured by electrically connecting the electrode terminal of the semiconductor element 12 and the lead frame 31 with a bonding wire 13 of gold or the like, then sealing with a molding resin 14, and processing and molding an external lead.
上述した従来の樹脂封止型半導体装置は、金属板をプレ
ス方式やエッチング方式で加工したリードフレームを用
いているため、リード数が増えて微細な加工を行なった
場合に、内部又は外部のリードが変形しやすくなるとい
う欠点がある。リードの変形は、組立歩留の低下やプリ
ント基板へ実装する際の半田付不良を生じやすく、超多
ピンタイプの樹脂封止型半導体装置を開発する上で大き
な支障をきたすという欠点がある。Since the conventional resin-encapsulated semiconductor device described above uses a lead frame obtained by processing a metal plate by a pressing method or an etching method, when the number of leads increases and fine processing is performed, internal or external leads are formed. Has the drawback of being easily deformed. Deformation of the leads has a drawback that the assembly yield is lowered and soldering failure is likely to occur when the leads are mounted on a printed circuit board, which is a great obstacle in developing an ultra-multi-pin type resin-sealed semiconductor device.
本発明の目的は、外部リードの変形がなく、組立歩留が
高く、プリント基板へ実装する際の半田付不良がなく、
超多ピン化へ対応できる樹脂封止型半導体装置を提供す
ることにある。The object of the present invention is to prevent deformation of external leads, high assembly yield, and no soldering defects when mounting on a printed circuit board.
It is an object of the present invention to provide a resin-encapsulated semiconductor device that can cope with an increase in the number of pins.
本発明は、複数の内部リードと外部リードとを有する樹
脂封止型半導体装置において、熱可塑性樹脂絶縁基板上
に金属薄膜のリードパターンを形成し、前記熱可塑性樹
脂絶縁基板上に半導体素子を載置し、前記金属薄膜のリ
ードと前記半導体素子の電極端子とが結線されている。According to the present invention, in a resin-sealed semiconductor device having a plurality of internal leads and external leads, a lead pattern of a metal thin film is formed on a thermoplastic resin insulating substrate, and a semiconductor element is mounted on the thermoplastic resin insulating substrate. Then, the lead of the metal thin film and the electrode terminal of the semiconductor element are connected.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例の断面図、第２図は第１
の実施例の製造工程途中のモールド樹脂封止後の平面図
である。FIG. 1 is a sectional view of a first embodiment of the present invention, and FIG.
FIG. 6 is a plan view after molding resin sealing during the manufacturing process of the example of FIG.
第２図において、熱可塑性樹脂絶縁基板11上には金属配
線層15のパターンが形成されており、半導体素子12と外
部との電気的接続をとる役目を果たす。外部リード部の
加工は熱可塑性樹脂を用いているため、軟化する程度に
加熱して曲げ加工をすれば容易に形状を変えることがで
き、第１図の如き形状を得ることができる。また、外部
リード部は一体構造となっているため、変形の心配もな
く、プリント基板への半田付けの歩留を飛躍的に向上さ
せることができる。In FIG. 2, a pattern of the metal wiring layer 15 is formed on the thermoplastic resin insulating substrate 11 and serves to electrically connect the semiconductor element 12 to the outside. Since a thermoplastic resin is used for processing the outer lead portion, the shape can be easily changed by heating and bending to the extent that it softens, and the shape shown in FIG. 1 can be obtained. Further, since the external lead portion has an integrated structure, there is no fear of deformation, and the yield of soldering to the printed circuit board can be dramatically improved.
ここで熱可塑性樹脂絶縁基板11の材質としてはガラス繊
維等で強化したPPS（ポリフェニレンサルファイド）樹
脂やPET（ポリエチレンテレフタレート樹脂等が適して
いるが限定されるものではない。また金属配線層15は、
銅等の金属をラミネート又はめっき等により熱可塑性樹
脂絶縁基板11上に形成する。その厚さは数十μｍで充分
である。その後、ホトエッチング法等によりパターンを
形成すればよく薄膜であるため微細加工が容易であるこ
とから、超多ピンパッケージ用として適している。な
お、ボンディングを行なうために、予め金や銀等の部分
めっき層を金属配線層15上に設けておくとよい。Here, PPS (polyphenylene sulfide) resin or PET (polyethylene terephthalate resin) reinforced with glass fiber or the like is suitable as the material of the thermoplastic resin insulating substrate 11, but is not limited thereto.
A metal such as copper is formed on the thermoplastic resin insulating substrate 11 by laminating or plating. Its thickness is several tens of μm. After that, a pattern may be formed by a photoetching method or the like, and since it is a thin film, microfabrication is easy. Therefore, it is suitable for an ultra-multipin package. It should be noted that a partial plating layer of gold, silver or the like may be previously provided on the metal wiring layer 15 in order to perform bonding.
第３図は本発明の第２の実施例の断面図である。FIG. 3 is a sectional view of the second embodiment of the present invention.
第２の実施例では、熱可塑性樹脂絶縁基板21にスルーホ
ール部26を設け、金属配線層25を表面から裏面側に移行
させている。従って、本方式を用いれば熱可塑性樹脂絶
縁基板21の表裏両面に金属配線層25を形成することが可
能となり、より多ピンのパッケージを製作するのに有利
となる。In the second embodiment, the thermoplastic resin insulating substrate 21 is provided with the through holes 26 and the metal wiring layer 25 is moved from the front surface to the back surface side. Therefore, by using this method, the metal wiring layers 25 can be formed on both front and back surfaces of the thermoplastic resin insulating substrate 21, which is advantageous for manufacturing a package with more pins.
以上説明したように本発明は、熱可塑性樹脂絶縁基板上
に金属配線層を設け、樹脂封止部の内部及び外部のリー
ドとすることで、微細配線加工が容易となり、超多ピン
化への応対がとれる効果がある。As described above, according to the present invention, by providing a metal wiring layer on a thermoplastic resin insulating substrate and using the leads inside and outside the resin-sealed portion, fine wiring processing is facilitated, and ultra-high pin count is achieved. It has the effect of being able to respond.
また、熱可塑性樹脂絶縁基板及びその上に形成された金
属配線層を加熱加工により一体成形し、外部リードとす
ることで、リードの変形を皆無にでき、半田付の歩留を
飛躍的に高められる効果も有する。In addition, the thermoplastic resin insulation substrate and the metal wiring layer formed on it are integrally molded by heating to form external leads, which can eliminate lead deformation and dramatically increase the soldering yield. It also has the effect.
第１図は本発明の第１の実施例の断面図、第２図は第１
の実施例の製造工程途中のモールド樹脂封止後の平面
図、第３図は本発明の第２の実施例の断面図、第４図は
従来の半導体装置の一例の断面図である。 11,21……熱可塑性樹脂絶縁基板、12……半導体素子、1
3……ボンディングワイヤー、14……モールド樹脂、15,
25……金属配線層、26……スルーホール部、31……リー
ドフレーム。FIG. 1 is a sectional view of a first embodiment of the present invention, and FIG.
FIG. 3 is a plan view after sealing with a mold resin in the manufacturing process of the embodiment of FIG. 3, FIG. 3 is a sectional view of a second embodiment of the present invention, and FIG. 4 is a sectional view of an example of a conventional semiconductor device. 11,21 …… thermoplastic resin insulating substrate, 12 …… semiconductor element, 1
3 ... Bonding wire, 14 ... Mold resin, 15,
25 …… Metal wiring layer, 26 …… Through hole part, 31 …… Lead frame.
Claims (1)
樹脂封止型半導体装置において、熱可塑性樹脂絶縁基板
上に金属薄膜のリードパターンを形成し、前記熱可塑性
樹脂絶縁基板上に半導体素子を載置し、前記金属薄膜の
リードと前記半導体素子の電極端子とを結線したことを
特徴とする半導体装置。1. A resin-sealed semiconductor device having a plurality of internal leads and external leads, wherein a lead pattern of a metal thin film is formed on a thermoplastic resin insulating substrate, and a semiconductor element is formed on the thermoplastic resin insulating substrate. A semiconductor device, characterized in that it is mounted and the leads of the metal thin film are connected to the electrode terminals of the semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27976488A JPH06101488B2 (en) | 1988-11-04 | 1988-11-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27976488A JPH06101488B2 (en) | 1988-11-04 | 1988-11-04 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02125629A JPH02125629A (en) | 1990-05-14 |
| JPH06101488B2 true JPH06101488B2 (en) | 1994-12-12 |
Family
ID=17615578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27976488A Expired - Fee Related JPH06101488B2 (en) | 1988-11-04 | 1988-11-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06101488B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0637241A (en) * | 1992-07-17 | 1994-02-10 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
-
1988
- 1988-11-04 JP JP27976488A patent/JPH06101488B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02125629A (en) | 1990-05-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |