JPH06100939B2 - Power supply circuit - Google Patents
Power supply circuitInfo
- Publication number
- JPH06100939B2 JPH06100939B2 JP62224657A JP22465787A JPH06100939B2 JP H06100939 B2 JPH06100939 B2 JP H06100939B2 JP 62224657 A JP62224657 A JP 62224657A JP 22465787 A JP22465787 A JP 22465787A JP H06100939 B2 JPH06100939 B2 JP H06100939B2
- Authority
- JP
- Japan
- Prior art keywords
- potential
- signal
- circuit
- load current
- differential amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
- Dram (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電源回路に関し、特に同一半導体基板上に集積
された負荷回路に電源電位の変動によらず一定の電位を
供給する電源回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit, and more particularly to a power supply circuit which supplies a constant potential to load circuits integrated on the same semiconductor substrate regardless of fluctuations in the power supply potential.
従来、この種の電源回路は基準電位と出力電位の差電位
を差動増幅することにより、負荷電流の変動に対し出力
電位を一定に保つ様構成されていた。Conventionally, this type of power supply circuit has been configured to differentially amplify the difference potential between the reference potential and the output potential to keep the output potential constant with respect to fluctuations in the load current.
第３図は従来の電源回路の一例の回路図、第４図
（ａ），（ｂ）は第３図の電源回路の動作波形図を示
し、第４図（ａ）は電圧、第４図（ｂ）は負荷電流IOUT
を示している。図において、１は基準電位発生回路であ
り、抵抗R1及びソースとドレインが共通接続されたＮチ
ャンネルMOSトランジスタQ1,Q2,Q3が直列接続されてい
る為に、出力φＡは電源電位によらずＮチャンネルMOS
トランジスタのしきい値により定まる電位となる。差動
増幅回路２は、電位φＡ及びφＢを入力とし出力電位を
φOUTを出力とする回路であり、ここでは電位φＢは電
位φOUTと共通接続され、ＰチャンネルMOSトランジスタ
Q6,Q7及びＮチャンネルMOSトランジスタQ8,Q9により、
ミラー型差動増幅回路を構成している。FIG. 3 is a circuit diagram of an example of a conventional power supply circuit, FIGS. 4 (a) and 4 (b) are operation waveform diagrams of the power supply circuit of FIG. 3, and FIG. 4 (a) is a voltage and FIG. (B) is the load current I OUT
Is shown. In the figure, reference numeral 1 is a reference potential generating circuit, and since a resistor R 1 and N-channel MOS transistors Q 1 , Q 2 and Q 3 whose sources and drains are commonly connected are connected in series, the output φ A is a power supply. N-channel MOS regardless of potential
The potential is determined by the threshold value of the transistor. The differential amplifier circuit 2 is a circuit that inputs the potentials φ A and φ B and outputs the output potential φ OUT . Here, the potential φ B is commonly connected to the potential φ OUT, and a P-channel MOS transistor is provided.
With Q 6 and Q 7 and N-channel MOS transistors Q 8 and Q 9 ,
It constitutes a mirror type differential amplifier circuit.
ＰチャンネルMOSトランジスタQ5はこのミラー型差動増
幅回路への電流供給手段であり、ＰチャンネルMOSトラ
ンジスタQ4は、第４図（ａ）のように負荷電流の増加す
る期間の信号φ１により活性化されることにより、ミラ
ー型差動増幅回路への供給電流を増加させる機能を有す
る。The P-channel MOS transistor Q 5 is a means for supplying a current to this mirror type differential amplifier circuit, and the P-channel MOS transistor Q 4 receives the signal φ 1 during the period when the load current increases as shown in FIG. 4 (a). When activated, it has a function of increasing the supply current to the mirror type differential amplifier circuit.
一般に、ミラー型差動増幅回路は、供給電流を増加させ
ることにより、入力信号の変動に対する応答速度が向上
する特性を有している。従って、差動増幅回路２は、負
荷電流の変動に同期した信号φ１を用いることにより、
負荷電流が増大する際には、信号φ１が活性化され、消
費電流は増大するが、出力電位の変動に対する応答速度
が向上し、負荷電流が少ない場合には信号φ１が非活性
化され、出力電位の変動に対する応答速度が低下する
が、消費電流は低下することとなり、消費電流が少な
く、かつ負荷電流の変動に対する出力電位の変動の少な
い電源回路を実現している。In general, the mirror type differential amplifier circuit has a characteristic that the response speed to the fluctuation of the input signal is improved by increasing the supply current. Therefore, the differential amplifier circuit 2 uses the signal φ 1 synchronized with the fluctuation of the load current,
When the load current increases, the signal φ 1 is activated and the current consumption increases, but the response speed to the fluctuation of the output potential improves, and when the load current is small, the signal φ 1 is deactivated. Although the response speed with respect to the fluctuation of the output potential is reduced, the current consumption is also reduced, and a power supply circuit with less current consumption and less variation of the output potential with respect to the variation of the load current is realized.
上述した従来の電源回路は、負荷電流の変動により出力
電位の変動を、負荷電流IOUTの変動に同期する信号を用
いて出力電位の変動を検出する差動増幅回路２の応答速
度を速めることにより低減しようとするものである。従
って、出力電位の変動が起きた後で、差動増幅回路２が
動作することとなる為に、差動増幅回路の応答速度の向
上に対する出力電位の安定化への寄与が少ないという欠
点があった。The above-described conventional power supply circuit increases the response speed of the differential amplifier circuit 2 which detects the fluctuation of the output potential due to the fluctuation of the load current and the fluctuation of the output potential by using the signal synchronized with the fluctuation of the load current I OUT. It is intended to be reduced by Therefore, since the differential amplifier circuit 2 operates after the output potential fluctuates, there is a drawback that contribution to the stabilization of the output potential to the improvement of the response speed of the differential amplifier circuit is small. It was
本発明の目的は、これらの欠点を除き、基準電位と信号
により制御された比較電位との差電位を作動増幅するこ
とにより、出力電位を電源変動によらず安定に制御する
ことのできる電源回路を提供することにある。An object of the present invention is to eliminate the above drawbacks, and by operating and amplifying a difference potential between a reference potential and a comparison potential controlled by a signal, a power supply circuit that can stably control an output potential regardless of power supply fluctuations. To provide.
本発明による電源回路は、基準電位を出力する基準電位
発生回路と、前記基準電位と入力電位との差電位を増幅
して出力電位とすると共に負荷電流の増大時に対応した
第１の信号が活性化したとき供給電流を増加させて前記
負荷電流を増加できるようにし、前記第１の信号が不活
性のとき前記供給電流を減少させて前記負荷電流を減少
させる差動増幅回路と、前記第１の信号に同期して前記
負荷電流の過大時期に対応してその第１の信号の切換え
時から所定時間遅れて所定短時間活性化された第２の信
号が活性化したとき前記差動増幅回路の出力電位を下げ
るよう制御して前記入力電位を出力する比較電位発生回
路とを備えることを特徴とする。In the power supply circuit according to the present invention, a reference potential generating circuit that outputs a reference potential and an output potential by amplifying a difference potential between the reference potential and an input potential and a first signal corresponding to an increase in load current are activated. A differential amplifier circuit that increases the supply current to increase the load current when the signal is activated, and decreases the supply current to decrease the load current when the first signal is inactive; The differential amplifier circuit is activated when a second signal activated for a predetermined short time is activated in synchronization with the load current in response to an excessive period of the load current by a predetermined time after the switching of the first signal. And a comparison potential generation circuit that outputs the input potential by controlling so as to lower the output potential.
以下、図面により本発明を詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to the drawings.
第１図は本発明の一実施例の回路図、第２図（ａ），
（ｂ）はその動作波形図を示す。本実施例は基準電位発
生回路1,差動増幅回路２および比較電位発生回路３から
構成される。比較用電位発生回路３の入力φＣは、電源
回路の出力端子４に接続され、比較電位発生回路３の出
力φＢは差動増幅回路２の入力へ接続される。比較電位
発生回路１は、抵抗R2とＮチャンネルMOSトランジスタQ
11とで構成された放電手段を有する。FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 (a),
(B) shows the operation waveform diagram. This embodiment comprises a reference potential generating circuit 1, a differential amplifier circuit 2 and a comparison potential generating circuit 3. The input φ C of the comparison potential generation circuit 3 is connected to the output terminal 4 of the power supply circuit, and the output φ B of the comparison potential generation circuit 3 is connected to the input of the differential amplifier circuit 2. The comparison potential generation circuit 1 includes a resistor R 2 and an N-channel MOS transistor Q.
11 has a discharge means constituted by.
なお、第２図（ａ）に示すように、信号φ２は負荷電流
の増加期間の信号φ１のうち、第２図（ｂ）に示すよう
な過大なラッシュ電流の流れる期間の信号に相当し、使
用回路により予め決められる期間である。As shown in FIG. 2 (a), the signal φ 2 corresponds to the signal φ 1 in the period in which the load current increases, which corresponds to the signal in the period in which an excessive rush current flows as shown in FIG. 2 (b). However, it is a period determined in advance by the circuit used.
第１図の比較電位発生回路３は信号φ２が非活性のとき
は出力φＢが入力φＣと同電位であるが、信号φ２が活
性化されると、出力φＢの電位は出力電位φOUTを抵抗R
2とＮチャンネルMOSトランジスタQ11との抵抗比で分割
した電位となる。Although comparison potential generating circuit 3 of FIG. 1 is a signal phi 2 is at the same potential output phi B and an input phi C when inactive, the signal phi 2 is activated, the potential of the output phi B is output Potential φ OUT is resistance R
The potential is divided by the resistance ratio of 2 and the N channel MOS transistor Q 11 .
従って、第１図においては信号φ２を負荷電流の増加の
直前に一定時間活性化される信号とすることにより、負
荷電流の増加と同時、もしくはその直前に差動増幅回路
２に差電位が入力される為に、負荷電流の増大に伴なう
出力電位の低下が軽減される。Therefore, in FIG. 1, by setting the signal φ 2 to be a signal that is activated for a certain period of time immediately before the increase of the load current, a differential potential is generated in the differential amplifier circuit 2 at the same time as or immediately before the increase of the load current. Since it is input, the decrease in the output potential due to the increase in load current is reduced.
以上説明したように本発明は、負荷電流の増大に同期し
た信号を入力信号として比較電位発生回路の出力電位を
制御することにより、差動増幅回路の動作の遅れをなく
し、負荷電流の変動によらない安定した出力電位を得る
ことができる効果がある。As described above, the present invention eliminates the delay in the operation of the differential amplifier circuit by controlling the output potential of the comparison potential generation circuit by using the signal synchronized with the increase of the load current as the input signal, and the fluctuation of the load current is prevented. There is an effect that a stable output potential can be obtained regardless of the above.
第１図は本発明の電源回路の一実施例の回路図、第２図
（ａ），（ｂ）は第１図の回路の動作電圧・電流を示す
波形図、第３図は従来の電源回路の一例の回路図、第４
図（ａ），（ｂ）は第３図の回路の動作電圧・電流を示
す波形図である。 １……基準電圧発生回路、２……差動増幅回路、３……
比較電位発生回路、４……出力端子、Q1,Q2,Q3,Q8,Q9,Q
11……ＮチャンネルMOSトランジスタ、Q4,Q5,Q6,Q7,Q10
……ＰチャンネルMOSトランジスタ、R1,R2……抵抗。FIG. 1 is a circuit diagram of an embodiment of a power supply circuit of the present invention, FIGS. 2 (a) and 2 (b) are waveform diagrams showing operating voltages and currents of the circuit of FIG. 1, and FIG. 3 is a conventional power supply. Circuit diagram of an example of a circuit, fourth
3A and 3B are waveform diagrams showing operating voltages and currents of the circuit of FIG. 1 ... Reference voltage generating circuit, 2 ... Differential amplifier circuit, 3 ...
Comparison potential generation circuit, 4 ... Output terminal, Q 1 , Q 2 , Q 3 , Q 8 , Q 9 , Q
11 N-channel MOS transistor, Q 4 , Q 5 , Q 6 , Q 7 , Q 10
...... P-channel MOS transistor, R 1 , R 2 ...... Resistance.
Claims (1)
前記基準電位と入力電位との差電位を増幅して出力電位
とすると共に負荷電流の増大時に対応した第１の信号が
活性化したとき供給電流を増加させて前記負荷電流を増
加できるようにし、前記第１の信号が不活性のとき前記
供給電流を減少させて前記負荷電流を減少させる差動増
幅回路と、前記第１の信号に同期して前記負荷電流の過
大時期に対応してその第１の信号の切換え時から所定時
間遅れて所定短時間活性化された第２の信号が活性化し
たとき前記差動増幅回路の出力電位を下げるよう制御し
て前記入力電位を出力する比較電位発生回路とを備える
ことを特徴とする電源回路。1. A reference potential generating circuit for outputting a reference potential,
Amplifying a difference potential between the reference potential and the input potential to obtain an output potential and increasing the supply current when the first signal corresponding to the increase of the load current is activated, thereby increasing the load current, A differential amplifier circuit that reduces the supply current to reduce the load current when the first signal is inactive; and a differential amplifier circuit that responds to an excessive period of the load current in synchronization with the first signal. Comparison potential generation for outputting the input potential by controlling the output potential of the differential amplifier circuit to decrease when the second signal activated for a predetermined short time after activation of the first signal is activated And a power supply circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62224657A JPH06100939B2 (en) | 1987-09-07 | 1987-09-07 | Power supply circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62224657A JPH06100939B2 (en) | 1987-09-07 | 1987-09-07 | Power supply circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6465610A JPS6465610A (en) | 1989-03-10 |
| JPH06100939B2 true JPH06100939B2 (en) | 1994-12-12 |
Family
ID=16817159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62224657A Expired - Lifetime JPH06100939B2 (en) | 1987-09-07 | 1987-09-07 | Power supply circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06100939B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2883625B2 (en) * | 1989-03-30 | 1999-04-19 | 株式会社東芝 | MOS type charging circuit |
| US4952863A (en) * | 1989-12-20 | 1990-08-28 | International Business Machines Corporation | Voltage regulator with power boost system |
| US6906159B2 (en) | 2000-08-03 | 2005-06-14 | Nippon Shokubai Co., Ltd. | Water-absorbent resin, hydropolymer, process for producing them, and uses of them |
| US20060273771A1 (en) | 2005-06-03 | 2006-12-07 | Micrel, Incorporated | Creating additional phase margin in the open loop gain of a negative feedback amplifier system |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5627537Y2 (en) * | 1972-03-09 | 1981-07-01 | ||
| JPS53106410A (en) * | 1977-02-25 | 1978-09-16 | Mitsubishi Electric Corp | Speed compensator |
| JPS6019684A (en) * | 1983-07-13 | 1985-01-31 | 株式会社日立製作所 | Suspension supporter |
| JPS6196587A (en) * | 1984-10-17 | 1986-05-15 | Toshiba Corp | Sense amplifier circuit |
-
1987
- 1987-09-07 JP JP62224657A patent/JPH06100939B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6465610A (en) | 1989-03-10 |
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