JPH0586071B2 - - Google Patents
Info
- Publication number
- JPH0586071B2 JPH0586071B2 JP62318783A JP31878387A JPH0586071B2 JP H0586071 B2 JPH0586071 B2 JP H0586071B2 JP 62318783 A JP62318783 A JP 62318783A JP 31878387 A JP31878387 A JP 31878387A JP H0586071 B2 JPH0586071 B2 JP H0586071B2
- Authority
- JP
- Japan
- Prior art keywords
- board
- chips
- mounting
- wiring
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 claims description 18
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000015654 memory Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
- Y02T10/00—Road transport of goods or passengers
- Y02T10/10—Internal combustion engine [ICE] based vehicles
- Y02T10/12—Improving ICE efficiencies
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は同一ボードあるいは基板に複数の半導
体装置（半導体チツプ）を実装した半導体実装装
置に関する。Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor mounting device in which a plurality of semiconductor devices (semiconductor chips) are mounted on the same board or substrate.
（従来の技術）
従来、例えばメモリー・ボードのように、同一
基板に多数の同一半導体装置を実装する場合、実
装密度をいかに向上させるかが大きな問題であつ
た。(Prior Art) Conventionally, when a large number of the same semiconductor devices are mounted on the same substrate, such as a memory board, a major problem has been how to improve the mounting density.
ボード上に半導体装置を実装する方法として
は、従来からプラスチツクあるいはセラミツクの
パツケージに組み込まれた半導体装置を用いる方
法が採用されているが、実装密度の向上にとつて
パツケージの大きさが無視できない状況になりつ
つある。 The conventional method for mounting semiconductor devices on a board is to use semiconductor devices embedded in plastic or ceramic packages, but the size of the package cannot be ignored in order to improve packaging density. It is becoming.
このような状況において、近年ではTAB
（Tape Automated Bonding）あるいはCOB
（Chip On Boad）のような実装技術の開発が盛
んに行なわれている。またさらに実装密度を向上
させるために、ボードの両面に半導体装置を実装
する方法も開発されつつある。 In this situation, in recent years TAB
(Tape Automated Bonding) or COB
Mounting technologies such as (Chip On Board) are being actively developed. Furthermore, in order to further improve the packaging density, methods are being developed in which semiconductor devices are mounted on both sides of the board.
（発明が解決しようとする問題点）
ところで上記のような実装技術が進めば進むほ
ど、ボード上に形成された電源や信号の配線に要
する面積が、実装密度の向上にとつて問題である
ことが明らかとなつてきた。(Problems to be Solved by the Invention) However, as the above-mentioned packaging technology advances, the area required for power supply and signal wiring formed on the board becomes a problem for improving packaging density. has become clear.
本発明は上記実情に鑑みてなされたもので、同
一のボードあるいは基板上に、より多くの同一の
半導体装置を実装することができる半導体実装装
置を提供しようとするものである。 The present invention has been made in view of the above circumstances, and is intended to provide a semiconductor mounting device that can mount a larger number of the same semiconductor devices on the same board or substrate.
［発明の構成］
（問題点を解決するための手段と作用）
本発明は、チツプ実装用板体の表裏で対向配置
されたとき、少なくとも互いに対応する端子どう
しが鏡像関係となるような実装パターンを有する
半導体チツプどうしを、前記板体を挟んで前記鏡
像関係になるように前記板体に配置し、前記チツ
プ間で互いに対応する端子どうしを、前記板体の
表裏間を貫通するスルーホールを通して接続する
と共に前記板体の表裏いずれかの配線パターンに
共通接続したことを特徴とする半導体実装装置で
ある。[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a mounting pattern in which at least corresponding terminals are mirror images of each other when they are arranged facing each other on the front and back sides of a chip mounting board. Semiconductor chips having the following characteristics are arranged on the plate body so as to be mirror images with the plate body in between, and terminals corresponding to each other between the chips are passed through through holes penetrating between the front and back of the plate body. This semiconductor mounting device is characterized in that it is connected in common to a wiring pattern on one of the front and back sides of the board.
即ち本発明においては、この様な構成としたた
め、上記チツプ実装用板体上での配線の占有面積
が縮小され、したがつて実装密度の向上が図れ
る。また上記配線パターンは、スルーホールの箇
所の接続領域に接続される板体上片面配置である
から、配線パターンの配線自由度が増す。また、
上記配線が縮小した分だけ、不要な寄生の配線容
量を減らすことができるものである。 That is, in the present invention, with such a configuration, the area occupied by the wiring on the chip mounting board is reduced, and therefore the packaging density can be improved. Further, since the wiring pattern is arranged on one side of the plate to be connected to the connection area of the through hole, the degree of freedom in wiring the wiring pattern is increased. Also,
Unnecessary parasitic wiring capacitance can be reduced to the extent that the wiring is reduced.
（実施例）
以下図面を参照して本発明の実施例を説明す
る。第１図は、本発明の改良前の一例を示してい
る。第１図において１はボードであり、このボー
ド１上には複数のチツプ２，３が隣接配置されて
いる。これらのチツプ２，３は、互いに鏡像関係
となるような実装パターンを有する。即ち、例え
ばそれぞれの電源パツド４，５は互いに向かい合
う方向に出ており、またチツプ２，３がメモリー
であるなら、共通のアドレス６，７は互いに向か
い合う方向に出ている。このような配置構成のチ
ツプ２，３であれば、これらのチツプでボード１
上の電源ライン８を共有し、ワイヤ９により電源
パツド４，５に共通接続でき、配線面積的に有利
化される。(Example) Examples of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of the present invention before improvement. In FIG. 1, 1 is a board, on which a plurality of chips 2 and 3 are arranged adjacent to each other. These chips 2 and 3 have mounting patterns that are mirror images of each other. That is, for example, the respective power supply pads 4, 5 are directed toward each other, and if the chips 2, 3 are memories, the common addresses 6, 7 are directed toward each other. If chips 2 and 3 are arranged like this, these chips can be used to connect board 1.
The upper power supply line 8 can be shared and commonly connected to the power supply pads 4 and 5 by a wire 9, which is advantageous in terms of wiring area.
このことは、共通のアドレスパツド６，７のラ
イン１０についても同様のことが云える。 The same can be said of the line 10 of the common address pads 6 and 7.
第２図、第３図は本発明の一実施例を示す実装
例で、第２図はボード２０上から見た上面図、第
３図は同じくボード２０の裏面から見た下面図で
ある。ここでボード２０に表裏対向配置されたチ
ツプ２１，２２は、互いに鏡像関係となるような
実装パターンを有する。即ち電源パツド２３，２
４は互いに向かい合う方向に出ており、またチツ
２１，２２がメモリーであるなら、共通のアドレ
スパツド２５，２６は互いに向かい合う方向に出
ている。このような配置構成のチツプ２１，２２
であれば、スルーホール２７を通しかつ中継用配
線パターン２８、ワイヤ２９を用いて電源パツド
２３，２４を電源ライン３０に共通接続できる。
この場合ボード２０上の電源ライン３０は、ボー
ド２０の表あるいは裏のどちらかにあればよく、
配線面積的に有利化される。即ち上記の構成にお
いては、イチツプ実装用板体２０の表裏において
鏡像関係で配置される半導体チツプどうしを、平
面的にほとんど場所を必要としないスルーホール
２７，３５を通して接続することにより、チツプ
実装用板体２０上における配線占有面積的にも、
配線距離的にも、縮小化が図れるものである。ロ
上記イ項で説明したスルーホールを通して設けら
れる接続領域は、前記板体２０の平面的な場所の
選択が不要で、その分前記板体２０上の集積度が
上がるばかりか、上記スルーホール２７，３５を
通して設けられる接続領域に接続される上記配線
パターン３０は、上記接続領域（スルーホールの
箇所の）のみに接続されるならば、板体２０の片
面でどのように配線しても良く、したがつて、上
記配線パターンの配線自由度が増すものである。
ハ上記イ，ロ項で説明した配線が縮小した分だ
け、不要な寄生の配線容量を減少させることがで
きる。 2 and 3 are mounting examples showing an embodiment of the present invention. FIG. 2 is a top view of the board 20 as seen from above, and FIG. 3 is a bottom view of the board 20 as seen from the back side. Here, the chips 21 and 22 disposed on the board 20 facing each other have mounting patterns that are mirror images of each other. That is, the power supply pads 23, 2
4 extend in directions facing each other, and if chips 21 and 22 are memories, common address pads 25 and 26 extend in directions facing each other. Chips 21 and 22 with such an arrangement
If so, the power supply pads 23 and 24 can be commonly connected to the power supply line 30 through the through hole 27 and using the relay wiring pattern 28 and the wire 29.
In this case, the power line 30 on the board 20 may be on either the front or back of the board 20,
This provides an advantage in terms of wiring area. That is, in the above configuration, the semiconductor chips arranged in a mirror image relationship on the front and back sides of the chip mounting board 20 are connected through the through holes 27 and 35, which require almost no space in a plane, so that the chip mounting board 20 can be easily mounted. In terms of the area occupied by the wiring on the board 20,
The wiring distance can also be reduced. (b) The connection area provided through the through hole described in the above item (a) does not require selection of a planar location on the plate body 20, which not only increases the degree of integration on the plate body 20, but also increases the degree of integration on the plate body 20. , 35, the wiring pattern 30 may be wired in any way on one side of the board 20 as long as it is connected only to the connection area (at the through hole). Therefore, the degree of freedom in wiring the wiring pattern is increased.
2) Unnecessary parasitic wiring capacitance can be reduced to the extent that the wiring explained in sections 1 and 2 above is reduced.
このことは、共通のアドレスパツド２５，２６
のライン３３についても同様のことが云える。な
お３４は中継用配線パターン、３５はスルーホー
ル、３６は配線用ワイヤである。 This means that the common address pads 25, 26
The same can be said about line 33. Note that 34 is a relay wiring pattern, 35 is a through hole, and 36 is a wiring wire.
上記のように、互いに鏡像関係となるような実
装パターンを有するチツプ２，３、またはチツプ
２１，２２を得るには、同一レチクルに、互に鏡
像関係となるマスク用パターンを有するものを用
いてもよいし、また別々のレチクルに、互いに鏡
像関係となるマスク用パターンを有するものを用
いてもよいし、要はチツプどうしを対向配置した
とき、少くとも互に対応する端子どうしが鏡像関
係となるようにできるものであればよい。 As mentioned above, in order to obtain chips 2 and 3 or chips 21 and 22 having mounting patterns that are mirror images of each other, the same reticle has mask patterns that are mirror images of each other. Alternatively, separate reticles may be used that have mask patterns that are mirror images of each other.The point is that when chips are placed facing each other, at least the corresponding terminals are mirror images of each other. It is fine as long as it can be done.
なお本発明は実施例のみに限られず種々の応用
が可能である。例えば実施例ではチツプを直接ボ
ード上に実装する方法を用いているが、その他の
方法例えばDIP（Dual In−line Package）や
TABなどの方法においても同様であることは云
うまでもない。また実施例では半導体装置とし
て、メモリーチツプを用いたが、他の半導体装置
であつてもよい。 Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, although the example uses a method of mounting the chip directly on the board, other methods such as DIP (Dual In-line Package) or
Needless to say, the same applies to methods such as TAB. Furthermore, although a memory chip is used as the semiconductor device in the embodiment, other semiconductor devices may be used.
［発明の効果］
以上説明した如く本発明によれば、ボードある
いは基板に実装される半導体装置の実装パターン
を、表裏対向する半導体装置で互いに鏡像関係に
なるようにすることによつて、実装密度の向上を
はかることができる。また本発明はボード上の配
線パターンを減少させることができるため、配線
容量を減少することができる。また、鏡像関係に
あるチツプをつくることは、現在の製造プロセス
においては、コストダウンあるいはスループツト
を向上させるためのマルチチツプ・レチクルを利
用すれば、全く従来通りの設備、コストで可能で
あることは明らかである。[Effects of the Invention] As explained above, according to the present invention, the mounting density of the semiconductor devices mounted on a board or substrate is improved by making the mounting patterns of the semiconductor devices mounted on the front and back sides mirror images of each other. can be improved. Furthermore, since the present invention can reduce the number of wiring patterns on the board, the wiring capacitance can be reduced. Furthermore, it is clear that it is possible to create mirror-image chips using the same equipment and cost as in the current manufacturing process, by using multi-chip reticles to reduce costs or improve throughput. It is.
第１図は、本発明に至る改良前の装置例の平面
図、第２図、第３図は、本発明の一実施例の上面
図、下面図である。
１，２０……ボード、２，３，２１，２２……
チツプ、４，５，２３，２４……電源パツド、
６，７，２５，２６……アドレスパツド、８，３
０……電源ラインの配線パターン、９，２９，３
６……ワイヤ、１０，３３……アドレスライン、
２８，３４……中継用配線パターン、２７，３５
……スルーホール。
FIG. 1 is a plan view of an example of an apparatus before improvement leading to the present invention, and FIGS. 2 and 3 are a top view and a bottom view of an embodiment of the present invention. 1, 20...board, 2, 3, 21, 22...
Chip, 4, 5, 23, 24...Power pad,
6, 7, 25, 26...address pad, 8, 3
0...Power line wiring pattern, 9, 29, 3
6...wire, 10,33...address line,
28, 34... Relay wiring pattern, 27, 35
...Through hole.
Claims (1)
き、少なくとも互いに対応する端子どうしが鏡像
関係となるような実装パターンを有する半導体チ
ツプどうしを、前記板体を挟んで前記鏡像関係に
なるように前記板体に配置し、前記チツプ間で互
いに対応する端子どうしを、前記板体の表裏間を
貫通するスルーホールを通して接続すると共に前
記板体の表裏いずれかの配線パターンに共通接続
したことを特徴とする半導体実装装置。1 Semiconductor chips having mounting patterns such that at least their corresponding terminals are in a mirror image relationship when placed facing each other on the front and back sides of a chip mounting board are placed in such a manner that they have the mirror image relationship with the board in between. Terminals arranged on the board and corresponding to each other between the chips are connected through through holes penetrating between the front and back of the board, and are commonly connected to a wiring pattern on either the front or back of the board. Semiconductor mounting equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62318783A JPH01161744A (en) | 1987-12-18 | 1987-12-18 | Semiconductor mounting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62318783A JPH01161744A (en) | 1987-12-18 | 1987-12-18 | Semiconductor mounting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01161744A JPH01161744A (en) | 1989-06-26 |
| JPH0586071B2 true JPH0586071B2 (en) | 1993-12-09 |
Family
ID=18102895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62318783A Granted JPH01161744A (en) | 1987-12-18 | 1987-12-18 | Semiconductor mounting device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01161744A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS523271A (en) * | 1975-06-24 | 1977-01-11 | Hitoshi Tsujimoto | Cleaning apparatus for processed parts |
| JPS5814391U (en) * | 1981-07-21 | 1983-01-28 | 九州積水工業株式会社 | Hopper loader valve plate operating mechanism |
-
1987
- 1987-12-18 JP JP62318783A patent/JPH01161744A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS523271A (en) * | 1975-06-24 | 1977-01-11 | Hitoshi Tsujimoto | Cleaning apparatus for processed parts |
| JPS5814391U (en) * | 1981-07-21 | 1983-01-28 | 九州積水工業株式会社 | Hopper loader valve plate operating mechanism |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01161744A (en) | 1989-06-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |