JPH0582515A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0582515A JPH0582515A JP26697791A JP26697791A JPH0582515A JP H0582515 A JPH0582515 A JP H0582515A JP 26697791 A JP26697791 A JP 26697791A JP 26697791 A JP26697791 A JP 26697791A JP H0582515 A JPH0582515 A JP H0582515A
- Authority
- JP
- Japan
- Prior art keywords
- active region
- oxide film
- edge
- stop layer
- channel stop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置およびその
製造方法に関し、詳しくは素子分離技術、特にチャネル
ストップ層の構造および製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to an element isolation technique, and more particularly to a structure and a manufacturing method of a channel stop layer.
【０００２】[0002]
【従来の技術】サブミクロンレベルの半導体装置では、
特に拡散層エッジでの接合容量（接合容量の線成分）を
減少させる必要がある。これは、拡散層平面部での接合
容量（接合容量の面成分）は寸法の縮小に伴い２次で比
例するため容易に減少するが、線成分は寸法に対し１次
で比例するため、寸法を縮小しても接合容量があまり小
さくならないからである。2. Description of the Related Art In a submicron level semiconductor device,
In particular, it is necessary to reduce the junction capacitance (line component of the junction capacitance) at the edge of the diffusion layer. This is because the junction capacitance (plane component of the junction capacitance) in the plane portion of the diffusion layer is quadratically proportional to the reduction of the dimension and thus easily decreases, but the line component is linearly proportional to the dimension, This is because the junction capacitance does not become so small even if is reduced.
【０００３】ところで、サブミクロンレベルでの素子分
離方法として、チャネルストップイオン注入をフィール
ド酸化後に行うＩＴＦ（Ion implantation Through Fie
ldoxide ）法が注目されているが、この方法ではアクテ
ィブ領域にもチャネルストップ不純物が導入されてチャ
ネルストップ層が形成されるため、拡散層の接合容量が
増加するという問題がある。しかし、接合容量の面成分
は、ＩＴＦ法によるイオン注入時のエネルギーを高くし
てチャネルストップ層を深く形成することにより、容易
に削減できる。By the way, as an element isolation method at the submicron level, an ITF (Ion Implantation Through Fie) in which channel stop ion implantation is performed after field oxidation is performed.
The ldoxide) method is drawing attention, but this method has a problem that the junction capacitance of the diffusion layer increases because the channel stop layer is formed by introducing the channel stop impurity into the active region. However, the surface component of the junction capacitance can be easily reduced by increasing the energy at the time of ion implantation by the ITF method and forming the channel stop layer deep.
【０００４】[0004]
【発明が解決しようとする課題】しかるに、接合容量の
線成分はＩＴＦ法の条件にあまり依存しないため削減で
きず、特にこの線成分を減少させる必要があるという要
望に答えられない結果となる。However, since the line component of the junction capacitance is not so dependent on the conditions of the ITF method, it cannot be reduced, and in particular, the demand that this line component needs to be reduced cannot be answered.
【０００５】この発明は上記の点に鑑みなされたもの
で、ＩＴＦ法によるチャネルストップ層の形成法を採用
して、拡散層エッジ部での接合容量（接合容量の線成
分）を削減することができる半導体装置およびその製造
方法を提供することを目的とする。The present invention has been made in view of the above points, and it is possible to reduce the junction capacitance (line component of the junction capacitance) at the edge portion of the diffusion layer by adopting the method of forming the channel stop layer by the ITF method. An object of the present invention is to provide a semiconductor device that can be manufactured and a manufacturing method thereof.
【０００６】[0006]
【課題を解決するための手段】この発明では、アクティ
ブ領域エッジで選択的に深くしてＩＴＦ法でチャネルス
トップ層を形成する。According to the present invention, the channel stop layer is formed by the ITF method by selectively deepening the edge of the active region.
【０００７】[0007]
【作用】アクティブ領域エッジでチャネルストップ層が
選択的に深く形成されると、該アクティブ領域エッジ
で、拡散層のエッジとチャネルストップ層間の距離を大
きくとることができ、拡散層エッジ部での接合容量（接
合容量の線成分）を減少させることができる。When the channel stop layer is selectively formed deep at the edge of the active region, the distance between the edge of the diffusion layer and the channel stop layer can be increased at the edge of the active region, and the junction at the edge portion of the diffusion layer can be obtained. The capacitance (line component of the junction capacitance) can be reduced.
【０００８】[0008]
【実施例】以下この発明の一実施例を図１および図２を
参照して説明する。一実施例では図１（ａ）〜（ｄ）お
よび図２（ａ）に示すように、まずフレームドＬＯＣＯ
Ｓ法を用いてＰ型シリコン基板１の表面にフィールド酸
化膜５を形成する。ここで、フレームドＬＯＣＯＳ法と
は、通常のＬＯＣＯＳ法にSi3N4 膜のサイドウォール４
ａを付加することによりバーズビーク幅Ｗを削減し、か
つアクティブ領域エッジでくぼみ６を持つフィールド酸
化膜形状が得られる素子分離法であり、詳細は次の通り
である。まず、Ｐ型シリコン基板１の表面上に、アクテ
ィブ領域部を覆うようにパッド酸化膜２（２００〜３０
０Å厚）とSi3N4 膜３（１５００〜２０００Å厚）の２
層構造のパターンを形成する（図１（ａ））。次に、全
面に図１（ｂ）に示すように第２のSi3N4 膜４を１００
０〜１５００Å厚に形成し、これをエッチバックするこ
とにより、前記２層パターンの側壁に図１（ｃ）に示す
ようにSi3N4 膜のサイドウォール４ａを形成する。そし
てこのサイドウォール４ａとSi3N4 膜３をマスクとして
選択酸化を行って図１（ｄ）に示すようにシリコン基板
１の表面にフィールド酸化膜５を形成する。その後図２
（ａ）に示すようにサイドウォール４ａ，Si3N4 膜３お
よびパッド酸化膜２を除去して基板１のアクティブ領域
を露出させ、フレームドＬＯＣＯＳ法を終了する。この
終了時点でフィールド酸化膜５には、アクティブ領域エ
ッジで深さＨが数１のくぼみ６が発生する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In one embodiment, as shown in FIGS. 1 (a)-(d) and FIG. 2 (a), first, a framed LOCO is used.
The field oxide film 5 is formed on the surface of the P-type silicon substrate 1 by using the S method. Here, the framed LOCOS method refers to the side wall 4 of the Si 3 N 4 film in addition to the usual LOCOS method.
This is an element isolation method in which the bird's beak width W is reduced by adding a and a field oxide film shape having a depression 6 is obtained at the edge of the active region. The details are as follows. First, the pad oxide film 2 (200 to 30) is formed on the surface of the P-type silicon substrate 1 so as to cover the active region.
0 Å) and Si 3 N 4 film 3 (1500 to 2000 Å) 2
A pattern having a layered structure is formed (FIG. 1A). Then, a second Si 3 N 4 film 4 is formed on the entire surface by 100 as shown in FIG.
It is formed to a thickness of 0 to 1500 Å and is etched back to form a side wall 4a of a Si 3 N 4 film on the side wall of the two-layer pattern as shown in FIG. 1 (c). Then, selective oxidation is performed using the sidewalls 4a and the Si 3 N 4 film 3 as a mask to form a field oxide film 5 on the surface of the silicon substrate 1 as shown in FIG. Then Figure 2
As shown in (a), the sidewall 4a, the Si 3 N 4 film 3 and the pad oxide film 2 are removed to expose the active region of the substrate 1, and the framed LOCOS method is completed. At the end of this, a recess 6 having a depth H of 1 is formed in the field oxide film 5 at the edge of the active region.
【数１】 [Equation 1]
【０００９】以上のようにしてフレームドＬＯＣＯＳ法
でフィールド酸化膜５を形成したら、次にＩＴＦ法によ
るチャネルストップイオン注入（Ｂ+ イオンで、ドーズ
量は１〜５Ｅ１２cm-2、加速電圧は２００〜３００keV
）を基板全面に対して行い、図２（ｂ）に示すように
フィールド酸化膜５下およびアクティブ領域内にチャネ
ルストップ層７を形成する。この時、フィールド酸化膜
５のくぼみ６の形状を反映してチャネルストップ層７
は、アクティブ領域のエッジで他より深く形成される。After the field oxide film 5 is formed by the framed LOCOS method as described above, the channel stop ion implantation (B + ion, the dose amount is 1 to 5E12 cm -2 , and the accelerating voltage is 200 to 200) by the ITF method. 300keV
2) is performed on the entire surface of the substrate to form a channel stop layer 7 under the field oxide film 5 and in the active region as shown in FIG. At this time, the shape of the depression 6 of the field oxide film 5 is reflected to reflect the shape of the channel stop layer 7.
Are formed deeper than others at the edges of the active area.
【００１０】その後、くぼみ６が後工程で悪影響を及ぼ
さないように該くぼみ６の埋め込み工程を実施する。す
なわち、基板上の全面にＯ3 ＴＥＯＳ法により図２
（ｃ）に示すようにＣＶＤ酸化膜８を１０００〜２００
０Å成長させ、これをエッチバックして図２（ｄ）に示
すようにくぼみ６にのみ残すことで、該くぼみ６の埋め
込みを行う。しかる後、フィールド酸化膜５および埋め
込みＣＶＤ酸化膜８をマスクとしてイオン注入法で基板
１のアクティブ領域表面部に拡散層９を形成する。After that, a step of embedding the dent 6 is carried out so that the dent 6 does not adversely affect the subsequent step. That is, FIG. 2 on the entire surface of the substrate by O 3 TEOS method
As illustrated in FIG.
The cavities 6 are embedded by growing 0 Å and etching back this to leave only the cavities 6 as shown in FIG. 2D. Then, a diffusion layer 9 is formed on the surface of the active region of the substrate 1 by ion implantation using the field oxide film 5 and the buried CVD oxide film 8 as a mask.
【００１１】以上で、チャネルストップ層７がアクティ
ブ領域エッジで他より深くなった半導体装置が完成す
る。この半導体装置によれば、前記のようにチャネルス
トップ層７がアクティブ領域エッジで他より深くなって
いるので、拡散層９のエッジとチャネルストップ層７間
の距離を図２（ｄ）に示すようにＬ２と長くとることが
でき、拡散層９エッジでの接合容量（接合容量の線成
分）を少なくすることができる。As described above, a semiconductor device in which the channel stop layer 7 is deeper than others at the edge of the active region is completed. According to this semiconductor device, since the channel stop layer 7 is deeper than others at the edge of the active region as described above, the distance between the edge of the diffusion layer 9 and the channel stop layer 7 is as shown in FIG. L2 can be made long and the junction capacitance (line component of the junction capacitance) at the edge of the diffusion layer 9 can be reduced.
【００１２】図３（ａ）〜（ｄ）は、各方法でチャネル
ストップ層１０を形成した場合を示し、（ａ）はＩＴＦ
法を用いない場合、（ｂ）はＩＴＦ法を用いた場合、
（ｃ）は面成分の接合容量を抑えるため、ＩＴＦ法でイ
オン注入エネルギーを高くした場合、（ｄ）は上記この
発明の一実施例の場合である。また、これら（ａ）〜
（ｄ）の各方法における面成分接合容量を図４、線成分
接合容量を図５に示す。図４および図５から明らかなよ
うに、面成分は数２の順に大きく、線成分は数３の順に
大きいものとなる。3A to 3D show the case where the channel stop layer 10 is formed by each method, and FIG. 3A shows the ITF.
When the ITF method is used,
(C) is the case where the ion implantation energy is increased by the ITF method in order to suppress the junction capacitance of the surface component, and (d) is the case of the above-described embodiment of the present invention. Also, these (a) ~
FIG. 4 shows the surface component junction capacitance and FIG. 5 shows the line component junction capacitance in each method of (d). As is clear from FIG. 4 and FIG. 5, the surface component becomes large in the order of Formula 2, and the line component becomes large in the order of Formula 3.
【数２】 [Equation 2]
【数３】ａ＞ｂ＞ｃ＞ｄ 実際の素子では面成分の接合容量は素子の大きさからあ
まり問題となることはなく、線成分の接合容量の大小が
重要な要件であるが、この発明の一実施例の（ｄ）によ
れば４つの方法のうち最も線成分接合容量が少なく、有
効であることが分る。[Mathematical formula-see original document] a>b>c> d In an actual device, the junction capacitance of the plane component does not cause much problem due to the size of the device, and the magnitude of the junction capacitance of the line component is an important requirement. According to (d) of the embodiment of the invention, it is found that the line component junction capacitance is the smallest among the four methods and is effective.
【００１３】なお、上記一実施例において、フィールド
酸化膜５に生じたくぼみ６をＣＶＤ酸化膜８（マスク
材）で埋め込まない状態でイオン注入法で拡散層９の形
成を行ったとすると、該拡散層９が図２（ｄ）の点線の
ように伸びてチャネルストップ層７との間隔がＬ１と狭
くなってしまう。すなわち、チャネルストップ層７をア
クティブ領域エッジで他より深くした効果が得られなく
なる。これに対して上記一実施例のようにくぼみ６をＣ
ＶＤ酸化膜８で埋め込んだ上で拡散層９の形成を行え
ば、該拡散層９の不要な伸びをセルフアライン的手法で
防止でき、チャネルストップ層７をアクティブ領域エッ
ジで深くした効果を確実に得ることができる。また、く
ぼみ６を埋め込めば、段差が軽減されるので、上層のパ
ターニングなどにも有利となる。In the above embodiment, if the diffusing layer 9 is formed by the ion implantation method without filling the depression 6 formed in the field oxide film 5 with the CVD oxide film 8 (mask material), the diffusion is performed. The layer 9 extends as shown by the dotted line in FIG. 2D, and the distance between the layer 9 and the channel stop layer 7 is narrowed to L1. That is, the effect of making the channel stop layer 7 deeper at the edges of the active region cannot be obtained. On the other hand, as shown in the above-mentioned embodiment, the depression 6 is C
If the diffusion layer 9 is formed after being filled with the VD oxide film 8, unnecessary extension of the diffusion layer 9 can be prevented by a self-aligned method, and the effect of deepening the channel stop layer 7 at the edge of the active region is ensured. Obtainable. Further, if the recess 6 is embedded, the step difference is reduced, which is advantageous for patterning the upper layer.
【００１４】[0014]
【発明の効果】以上詳細に説明したようにこの発明によ
れば、ＩＴＦ法によるチャネルストップ層の形成におい
て、該チャネルストップ層をアクティブ領域のエッジで
他より深くしたので、拡散層エッジでの接合容量（接合
容量の線成分）を減少させることができる。その結果、
素子の高速動作が可能となる。As described above in detail, according to the present invention, in the formation of the channel stop layer by the ITF method, the channel stop layer is made deeper than the other in the edge of the active region, so that the junction at the edge of the diffusion layer is formed. The capacitance (line component of the junction capacitance) can be reduced. as a result,
High-speed operation of the device becomes possible.
【図１】この発明の一実施例の一部を示す工程断面図で
ある。FIG. 1 is a process sectional view showing a part of an embodiment of the present invention.
【図２】この発明の一実施例の一部を示す工程断面図で
ある。FIG. 2 is a process sectional view showing a part of an embodiment of the present invention.
【図３】各方法でチャネルストップ層を形成した半導体
装置の断面図である。FIG. 3 is a cross-sectional view of a semiconductor device in which a channel stop layer is formed by each method.
【図４】各方法でチャネルストップ層を形成した場合の
面成分接合容量比較特性図である。FIG. 4 is a surface component junction capacitance comparison characteristic diagram when a channel stop layer is formed by each method.
【図５】各方法でチャネルストップ層を形成した場合の
線成分接合容量比較特性図である。FIG. 5 is a line component junction capacitance comparison characteristic diagram when a channel stop layer is formed by each method.
１ Ｐ型シリコン基板 ３ Si3N4 膜 ４ａ サイドウォール ５ フィールド酸化膜 ６ くぼみ ７ チャネルストップ層 ８ ＣＶＤ酸化膜 ９ 拡散層1 P-type silicon substrate 3 Si 3 N 4 film 4a Side wall 5 Field oxide film 6 Recess 7 Channel stop layer 8 CVD oxide film 9 Diffusion layer
Claims (3)
領域内にも連続してチャネルストップ層を形成するよう
にした半導体装置において、 チャネルストップ層はアクティブ領域のエッジにおいて
選択的に深くなっていることを特徴とする半導体装置。1. A semiconductor device in which a channel stop layer is continuously formed not only under a field oxide film but also within an active region, wherein the channel stop layer is selectively deep at an edge of the active region. Semiconductor device.
エッジでくぼみをもつフレームドＬＯＣＯＳ法で半導体
基板に対してフィールド酸化膜を形成し、その状態で全
面にイオン注入を行って、アクティブ領域エッジで選択
的に深くなったチャネルストップ層を前記フィールド酸
化膜下およびアクティブ領域内に形成するようにした半
導体装置の製造方法。2. A field oxide film is formed on a semiconductor substrate by a framed LOCOS method in which the shape of the field oxide film has a depression at the edge of the active region, and ion implantation is performed on the entire surface in that state to select at the edge of the active region. A method of manufacturing a semiconductor device, wherein a channel stop layer deepened in depth is formed under the field oxide film and in an active region.
ＬＯＣＯＳ法で生じたアクティブ領域エッジのくぼみを
酸化膜で埋め込んだ上で、イオン注入法でアクティブ領
域表面部に拡散層を形成するようにした請求項２記載の
半導体装置の製造方法。3. After the formation of the channel stop layer, the recesses at the edges of the active region produced by the framed LOCOS method are filled with an oxide film, and then the diffusion layer is formed on the surface of the active region by the ion implantation method. Item 3. A method of manufacturing a semiconductor device according to item 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26697791A JPH0582515A (en) | 1991-09-19 | 1991-09-19 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26697791A JPH0582515A (en) | 1991-09-19 | 1991-09-19 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0582515A true JPH0582515A (en) | 1993-04-02 |
Family
ID=17438346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26697791A Pending JPH0582515A (en) | 1991-09-19 | 1991-09-19 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0582515A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5672538A (en) * | 1995-12-04 | 1997-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd | Modified locus isolation process in which surface topology of the locos oxide is smoothed |
| US5686346A (en) * | 1996-03-26 | 1997-11-11 | Advanced Micro Devices, Inc. | Method for enhancing field oxide thickness at field oxide perimeters |
| US5858860A (en) * | 1996-02-08 | 1999-01-12 | Samsung Electronics Co., Ltd. | Methods of fabricating field isolated semiconductor devices including step reducing regions |
| US7832999B2 (en) | 1999-07-27 | 2010-11-16 | Dai Nippon Toryo Co., Ltd. | Method of forming a coating layer on the surface of a molded product within a mold |
-
1991
- 1991-09-19 JP JP26697791A patent/JPH0582515A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5672538A (en) * | 1995-12-04 | 1997-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd | Modified locus isolation process in which surface topology of the locos oxide is smoothed |
| US5858860A (en) * | 1996-02-08 | 1999-01-12 | Samsung Electronics Co., Ltd. | Methods of fabricating field isolated semiconductor devices including step reducing regions |
| US5686346A (en) * | 1996-03-26 | 1997-11-11 | Advanced Micro Devices, Inc. | Method for enhancing field oxide thickness at field oxide perimeters |
| US7832999B2 (en) | 1999-07-27 | 2010-11-16 | Dai Nippon Toryo Co., Ltd. | Method of forming a coating layer on the surface of a molded product within a mold |
| US7837918B2 (en) | 1999-07-27 | 2010-11-23 | Dai Nippon Toryo Co., Ltd. | Method of forming a coating layer on the surface of a molded product within a mold |
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