JPH0575661A - Delay detection demodulation circuit - Google Patents

Delay detection demodulation circuit

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Publication number
JPH0575661A
JPH0575661A JP3233439A JP23343991A JPH0575661A JP H0575661 A JPH0575661 A JP H0575661A JP 3233439 A JP3233439 A JP 3233439A JP 23343991 A JP23343991 A JP 23343991A JP H0575661 A JPH0575661 A JP H0575661A
Authority
JP
Japan
Prior art keywords
circuit
complex
detection output
output
sign
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3233439A
Other languages
Japanese (ja)
Inventor
Fumiyuki Adachi
文幸 安達
Masaharu Ikura
雅治 伊倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP3233439A priority Critical patent/JPH0575661A/en
Publication of JPH0575661A publication Critical patent/JPH0575661A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To enable stable frequency drift correction without false lock even when fading is in existence such as mobile communication by obtaining a correction coefficient is obtained by the feedforward system. CONSTITUTION:This circuit is provided with a 2nd sign discrimination circuit 3 discriminating the sign of a real part and an imaginary part of a complex delay detection output outputted from a delay detection circuit 1, a complex conjugation circuit 4 as a correlation circuit obtaining a complex correction coefficient by the correlation between an output of the sign discrimination circuit 3 and an output of a delay detection circuit 1, a multiplier 5 and an averaging circuit 6 in addition to a frequency drift correction means. That is, the two sign discrimination circuits 2,3 are employed and the discrimination circuit 3 discriminates tentatively the sign of a detection output not corrected. The correction coefficient is obtained through the correlation calculation between the tentative sign discrimination and the detection output to correct the detection output. The other discrimination circuit 2 applies the main sign discrimination circuit to the corrected detection output.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はディジタル移動無線通信
に利用する。特に、搬送波周波数のドリフトによる遅延
検波復調回路の誤り率特性の劣化の改善に関する。BACKGROUND OF THE INVENTION The present invention is used in digital mobile radio communications. In particular, it relates to improvement of the deterioration of the error rate characteristic of the differential detection demodulation circuit due to the drift of the carrier frequency.

【０００２】[0002]

【従来の技術】ＰＳＫなどの位相変調方式では、復調の
ために同期検波や遅延検波が用いられる。同期検波を用
いると、遅延検波に比較して優れた誤り特性が得られ
る。しかし、同期検波を行うためには、搬送波を再生す
る必要がある。この搬送波再生のためには長いプリアン
ブル信号が必要となり、バースト伝送方式で利用すると
伝送効率が低下してしまう。これに対して遅延検波は、
搬送波再生を必要としないことから、バースト伝送に適
している。2. Description of the Related Art In a phase modulation system such as PSK, synchronous detection or differential detection is used for demodulation. Using synchronous detection provides superior error characteristics compared to differential detection. However, in order to perform the synchronous detection, it is necessary to regenerate the carrier wave. A long preamble signal is required for reproducing the carrier wave, and if it is used in the burst transmission method, the transmission efficiency is reduced. On the other hand, differential detection is
It is suitable for burst transmission because it does not require carrier recovery.

【０００３】しかし、遅延検波は、搬送波周波数が変動
すると誤り率特性が劣化やすい欠点がある。特に移動無
線通信では、移動機を小型かつ安価にするため、基地局
の無線機に比較して安定度の低い周波数発振器が用いら
れているので、遅延検波をそのまま使用することは現実
的ではなかった。However, the differential detection has a drawback that the error rate characteristic is easily deteriorated when the carrier frequency fluctuates. Especially in mobile radio communication, in order to make the mobile device small and inexpensive, a frequency oscillator having a lower stability than that of the radio device of the base station is used, so it is not realistic to use the differential detection as it is. It was

【０００４】このような課題を解決した遅延検波復調回
路の例を図２に示す。この従来例は本願出願人により出
願されたものであり、特開平３−８５０４４号公報に詳
しく開示されている。FIG. 2 shows an example of a differential detection demodulation circuit that solves such a problem. This conventional example was filed by the applicant of the present application and is disclosed in detail in Japanese Patent Laid-Open No. 3-85044.

【０００５】この従来例は、遅延検波出力を複素表示し
たとき、周波数ドリフトがあるとそれが検波出力の位相
の回転となって現れることを利用し、符号判定出力との
相関演算によってこの位相回転を打ち消す補正係数を求
め、検波出力から周波数ドリフトの影響を除去するもの
である。In this conventional example, when the differential detection output is displayed in a complex manner, if there is a frequency drift, it appears as a rotation of the phase of the detection output, and this phase rotation is performed by the correlation calculation with the code determination output. A correction coefficient for canceling is removed and the influence of frequency drift is removed from the detection output.

【０００６】遅延検波回路１は、受信位相変調波を遅延
検波して、同相検波出力を実数とし直交検波出力を虚数
とした複素遅延検波出力を生成する。この複素遅延検波
出力は、乗算器７を介して符号判定回路２に供給され
る。符号判定回路２は、複素遅延検波出力の実数部およ
び虚数部をそれぞれ符号判定して複素判定出力を生成す
る。遅延検波回路１の出力はまた、複素共役回路４に供
給される。複素共役回路４は、遅延検波回路１の出力の
複素共役をとり、それを乗算器５に供給する。乗算器５
は、この複素共役を符号判定回路２の出力に乗算し、乗
算結果を平均化回路６に供給する。平均化回路６は、乗
算器５の出力を平均化して複素補正係数を求め、その係
数を乗算器７に供給する。乗算器７は、遅延検波回路１
からの複素遅延検波出力に複素補正係数を乗算して、そ
の結果を符号判定回路２に供給する。The differential detection circuit 1 delay-detects the reception phase-modulated wave to generate a complex differential detection output in which the in-phase detection output is a real number and the quadrature detection output is an imaginary number. This complex differential detection output is supplied to the code determination circuit 2 via the multiplier 7. The sign determination circuit 2 determines the sign of each of the real number part and the imaginary part of the complex differential detection output and generates a complex determination output. The output of the differential detection circuit 1 is also supplied to the complex conjugate circuit 4. The complex conjugate circuit 4 takes the complex conjugate of the output of the differential detection circuit 1 and supplies it to the multiplier 5. Multiplier 5
Multiplies this complex conjugate by the output of the sign determination circuit 2 and supplies the multiplication result to the averaging circuit 6. The averaging circuit 6 averages the output of the multiplier 5 to obtain a complex correction coefficient and supplies the coefficient to the multiplier 7. The multiplier 7 is a differential detection circuit 1
The complex differential detection output from is multiplied by a complex correction coefficient, and the result is supplied to the code determination circuit 2.

【０００７】このようにして、検波出力を補正した後の
符号判定結果と検波出力との相関演算を行い、周波数ド
リフトで生じた検波出力の位相回転を打ち消すような位
相をもつ補正係数を求めて検波出力を補正する。この従
来例では、補正後の符号判定結果を用いているため、補
正係数の軽度が高く、優れた補正効果が得られる。In this manner, the correlation calculation between the code determination result after the detection output is corrected and the detection output is performed to obtain the correction coefficient having a phase that cancels the phase rotation of the detection output caused by the frequency drift. Correct the detection output. In this conventional example, since the code determination result after correction is used, the correction coefficient has a high degree of lightness, and an excellent correction effect can be obtained.

【０００８】[0008]

【発明が解決しようとする課題】しかし、移動通信など
のフェージングのある用途では、受信レベルがしばしば
熱雑音以下に落ち込むため、補正係数の位相、すなわち
推定した逆位相回転量が±π／４ラジアン以上に揺らい
でしまうことがある。このような場合には、それ以降の
補正係数の位相が正しい値から±π／２ラジアンはずれ
たところに誤って固定される現象、すなわち「フォール
スロック」が発生してしまう欠点があった。バースト受
信の場合には、補正係数を求める演算を受信毎にリセッ
トすることにより、フォールスロックを避けることがで
きる。しかし、連続受信の場合には、受信途中のフォー
ルスロックを検出して正しい補正係数に戻すための付加
回路が必要になってしまう。However, in applications with fading such as mobile communications, the reception level often drops below thermal noise, so the phase of the correction coefficient, that is, the estimated antiphase rotation amount is ± π / 4 radians. It may fluctuate more than that. In such a case, there has been a drawback that a phenomenon in which the phase of the correction coefficient after that is erroneously fixed at a position deviating from the correct value by ± π / 2 radians, that is, “false lock” occurs. In the case of burst reception, the false lock can be avoided by resetting the calculation for obtaining the correction coefficient every reception. However, in the case of continuous reception, an additional circuit is required to detect a false lock during reception and restore it to a correct correction coefficient.

【０００９】本発明は、このような問題を解決し、フォ
ールスロックが生じることなく検波出力から周波数ドリ
フトの影響を除去できる遅延検波復調回路を提供するこ
とを目的とする。An object of the present invention is to solve the above problems and to provide a differential detection demodulation circuit capable of removing the influence of frequency drift from the detection output without causing false lock.

【００１０】[0010]

【課題を解決するための手段】本発明の遅延検波復調回
路は、受信位相変調波を遅延検波して同相検波出力を実
数とし直交検波出力を虚数とした複素遅延検波出力を生
成する遅延検波回路と、その複素遅延検波出力に複素補
正係数を乗算して受信位相変調波の搬送波周波数ドリフ
トによってその複素遅延検波出力に生じた複素面上の変
位を補正する周波数ドリフト補正手段と、この周波数ド
リフト補正手段により補正された複素遅延検波出力の実
数部および虚数部を符号判定して複素判定出力を生成す
る第一の符号判定回路とを備えた遅延検波復調回路にお
いて、周波数ドリフト補正手段は、遅延検波回路の出力
した複素遅延検波出力の実数部および虚数部について符
号判定する第二の符号判定回路と、この第二の符号判定
回路の出力と遅延検波回路からの複素遅延検波出力との
相関により複素補正係数を求める相関回路とを含むこと
を特徴とする。SUMMARY OF THE INVENTION A differential detection demodulation circuit of the present invention is a differential detection circuit that delay-detects a received phase-modulated wave to generate a complex differential-detection output in which the in-phase detection output is a real number and the quadrature detection output is an imaginary number. And a frequency drift correction means for multiplying the complex differential detection output by a complex correction coefficient to correct the displacement on the complex plane generated in the complex differential detection output due to the carrier frequency drift of the received phase modulated wave, and the frequency drift correction In the differential detection demodulation circuit, the frequency drift correction means includes a first sign determination circuit that performs a sign determination of the real number part and the imaginary number part of the complex differential detection output corrected by the means to generate a complex determination output. A second sign judging circuit for judging the sign of the real part and the imaginary part of the complex differential detection output from the circuit, and the output and delay of this second sign judging circuit. Characterized in that it comprises a correlation circuit for obtaining a complex correction coefficient by the correlation of the complex differential detection output from the filter circuit.

【００１１】[0011]

【作用】フォールスロックが発生する原因は、補正され
た検波出力により相関演算を行って補正係数を求めるフ
ィードバック方式だからである。そこで本発明では、フ
ィードフォワード方式により補正係数を求める。すなわ
ち、二つの符号判定回路を用い、一方の判定回路では、
補正されていない検波出力を仮符号判定する。この仮符
号判定出力と検波出力との相関演算を行って補正係数を
求め、検波出力を補正する。もう一方の判定回路では、
この補正された検波出力について本符号判定する。The cause of the false lock is that the feedback method is used to obtain the correction coefficient by performing the correlation calculation with the corrected detection output. Therefore, in the present invention, the correction coefficient is obtained by the feedforward method. That is, using two code determination circuits, one determination circuit,
The uncorrected detection output is provisionally coded. A correlation coefficient is calculated between the temporary code determination output and the detection output to obtain a correction coefficient, and the detection output is corrected. In the other decision circuit,
The main code is determined for this corrected detection output.

【００１２】このようにフィードフォワード方式により
補正係数を求めるので、フォールスロックはまったく生
じない。したがって、移動通信のようにフェージングが
ある場合でも、フォールスロックのない安定した周波数
ドリフト補正を行うことができる。Since the correction coefficient is obtained by the feedforward method in this way, false lock does not occur at all. Therefore, even in the case of fading such as mobile communication, stable frequency drift correction without false lock can be performed.

【００１３】[0013]

【実施例】図１は本発明実施例の遅延検波復調回路を示
すブロック構成図である。1 is a block diagram showing a differential detection demodulation circuit according to an embodiment of the present invention.

【００１４】この実施例回路は、受信位相変調波を遅延
検波して同相検波出力を実数とし直交検波出力を虚数と
した複素遅延検波出力を生成する遅延検波回路１を備
え、その複素遅延検波出力に複素補正係数を乗算して受
信位相変調波の搬送波周波数ドリフトによってその複素
遅延検波出力に生じた複素面上の変位を補正する周波数
ドリフト補正手段として乗算器７を備え、周波数ドリフ
ト補正手段により補正された複素遅延検波出力の実数部
および虚数部を符号判定して複素判定出力を生成する第
一の符号判定回路２とを備える。The circuit of this embodiment is provided with a delay detection circuit 1 which delay-detects a received phase-modulated wave to generate a complex delay-detection output in which the in-phase detection output is a real number and the quadrature detection output is an imaginary number. Is multiplied by a complex correction coefficient to correct the displacement on the complex plane generated in the complex differential detection output by the carrier frequency drift of the received phase modulated wave, and a multiplier 7 is provided as the frequency drift correction means, and the frequency drift correction means corrects And a first sign judging circuit 2 for sign judging the real part and the imaginary part of the complex differential detection output thus generated to generate a complex judgment output.

【００１５】ここで本実施例の特徴とするところは、周
波数ドリフト補正手段にさらに、遅延検波回路１の出力
した複素遅延検波出力の実数部および虚数部について符
号判定する第二の符号判定回路３と、この符号判定回路
３の出力と遅延検波回路１からの複素遅延検波出力との
相関により複素補正係数を求める相関回路として複素共
役回路４、乗算器５および平均化回路６を備えたことに
ある。Here, the feature of this embodiment is that the frequency drift correction means further includes a second code determination circuit 3 for determining the sign of the real part and the imaginary part of the complex differential detection output output from the differential detection circuit 1. And a complex conjugate circuit 4, a multiplier 5 and an averaging circuit 6 as a correlation circuit for obtaining a complex correction coefficient by the correlation between the output of the code determination circuit 3 and the complex differential detection output from the differential detection circuit 1. is there.

【００１６】複素共役回路４は、遅延検波回路１の出力
の複素共役を求める。乗算器５は、この複素共役出力を
符号判定回路３の仮符号判定出力に乗算する。平均化回
路６は、乗算器５の出力を平均化し、補正係数を出力す
る。この補正係数は複素数であり、その位相項が周波数
ドリフトによる位相回転量のマイナスの推定値になる。
したがって、この補正係数を乗算器７により遅延検波回
路１の出力に乗算することにより、周波数ドリフトによ
る位相回転が打ち消される。符号判定回路２では、この
位相回転が打ち消された複素遅延検波出力を符号判定し
て復調データを出力する。The complex conjugate circuit 4 obtains the complex conjugate of the output of the differential detection circuit 1. The multiplier 5 multiplies the complex conjugate output by the temporary code determination output of the code determination circuit 3. The averaging circuit 6 averages the output of the multiplier 5 and outputs a correction coefficient. This correction coefficient is a complex number, and its phase term becomes a negative estimated value of the amount of phase rotation due to frequency drift.
Therefore, by multiplying the output of the differential detection circuit 1 by the multiplier 7 with this correction coefficient, the phase rotation due to the frequency drift is canceled. The sign judging circuit 2 judges the sign of the complex differential detection output whose phase rotation has been canceled, and outputs demodulated data.

【００１７】ここで、４相差動位相変調方式（ＱＤＰＳ
Ｋ）の場合の動作例を説明する。Here, a four-phase differential phase modulation system (QDPS
An operation example in the case of K) will be described.

【００１８】サンプリング時点ｔ＝ｎＴにおける遅延検
波回路１の複素遅延検波出力ｒn は、 ｒn ＝Ｒn・ｖn・ｅｘｐ〔ｊ ２π Δｆ・Ｔ〕＋雑音 ……（１） と表される。ここで、２πΔｆ・Ｔは周波数ドリフトに
よる位相回転量であり、Δｆが周波数ドリフト、Ｔがシ
ンボル長、ｖn は複素表示した送信符号であり、ｖn ＝
（±１±ｊ）／√２、Ｒn は遅延検波出力の信号振幅で
ある。符号判定回路３により送信符号と判定された結果
をｖn ′とすると、乗算器５では、これに遅延検波出力
ｒn の複素共役ｒ* nを乗算する。平均化回路６では、乗
算器５の出力を平均化処理し、 ｗn ＝（１−α）ｗn-1 ＋αｒ* n-1 ｖn-1′ ……（２） により複素補正係数ｗn を求める。ただし、０＜α＜１
である。The complex differential detection output r n of the differential detection circuit 1 at the sampling time t = nT is expressed as r n = R n · v n · exp [j 2π Δf · T] + noise (1) .. Here, 2πΔf · T is a phase rotation amount due to frequency drift, Δf is frequency drift, T is a symbol length, v n is a transmission code expressed in complex, and v n =
(± 1 ± j) / √2, R n is the signal amplitude of the differential detection output. Assuming that the result determined to be the transmission code by the code determination circuit 3 is v n ′, the multiplier 5 multiplies this by the complex conjugate r * n of the differential detection output r n . In the averaging circuit 6, the output of the multiplier 5 is averaged, and the complex correction coefficient w n is obtained by: w n = (1−α) w n−1 + αr * n−1 v n−1 ′ (2) Ask for. However, 0 <α <1
Is.

【００１９】符号判定回路３の判定誤りが小さければ、
ほとんどの場合にｖn ′＝ｖn となり、 ｒ* n ｖn′＝Ｒn・｜ｖn ｜2 ・ｅｘｐ〔−ｊ ２π Δｆ・Ｔ〕 ＝Ｒn・ｅｘｐ〔−ｊ ２π Δｆ・Ｔ〕 ……（３） となる。したがって、その平均値である複素補正係数ｗ
n の位相Δφもまた、周波数ドリフトによる位相回転の
マイナスの値をもつ。この複素補正係数ｗn を乗算器７
により遅延検波回路１の出力に乗算すれば、周波数ドリ
フトによって生じた式（１）に示した位相回転を補正で
きる。なお、このような相関演算による周波数ドリフト
の補正範囲は、｜Δｆ｜＜１／８Ｔである。If the decision error of the code decision circuit 3 is small,
V n '= v n next, r * n v n' in most cases = R n · | v n | 2 · exp [-j 2π Δf · T] = R n · exp [-j 2π Δf · T] … (3) Therefore, the complex correction coefficient w which is the average value thereof
The phase Δφ of n also has a negative value of the phase rotation due to frequency drift. This complex correction coefficient w n is multiplied by the multiplier 7
Thus, by multiplying the output of the differential detection circuit 1, the phase rotation shown in the equation (1) caused by the frequency drift can be corrected. The correction range of the frequency drift by such a correlation calculation is | Δf | <1 / 8T.

【００２０】ところで、遅延検波出力の雑音のため、複
素補正係数は平均値の周りに分布する。したがって、確
率的には、複素補正係数の位相Δφは−２πΔｆ・Ｔを
中心に分布することになる。そこで、ε＝Δφ＋２πΔ
ｆ・Ｔを推定位相誤差と呼ぶことにする。By the way, due to the noise of the differential detection output, the complex correction coefficient is distributed around the average value. Therefore, stochastically, the phase Δφ of the complex correction coefficient is distributed around −2πΔf · T. Therefore, ε = Δφ + 2πΔ
Let f · T be called the estimated phase error.

【００２１】図２に示した従来例では、検波出力を補正
した後の符号判定結果（従来例の場合には符号判定回路
は一つしかなく、本実施例の本符号判定に相当する）と
検波出力の複素共役との相関演算により補正係数を求め
ていた。したがって、補正係数の推定位相誤差が±π／
４ラジアンを越えると、符号誤りが急激に増加する。こ
れは、補正された検波出力の位相の中心点が、正しい符
号判定領域、すなわち送信符号の位相を基準にして±π
／４以内の領域から、隣の領域に移動してしまうからで
ある。一度この状態になると、相関回路では、正しい符
号の隣の判定領域に属する間違った符号をもとに補正係
数を求めることになる。このため、補正係数の位相誤差
は±π／２に収束し、そこに固定される。すなわち、フ
ォールスロックが発生する。そして、正しい符号の隣の
判定領域の符号が送信されたものと誤判定し続けてしま
うことになる。確率的には、補正係数の位相誤差がπに
フォールスロックされる場合もある。In the conventional example shown in FIG. 2, the code determination result after the detection output is corrected (in the conventional example, there is only one code determination circuit, which corresponds to the main code determination in this embodiment). The correction coefficient is obtained by the correlation calculation with the complex conjugate of the detection output. Therefore, the estimated phase error of the correction coefficient is ± π /
If it exceeds 4 radians, the number of code errors increases sharply. This is because the center point of the phase of the corrected detection output is ± π based on the correct code judgment area, that is, the phase of the transmission code.
This is because the area within / 4 moves to the adjacent area. Once in this state, the correlation circuit obtains the correction coefficient based on the wrong code belonging to the determination area next to the correct code. Therefore, the phase error of the correction coefficient converges to ± π / 2 and is fixed there. That is, false lock occurs. Then, it continues to erroneously determine that the code in the determination area adjacent to the correct code has been transmitted. Probabilistically, the phase error of the correction coefficient may be false-locked to π.

【００２２】これに対して本実施例では、補正された検
波出力を利用しないので、相関演算に用いる検波出力の
位相の中心点には変動がなく、常に２πΔｆ・Ｔを中心
に分布する。したがって、周波数ドリフトが｜Δｆ｜＜
１／８Ｔであれば、フォールスロックは全く発生しな
い。On the other hand, in this embodiment, since the corrected detection output is not used, the center point of the phase of the detection output used for the correlation calculation does not change and is always distributed around 2πΔf · T. Therefore, the frequency drift is | Δf | <
With 1 / 8T, no false lock occurs.

【００２３】[0023]

【発明の効果】以上説明したように、本発明の遅延検波
復調回路は、フェージングのある移動通信のような劣悪
な伝送条件のもとでも安定に動作し、フォールスロック
のない周波数ドリフト補正を実現できる効果がある。As described above, the differential detection demodulation circuit of the present invention operates stably even under bad transmission conditions such as mobile communication with fading, and realizes frequency drift correction without false lock. There is an effect that can be done.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明実施例の遅延検波復調回路を示すブロッ
ク構成図。FIG. 1 is a block diagram showing a differential detection demodulation circuit according to an embodiment of the present invention.

【図２】従来例遅延検波復調回路のブロック構成図。FIG. 2 is a block diagram of a conventional differential detection demodulation circuit.

【符号の説明】[Explanation of symbols]

１ 遅延検波回路 ２、３ 符号判定回路 ４ 複素共役回路 ５、７ 乗算器 ６ 平均化回路 1 Delay detection circuit 2, 3 Code determination circuit 4 Complex conjugate circuit 5, 7 Multiplier 6 Averaging circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 受信位相変調波を遅延検波して同相検波
出力を実数とし直交検波出力を虚数とする複素遅延検波
出力を生成する遅延検波回路と、 その複素遅延検波出力に複素補正係数を乗算して、受信
位相変調波の搬送波周波数ドリフトによってその複素遅
延検波出力に生じた複素面上の変位を補正する周波数ド
リフト補正手段と、 この周波数ドリフト補正手段により補正された複素遅延
検波出力の実数部および虚数部を符号判定して複素判定
出力を生成する第一の符号判定回路とを備えた遅延検波
復調回路において、 前記周波数ドリフト補正手段は、 前記遅延検波回路の複素遅延検波出力の実数部および虚
数部について符号判定する第二の符号判定回路と、 この第二の符号判定回路の出力と前記遅延検波回路から
の複素遅延検波出力との相関により複素補正係数を求め
る相関回路とを含むことを特徴とする遅延検波復調回
路。1. A delay detection circuit that delay-detects a received phase-modulated wave to generate a complex differential detection output in which the in-phase detection output is a real number and the quadrature detection output is an imaginary number, and the complex differential detection output is multiplied by a complex correction coefficient. Then, the frequency drift correction means for correcting the displacement on the complex plane generated in the complex differential detection output by the carrier frequency drift of the reception phase modulated wave, and the real part of the complex differential detection output corrected by the frequency drift correction means. In the differential detection demodulation circuit including a first sign determination circuit that determines the sign of the imaginary part and generates a complex determination output, the frequency drift correction means is a real part of the complex differential detection output of the differential detection circuit, and A second sign judging circuit for judging the sign of the imaginary part, and an output of the second sign judging circuit and a complex delay detection output from the delay detecting circuit. Delay detection demodulation circuit, characterized in that it comprises a correlation circuit for obtaining a complex correction factor by Seki.
JP3233439A 1991-09-12 1991-09-12 Delay detection demodulation circuit Pending JPH0575661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3233439A JPH0575661A (en) 1991-09-12 1991-09-12 Delay detection demodulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3233439A JPH0575661A (en) 1991-09-12 1991-09-12 Delay detection demodulation circuit

Publications (1)

Publication Number Publication Date
JPH0575661A true JPH0575661A (en) 1993-03-26

Family

ID=16955063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3233439A Pending JPH0575661A (en) 1991-09-12 1991-09-12 Delay detection demodulation circuit

Country Status (1)

Country Link
JP (1) JPH0575661A (en)

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