JPH0575551A - Clock signal transmitting circuit - Google Patents
Clock signal transmitting circuitInfo
- Publication number
- JPH0575551A JPH0575551A JP23140891A JP23140891A JPH0575551A JP H0575551 A JPH0575551 A JP H0575551A JP 23140891 A JP23140891 A JP 23140891A JP 23140891 A JP23140891 A JP 23140891A JP H0575551 A JPH0575551 A JP H0575551A
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- resistor
- circuit
- clock
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Noise Elimination (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、自動車電話機、携帯電
話機に利用するクロック信号伝送回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal transmission circuit used in automobile telephones and mobile telephones.
【0002】[0002]
【従来の技術】従来、この種のクロック信号伝送回路
は、クロック信号発生回路と、このクロック信号発生回
路から出力されるクロック信号で動作するクロック信号
受動回路と、この間を直接接続する接続線であるクロッ
ク伝送線路から構成されている。2. Description of the Related Art Conventionally, a clock signal transmission circuit of this type is composed of a clock signal generation circuit, a clock signal passive circuit which operates by a clock signal output from the clock signal generation circuit, and a connecting line which directly connects these circuits. It consists of a clock transmission line.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、従来例
のクロック信号伝送回路では、クロック信号発生回路の
出力インピーダンスとクロック信号受動回路の入力イン
ピーダンスが一致しない。このため、クロック伝送線路
上の不整合でクロック信号周波数が歪み、整数倍の高調
波が発生して、周囲に輻射されてしまい、この不要波で
装置内の回路の誤動作が生じ、また、周囲の機器で雑音
が発生する等の問題があった。However, in the conventional clock signal transmission circuit, the output impedance of the clock signal generation circuit and the input impedance of the clock signal passive circuit do not match. For this reason, the clock signal frequency is distorted due to mismatch on the clock transmission line, and harmonics that are an integral multiple are generated and are radiated to the surroundings. There was a problem such as noise being generated in the device.
【0004】本発明は、この課題を解決するものであ
り、クロック信号伝送線路からクロック信号周波数の整
数倍の高調波の輻射を減少できる優れたクロック信号伝
送回路を提供することを目的とする。An object of the present invention is to solve this problem, and an object of the present invention is to provide an excellent clock signal transmission circuit capable of reducing radiation of harmonics that are an integral multiple of the clock signal frequency from the clock signal transmission line.
【0005】[0005]
【課題を解決するための手段】この目的を解決するため
に、本発明のクロック信号伝送回路は、クロック信号発
生回路と、クロック信号発生回路から出力されるクロッ
ク信号で動作するクロック信号受動回路と、クロック信
号発生回路のクロック信号出力端とクロック信号受動回
路のクロック信号入力端との間に直列に抵抗器が配置さ
れるクロック信号伝送線路とを備えるものである。In order to solve this object, a clock signal transmission circuit of the present invention comprises a clock signal generation circuit and a clock signal passive circuit which operates with a clock signal output from the clock signal generation circuit. A clock signal transmission line in which a resistor is arranged in series is provided between the clock signal output end of the clock signal generation circuit and the clock signal input end of the clock signal passive circuit.
【0006】[0006]
【作用】したがって、本発明のクロック信号伝送回路に
よれば、抵抗器によりクロック伝送線路のインピーダン
スと、クロック信号受動回路の入力インピーダンスとが
整合するため、クロック伝送線路からのクロック信号周
波数の整数倍の高調波の輻射を減少させることができ
る。Therefore, according to the clock signal transmission circuit of the present invention, since the impedance of the clock transmission line and the input impedance of the clock signal passive circuit are matched by the resistor, it is an integral multiple of the clock signal frequency from the clock transmission line. It is possible to reduce the radiation of higher harmonic waves.
【0007】[0007]
【実施例】以下、本発明のクロック信号伝送回路の実施
例を図面にもとづいて説明する。Embodiments of a clock signal transmission circuit according to the present invention will be described below with reference to the drawings.
【0008】図1は実施例の構成を示している。図1に
おいて、11はクロック信号発生回路であり、12は、
クロック信号発生回路11のクロック信号出力端に、一
端が接続される抵抗器である。13、14、15は、そ
れぞれクロック信号受動回路であり、抵抗器12の他端
が、それぞれのクロック信号入力端に接続されて、クロ
ック信号発生回路11からのクロック信号が供給されて
いる。抵抗器12はクロック信号受動回路13、14、
15の入力インピーダンスに整合する値に設定する。FIG. 1 shows the configuration of the embodiment. In FIG. 1, 11 is a clock signal generation circuit, and 12 is
It is a resistor whose one end is connected to the clock signal output terminal of the clock signal generation circuit 11. Reference numerals 13, 14, and 15 are clock signal passive circuits, respectively, and the other end of the resistor 12 is connected to each clock signal input end, and the clock signal from the clock signal generation circuit 11 is supplied. The resistor 12 is a clock signal passive circuit 13, 14,
Set to a value that matches the input impedance of 15.
【0009】以上の構成における動作について説明す
る。抵抗器12からクロック信号受動回路13、14、
15のそれぞれのクロック信号入力端までのクロック信
号伝送線路のインピーダンスがクロック信号受動回路の
入力インピーダンスに近づき、クロック信号発生回路1
1のクロック信号出力端と、クロック信号受動回路1
3、14、15のクロック信号入力端と間のインピーダ
ンスが整合できることになる。The operation of the above configuration will be described. From the resistor 12 to the clock signal passive circuit 13, 14,
The impedance of the clock signal transmission line up to the respective clock signal input ends of 15 approaches the input impedance of the clock signal passive circuit, and the clock signal generation circuit 1
1 clock signal output terminal and clock signal passive circuit 1
The impedance between the clock signal input terminals 3, 14, and 15 can be matched.
【0010】このように、抵抗器12からクロック信号
受動回路13、14、15のそれぞれの入力端までのク
ロック信号伝送線路のインピーダンスがクロック信号受
動回路の入力インピーダンスに近づくため、不整合が阻
止されて、クロック伝送線路からのクロック信号周波数
の整数倍の高調波の輻射が減少でき、この不要波による
装置内の回路の誤動作、および周囲の機器における雑音
発生等の悪影響を阻止できる。As described above, since the impedance of the clock signal transmission line from the resistor 12 to the respective input ends of the clock signal passive circuits 13, 14, 15 approaches the input impedance of the clock signal passive circuit, the mismatch is prevented. As a result, radiation of harmonics that are an integral multiple of the frequency of the clock signal from the clock transmission line can be reduced, and adverse effects such as malfunction of circuits in the device and noise generation in surrounding equipment due to this unnecessary wave can be prevented.
【0011】なお、この実施例では、三つのクロック信
号受動回路13、14、15に、一つの抵抗器12を通
じてクロック信号を供給しているが、これに限ることな
く、4以上のクロック信号受動回路にクロック信号を供
給しても良く、また、クロック信号受動回路のそれぞれ
の入力端に、直列に抵抗器を接続する構成にしても、同
様の作用効果が得られる。この場合、インピーダンスが
整合する値の抵抗器を配置すれば良い。In this embodiment, the clock signal is supplied to the three clock signal passive circuits 13, 14 and 15 through one resistor 12, but the present invention is not limited to this, and four or more clock signal passive circuits are provided. A clock signal may be supplied to the circuit, and a similar effect can be obtained even if a resistor is connected in series to each input terminal of the clock signal passive circuit. In this case, it suffices to dispose a resistor whose impedance is matched.
【0012】[0012]
【発明の効果】以上の説明から明らかなように、本発明
のクロック信号伝送回路は、抵抗器をクロック伝送線路
に直列に配置し、この抵抗器によりクロック伝送線路の
インピーダンスと、クロック信号受動回路の入力インピ
ーダンスとが整合するようにしているため、クロック信
号周波数の整数倍の高調波の輻射を減少させることがで
きるという効果を有する。As is apparent from the above description, in the clock signal transmission circuit of the present invention, the resistor is arranged in series with the clock transmission line, and the impedance of the clock transmission line and the clock signal passive circuit are provided by this resistor. Since the input impedance is matched with the input impedance, the radiation of harmonics that are an integral multiple of the clock signal frequency can be reduced.
【図1】本発明のクロック信号伝送回路の構成を示すブ
ロック図FIG. 1 is a block diagram showing a configuration of a clock signal transmission circuit of the present invention.
11 クロック信号発生回路 12 抵抗器 13、14、15 クロック信号受動回路 11 Clock Signal Generation Circuit 12 Resistors 13, 14, 15 Clock Signal Passive Circuit
Claims (1)
信号発生回路から出力されるクロック信号で動作するク
ロック信号受動回路と、前記クロック信号発生回路のク
ロック信号出力端と前記クロック信号受動回路のクロッ
ク信号入力端との間に直列に抵抗器が配置されるクロッ
ク信号伝送線路とを備えたクロック信号伝送回路。1. A clock signal generation circuit, a clock signal passive circuit that operates with a clock signal output from the clock signal generation circuit, a clock signal output terminal of the clock signal generation circuit, and a clock signal of the clock signal passive circuit. A clock signal transmission circuit comprising a clock signal transmission line in which a resistor is arranged in series with an input end.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23140891A JPH0575551A (en) | 1991-09-11 | 1991-09-11 | Clock signal transmitting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23140891A JPH0575551A (en) | 1991-09-11 | 1991-09-11 | Clock signal transmitting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0575551A true JPH0575551A (en) | 1993-03-26 |
Family
ID=16923136
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23140891A Pending JPH0575551A (en) | 1991-09-11 | 1991-09-11 | Clock signal transmitting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0575551A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5399996A (en) * | 1993-08-16 | 1995-03-21 | At&T Global Information Solutions Company | Circuit and method for minimizing electromagnetic emissions |
US6520888B1 (en) | 1999-10-15 | 2003-02-18 | Nsk Ltd. | Loading cam apparatus for toroidal type continuously variable transmission |
US7750527B2 (en) | 2006-03-16 | 2010-07-06 | Nissan Motor Co., Ltd. | Motor/generator |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01213017A (en) * | 1988-02-22 | 1989-08-25 | Murata Mfg Co Ltd | Noise filter |
-
1991
- 1991-09-11 JP JP23140891A patent/JPH0575551A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01213017A (en) * | 1988-02-22 | 1989-08-25 | Murata Mfg Co Ltd | Noise filter |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5399996A (en) * | 1993-08-16 | 1995-03-21 | At&T Global Information Solutions Company | Circuit and method for minimizing electromagnetic emissions |
US6520888B1 (en) | 1999-10-15 | 2003-02-18 | Nsk Ltd. | Loading cam apparatus for toroidal type continuously variable transmission |
US7750527B2 (en) | 2006-03-16 | 2010-07-06 | Nissan Motor Co., Ltd. | Motor/generator |
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